微处理器温度感知的任务调度算法研究
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摘要
随着集成电路特征尺寸的不断缩小以及集成度的不断提高，处理器的功耗密度和温度持续上升。过高的温度不仅降低了芯片的可靠性，同时也对处理器的性能产生了很大的影响，温度问题已经成为限制微处理器持续发展的重要因素。而一些新兴的技术（如单芯片多处理器、3D堆叠技术等）则进一步增加了芯片的功耗密度，从而使得温度问题变得更加严峻。
芯片的温度在时间和空间上的巨大变化也给处理器的封装和冷却带来了巨大挑战，传统的散热方法已经越来越不能满足当前高性能微处理器对散热的要求。为了解决这一问题，目前普遍采用基于硬件的动态热管理技术（Hardware DynamicThermal Management，简称HW DTM）来限制处理器的温度，即一旦硬件检测到处理器的温度达到某一预定的阈值，就启动相应的温度管理机制（比如降频、降压、断电等）来降低处理器的温度，保护处理器不被损坏。但是，HW DTM技术会增加程序的运行时间，降低系统的吞吐率，最终降低处理器的性能。
本文的目标就是要尽可能地消除不必要的HW DTM触发事件，保护芯片的性能不受温度管理机制的影响。本文系统地研究了基于温度感知设计的一系列关键技术，针对已有工作的不足，提出了三种操作系统级的温度感知任务调度技术来避免HW DTM。本文主要的工作和创新点包括：
第一，全面深入地分析了微处理器温度感知设计技术，从不同层次、不同角度对现有的温度感知设计技术进行了总结，分析了这些技术的优缺点。
第二，进行温度感知任务调度需要在线进行功耗与温度计算，本文总结了现有的功耗估算模型和温度模型，对这些模型的特点进行了分析，讨论了功耗获取和温度计算的方法。
第三，针对单核处理器，提出了一种贪婪调度算法GSA，在处理器温度不超过阈值温度的前提下让热的任务先运行，充分利用处理器的时间“温度余量”，将处理器较早提升到一个温度较高的状态，使处理器能更快地耗散热量，从而减少DTM触发次数，提升系统的性能。实验结果表明，GSA与基准调度器相比，在低、中、高温环境下的SPEC2K负载以及中温环境下的非SPEC负载，DTM分别可以降低9.9%~82%（平均47.1%）、8.8%~73.8%（平均41.1%）、2.9%~58.7%（平均31.7%）和5.9%~45.5（平均31%），性能可以分别提升4.2%、5.2%、4.7%和3.7%；与随机算法、优先权算法、MinTemp+算法以及TreshHot算法相比，GSA均有不同程度的性能提升。
第四，针对2D CMP，提出了TSTB调度算法。CMP的自然分簇结构为温度管理提供了新的途径，调度一个热的任务到一个冷的核上比调度一个热的任务到热的核上，具有更低的峰值温度。TSTB利用CMP在时间和空间上的温度变化，通过改变冷热任务的执行顺序来挖掘CMP每个核内的时间“温度余量”，并将冷热任务安排到温度适合的核上运行来挖掘空间“温度余量”，减少热紧急事件，提升系统性能。实验结果表明，相比于基准调度算法，TSTB算法使TET（ThermalEmergency Time）降低了8.3%~91.5%，平均降低了48.3%，使性能提升了2.47%~6.58%（平均4.62%）；TSTB相比于随机调度算法、轮转调度算法、平衡算法以及ThresHot算法等，均有不同程度的性能提升。
第五，针对3D CMP，提出了HTBS调度算法。分析了3D CMP的温度特性，将垂直堆叠的核当作一个核堆，让任务的功耗在核堆之间进行平衡，同时将热的任务放在离热沉近的核上运行，以加速散热。当某个核出现过热时，对核堆中功耗最密集的处理器核进行DTM，使温度迅速降低。实验结果表明，相比于基准调度算法，HTBS算法使TET降低了8.4%~96.2%，平均降低了54.7%，获得了5.99%的性能提升；HTBS算法相比于随机调度、轮转调度、核间温度平衡调度以及堆间温度平衡调度算法，均有不同程度的性能提升。
With continuous IC (Integrated Circuit) technology size scaling, themicroprocessor’s power density and temperature continues to rise. The increase in dietemperature results in reduced performance and reliability. There are also emergingtechnologies, such as chip multi-processor and3D stacking technology, which canexacerbate the thermal condition on modern processors.
The chip’s temperature tremendous change in time and space also poses a greatchallenge to the processor’s package and cooling. Existing cooling methodologies arehard pressed to alleviate the high temperatures associated with current generation highperformance processors. Current processors mainly use hardware dynamic temperaturemanagement to alleviate the power and temperature issues. Once the processor'stemperature reaches a predetermined threshold value, it starts the appropriatetemperature management mechanisms (such as dynamic voltage and frequency scaling,DVFS) to reduce the temperature of the processor, and prevent the processor fromdamage. However, these mechanisms have the disadvantage of high cost and willjeopardize the processor’s performance.
Our goal is to eliminate unnecessary HW DTM as much as possible and improvethe chip’s performance. This paper studied the temperature-aware design technologiessystematically. Against the shortage of the existing method, we proposed three newtechnologies to avoid the unnecessary HW DTM. The main contributions of this paperare as follows:
First, this paper summarized the existing temperature-aware design techniques fromdifferent levels and different angles, and analyzed the advantages and disadvantages ofthese techniques.
Second, the temperature-aware task scheduling techniques needs power andtemperature calculation. This paper summarized the existing power estimation model andtemperature model, and then analyzed the characteristics of these models. We alsodiscussed how to obtain the power consumption and calculate the processor’stemperature.
Third, to improve the performance of the single-core processors, which is harmed bythe thermal overshoots and the HW DTMs, we propose an algorithm named GSA. Wefind that if the processor reaches a high temperature state sooner, then the processor willbe able to heat dissipation faster. Based on this fact, GSA schedules the hot jobs beforethe cool jobs as long as it does not exceed the threshold. By fully use of the processortemporal "temperature margin" to reduce the number of DTM trigger, the performance ofthe system will be improved. Plenty of experiments are made. The DTM reduction rangesare9.9-82%(47.1%on average),8.8-73.8%(41%on average),2.9-58.7%(31.7%on average), and5.9-45.5%(31%) for mild, medium, and harsh thermal environment, andnon-SPEC benchmarks in medium environment respectively and the CPU throughputwas improved by up to4.2%,5.2%,4.7%,3.7%on average respectively.
Fourth, we proposed TSTB algorithm for the2D CMP. CMP’s natural clusteringstructure offers a new approach for the temperature management. Scheduling a hot task toa cold core can lower the processor’s temperature. TSTB utilize CMP’s temporal andspatial temperature changes and arrange the order of execution of the hot and cold tasksand schedule the task to the appropriate core to reduce thermal emergencies, and improvesystem performance. Experimental results showed that the TSTB algorithm can reducethe TET by8.3%-91.5%(48.3%on average), and the CPU throughput was improved by2.47%-6.58%(4.62%on average).
Finally, we proposed TSTB algorithm for the3D CMP. This paper analyzed the3DCMP temperature characteristics. First, the vertically stacked core should be treated as acore stack. The power of jobs is balanced among the core stacks instead of the individualcores. Second, the hot jobs are moved close to the heat sink to expedite heat dissipation.Third, when the thermal emergencies happen, the most power-intensive job in a corestack is penalized in order to lower the temperature quickly. Experimental results showedthat the HTBS algorithm can reduce the TET by8.4%-96.2%(54.7%on average), andthe CPU throughput was improved by5.99%on average.
芯片的温度在时间和空间上的巨大变化也给处理器的封装和冷却带来了巨大挑战，传统的散热方法已经越来越不能满足当前高性能微处理器对散热的要求。为了解决这一问题，目前普遍采用基于硬件的动态热管理技术（Hardware DynamicThermal Management，简称HW DTM）来限制处理器的温度，即一旦硬件检测到处理器的温度达到某一预定的阈值，就启动相应的温度管理机制（比如降频、降压、断电等）来降低处理器的温度，保护处理器不被损坏。但是，HW DTM技术会增加程序的运行时间，降低系统的吞吐率，最终降低处理器的性能。
本文的目标就是要尽可能地消除不必要的HW DTM触发事件，保护芯片的性能不受温度管理机制的影响。本文系统地研究了基于温度感知设计的一系列关键技术，针对已有工作的不足，提出了三种操作系统级的温度感知任务调度技术来避免HW DTM。本文主要的工作和创新点包括：
第一，全面深入地分析了微处理器温度感知设计技术，从不同层次、不同角度对现有的温度感知设计技术进行了总结，分析了这些技术的优缺点。
第二，进行温度感知任务调度需要在线进行功耗与温度计算，本文总结了现有的功耗估算模型和温度模型，对这些模型的特点进行了分析，讨论了功耗获取和温度计算的方法。
第三，针对单核处理器，提出了一种贪婪调度算法GSA，在处理器温度不超过阈值温度的前提下让热的任务先运行，充分利用处理器的时间“温度余量”，将处理器较早提升到一个温度较高的状态，使处理器能更快地耗散热量，从而减少DTM触发次数，提升系统的性能。实验结果表明，GSA与基准调度器相比，在低、中、高温环境下的SPEC2K负载以及中温环境下的非SPEC负载，DTM分别可以降低9.9%~82%（平均47.1%）、8.8%~73.8%（平均41.1%）、2.9%~58.7%（平均31.7%）和5.9%~45.5（平均31%），性能可以分别提升4.2%、5.2%、4.7%和3.7%；与随机算法、优先权算法、MinTemp+算法以及TreshHot算法相比，GSA均有不同程度的性能提升。
第四，针对2D CMP，提出了TSTB调度算法。CMP的自然分簇结构为温度管理提供了新的途径，调度一个热的任务到一个冷的核上比调度一个热的任务到热的核上，具有更低的峰值温度。TSTB利用CMP在时间和空间上的温度变化，通过改变冷热任务的执行顺序来挖掘CMP每个核内的时间“温度余量”，并将冷热任务安排到温度适合的核上运行来挖掘空间“温度余量”，减少热紧急事件，提升系统性能。实验结果表明，相比于基准调度算法，TSTB算法使TET（ThermalEmergency Time）降低了8.3%~91.5%，平均降低了48.3%，使性能提升了2.47%~6.58%（平均4.62%）；TSTB相比于随机调度算法、轮转调度算法、平衡算法以及ThresHot算法等，均有不同程度的性能提升。
第五，针对3D CMP，提出了HTBS调度算法。分析了3D CMP的温度特性，将垂直堆叠的核当作一个核堆，让任务的功耗在核堆之间进行平衡，同时将热的任务放在离热沉近的核上运行，以加速散热。当某个核出现过热时，对核堆中功耗最密集的处理器核进行DTM，使温度迅速降低。实验结果表明，相比于基准调度算法，HTBS算法使TET降低了8.4%~96.2%，平均降低了54.7%，获得了5.99%的性能提升；HTBS算法相比于随机调度、轮转调度、核间温度平衡调度以及堆间温度平衡调度算法，均有不同程度的性能提升。
With continuous IC (Integrated Circuit) technology size scaling, themicroprocessor’s power density and temperature continues to rise. The increase in dietemperature results in reduced performance and reliability. There are also emergingtechnologies, such as chip multi-processor and3D stacking technology, which canexacerbate the thermal condition on modern processors.
The chip’s temperature tremendous change in time and space also poses a greatchallenge to the processor’s package and cooling. Existing cooling methodologies arehard pressed to alleviate the high temperatures associated with current generation highperformance processors. Current processors mainly use hardware dynamic temperaturemanagement to alleviate the power and temperature issues. Once the processor'stemperature reaches a predetermined threshold value, it starts the appropriatetemperature management mechanisms (such as dynamic voltage and frequency scaling,DVFS) to reduce the temperature of the processor, and prevent the processor fromdamage. However, these mechanisms have the disadvantage of high cost and willjeopardize the processor’s performance.
Our goal is to eliminate unnecessary HW DTM as much as possible and improvethe chip’s performance. This paper studied the temperature-aware design technologiessystematically. Against the shortage of the existing method, we proposed three newtechnologies to avoid the unnecessary HW DTM. The main contributions of this paperare as follows:
First, this paper summarized the existing temperature-aware design techniques fromdifferent levels and different angles, and analyzed the advantages and disadvantages ofthese techniques.
Second, the temperature-aware task scheduling techniques needs power andtemperature calculation. This paper summarized the existing power estimation model andtemperature model, and then analyzed the characteristics of these models. We alsodiscussed how to obtain the power consumption and calculate the processor’stemperature.
Third, to improve the performance of the single-core processors, which is harmed bythe thermal overshoots and the HW DTMs, we propose an algorithm named GSA. Wefind that if the processor reaches a high temperature state sooner, then the processor willbe able to heat dissipation faster. Based on this fact, GSA schedules the hot jobs beforethe cool jobs as long as it does not exceed the threshold. By fully use of the processortemporal "temperature margin" to reduce the number of DTM trigger, the performance ofthe system will be improved. Plenty of experiments are made. The DTM reduction rangesare9.9-82%(47.1%on average),8.8-73.8%(41%on average),2.9-58.7%(31.7%on average), and5.9-45.5%(31%) for mild, medium, and harsh thermal environment, andnon-SPEC benchmarks in medium environment respectively and the CPU throughputwas improved by up to4.2%,5.2%,4.7%,3.7%on average respectively.
Fourth, we proposed TSTB algorithm for the2D CMP. CMP’s natural clusteringstructure offers a new approach for the temperature management. Scheduling a hot task toa cold core can lower the processor’s temperature. TSTB utilize CMP’s temporal andspatial temperature changes and arrange the order of execution of the hot and cold tasksand schedule the task to the appropriate core to reduce thermal emergencies, and improvesystem performance. Experimental results showed that the TSTB algorithm can reducethe TET by8.3%-91.5%(48.3%on average), and the CPU throughput was improved by2.47%-6.58%(4.62%on average).
Finally, we proposed TSTB algorithm for the3D CMP. This paper analyzed the3DCMP temperature characteristics. First, the vertically stacked core should be treated as acore stack. The power of jobs is balanced among the core stacks instead of the individualcores. Second, the hot jobs are moved close to the heat sink to expedite heat dissipation.Third, when the thermal emergencies happen, the most power-intensive job in a corestack is penalized in order to lower the temperature quickly. Experimental results showedthat the HTBS algorithm can reduce the TET by8.4%-96.2%(54.7%on average), andthe CPU throughput was improved by5.99%on average.
引文
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