片上网络无虚通道容错路由技术研究
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摘要
随着微电子技术的发展，片上系统(System-on-Chip，SoC)中集成的IP核数目不断增加。传统的SoC共享总线结构无法满足多IP体系的发展需要。研究者们借鉴计算机通信网络技术的思想，提出了一种新的片上互连结构——片上网络(Networks-on-Chip，NoC)。NoC在结构上实现了通信模块和计算模块的分离，具有良好的并行通信能力，解决了传统的SoC总线扩展性差，通信效率低和全局同步功耗高等问题，成为了当前片上互连的设计趋势。
在集成电路特征尺寸减小、频率升高的趋势下，NoC对于串扰、电磁干扰、电压扰动等噪声干扰更为敏感，并可能导致错误数据的产生。另外，随着晶体管密度增大，芯片在生产时出现缺陷以及运行过程中出现故障的概率也随之增加，因此针对NoC的容错技术成为近年来相关领域的研究热点。本文以NoC容错路由为对象，研究片上网络无虚通道容错算法以及仿真验证平台的设计和构建，得出了一些新的、较为实用的技术和研究成果。主要内容包括：
1.单故障节点NoC无虚通道容错算法研究。在分析单故障节点NoC的结构特点的基础上，提出了一种新的无虚通道容错算法，以弥补现有算法在处理单故障节点NoC路由问题时存在的不足。该算法通过设置辅助节点和优化绕行策略，实现了均衡片上网络负载和减少网络传输时延的目的。在此基础上，推导证明了所提算法的无死锁性。静态和动态仿真表明：与现有算法相比，该算法具有低功耗、低时延的特点。
2.多故障节点NoC无虚通道容错算法研究。针对现有多故障节点无虚通道容错算法存在的问题，提出了一种适用于2D Mesh NoC的多故障节点无虚通道容错算法。详细分析了算法的路由器设计、优化方法及实现步骤，并在此基础上利用通道依赖图(Channel Dependency Graph，CDG)理论，证明了其具有无死锁性。进一步的仿真表明，与现有算法相比，该算法能够减少通信时延，且随着故障区域面积的增加，效果更为明显。
3.基于链路故障模型的NoC无虚通道容错路由算法研究。针对采用节点故障模型的容错算法存在故障区域面积大、节点利用率低的问题，提出一种基于链路故障模型的无虚通道容错算法。通过建立新的故障模型和优化容错路由策略，可有效减少绕行距离，并提高节点利用率。仿真表明：与采用节点故障模型的无虚通道容错算法相比，所提算法可减少传输时延，提高网络吞吐量。
4. NOC软件仿真工具的开发和应用。以OPNET为基础，通过在网络域、节点域和进程域三个层面对NoC系统进行的建模，实现了一种模块化的通用仿真工具——基于OPNET的NoC仿真平台。用户可以选择平台中己有模型进行NOC的仿真。同时该平台支持二次开发，用户能够通过修改相应模块的方式，增加新的拓扑结构、路由节点和路由算法。
5. NoC硬件仿真平台的设计和实现。分析了两种硬件平台的设计思路和结构，可以实现对NOC拓扑结构、路由节点和路由算法的仿真和验证。
With the development of microelectronics technology, more and more IP corescould be integrated on a single multiprocessor System-on-Chip (SoC). The traditionalSoC shared bus architecture does not meet the need of multi-IP system development. Tosolve this problem, a new on-chip interconnection architecture called Networks-on-Chip (NoC) is proposed by referencing the computer network technology. NoC realizesthe separation of communication module and computation module, has good parallelcommunication capability, and solves the shortages existed in SoC such as lowexpansibility, low communication efficiency, high power consumption due to globalsynchronization. NoC has become a design trend for on-chip interconnections.
With the reduction of feature size and higher frequency, NoC becomes moresensitive and unreliable to the noises caused by crosstalk, electromagnetic interferenceand voltage disturbance, etc. At the same time, the possibility of faults which occurs inmanufacturing process or operational phase increase as transistor density on IC becomeshigher and higher. Therefore, the fault tolerant technique for NoC has become a researchfocus in the related field. With the fault tolerant routing as the research prototype, thisdissertation focuses on fault tolerant routing algorithm without virtual channels andsimulation platform design of NoC. Some novel and practical results are also gained inthis paper. The main contributions are summarized as follows:
1. Single fault NoC tolerant algorithm without virtual channels has been studied.On basis of analyzing the structure of single fault NoC, a novel tolerant routingalgorithm is proposed to solve the deficiency of using existing algorithms in single faultNoC routing. By setting new auxiliary nodes and the optimized fault tolerant strategy,the network load can be balanced and the transmission delay is reduced. Moreover,deadlock free behavior of it is proved. Static and dynamic simulation results show thatproposed algorithm has the advantages of less power consumption and low delay.
2. Multiple faults NoC tolerant algorithm without virtual channels has been studied.With consideration of the problems of the existing algorithms, a novel fault tolerantrouting algorithm without using virtual channels for2D Mesh NoC is proposed. Therouter design is presented, and then optimization methods and implementation steps ofproposed algorithm are discussed. On this basis, its deadlock freeness is proved usingChannel Dependency Graph (CDG) theory. Simulation results show that the proposedalgorithm can reduce communication latency and has better performance when the faultarea increases.
3. Links fault model based NoC tolerant algorithm without virtual channels hasbeen studied. According to the deficiency of both larger fault region and low utilizationratio of nodes that exists in the nodes fault model, a novel fault tolerant routingalgorithm without using virtual channels based on links fault model is proposed.Because of using the new model and the optimized fault tolerant strategy, detourdistance of faults can be reduced and utilization ratio of nodes can be increased.Simulation results show that the proposed algorithm can reduce transmission delay andincrease network throughput.
4. Development and application of the NoC simulation tool. By carrying on themodeling of the network domain, the node domain and the process domain in OPNET, amodular software simulation tool—OBNSP (OPNET Based NoC Simulation Platform)is constructed. We can use the models base of the platform to make simulations of NoC.The platform also supports secondary development, and the new topology, the routerarchitecture and the routing algorithms can be added by modifying correspondingmodules.
5. Design and Implementation of NOC hard ware emulation and evaluationplatform. Introduce the design methods and structure of the two hardware platforms.Simulations of the NoC topology, the router architecture and the routing algorithms canbe realized.
在集成电路特征尺寸减小、频率升高的趋势下，NoC对于串扰、电磁干扰、电压扰动等噪声干扰更为敏感，并可能导致错误数据的产生。另外，随着晶体管密度增大，芯片在生产时出现缺陷以及运行过程中出现故障的概率也随之增加，因此针对NoC的容错技术成为近年来相关领域的研究热点。本文以NoC容错路由为对象，研究片上网络无虚通道容错算法以及仿真验证平台的设计和构建，得出了一些新的、较为实用的技术和研究成果。主要内容包括：
1.单故障节点NoC无虚通道容错算法研究。在分析单故障节点NoC的结构特点的基础上，提出了一种新的无虚通道容错算法，以弥补现有算法在处理单故障节点NoC路由问题时存在的不足。该算法通过设置辅助节点和优化绕行策略，实现了均衡片上网络负载和减少网络传输时延的目的。在此基础上，推导证明了所提算法的无死锁性。静态和动态仿真表明：与现有算法相比，该算法具有低功耗、低时延的特点。
2.多故障节点NoC无虚通道容错算法研究。针对现有多故障节点无虚通道容错算法存在的问题，提出了一种适用于2D Mesh NoC的多故障节点无虚通道容错算法。详细分析了算法的路由器设计、优化方法及实现步骤，并在此基础上利用通道依赖图(Channel Dependency Graph，CDG)理论，证明了其具有无死锁性。进一步的仿真表明，与现有算法相比，该算法能够减少通信时延，且随着故障区域面积的增加，效果更为明显。
3.基于链路故障模型的NoC无虚通道容错路由算法研究。针对采用节点故障模型的容错算法存在故障区域面积大、节点利用率低的问题，提出一种基于链路故障模型的无虚通道容错算法。通过建立新的故障模型和优化容错路由策略，可有效减少绕行距离，并提高节点利用率。仿真表明：与采用节点故障模型的无虚通道容错算法相比，所提算法可减少传输时延，提高网络吞吐量。
4. NOC软件仿真工具的开发和应用。以OPNET为基础，通过在网络域、节点域和进程域三个层面对NoC系统进行的建模，实现了一种模块化的通用仿真工具——基于OPNET的NoC仿真平台。用户可以选择平台中己有模型进行NOC的仿真。同时该平台支持二次开发，用户能够通过修改相应模块的方式，增加新的拓扑结构、路由节点和路由算法。
5. NoC硬件仿真平台的设计和实现。分析了两种硬件平台的设计思路和结构，可以实现对NOC拓扑结构、路由节点和路由算法的仿真和验证。
With the development of microelectronics technology, more and more IP corescould be integrated on a single multiprocessor System-on-Chip (SoC). The traditionalSoC shared bus architecture does not meet the need of multi-IP system development. Tosolve this problem, a new on-chip interconnection architecture called Networks-on-Chip (NoC) is proposed by referencing the computer network technology. NoC realizesthe separation of communication module and computation module, has good parallelcommunication capability, and solves the shortages existed in SoC such as lowexpansibility, low communication efficiency, high power consumption due to globalsynchronization. NoC has become a design trend for on-chip interconnections.
With the reduction of feature size and higher frequency, NoC becomes moresensitive and unreliable to the noises caused by crosstalk, electromagnetic interferenceand voltage disturbance, etc. At the same time, the possibility of faults which occurs inmanufacturing process or operational phase increase as transistor density on IC becomeshigher and higher. Therefore, the fault tolerant technique for NoC has become a researchfocus in the related field. With the fault tolerant routing as the research prototype, thisdissertation focuses on fault tolerant routing algorithm without virtual channels andsimulation platform design of NoC. Some novel and practical results are also gained inthis paper. The main contributions are summarized as follows:
1. Single fault NoC tolerant algorithm without virtual channels has been studied.On basis of analyzing the structure of single fault NoC, a novel tolerant routingalgorithm is proposed to solve the deficiency of using existing algorithms in single faultNoC routing. By setting new auxiliary nodes and the optimized fault tolerant strategy,the network load can be balanced and the transmission delay is reduced. Moreover,deadlock free behavior of it is proved. Static and dynamic simulation results show thatproposed algorithm has the advantages of less power consumption and low delay.
2. Multiple faults NoC tolerant algorithm without virtual channels has been studied.With consideration of the problems of the existing algorithms, a novel fault tolerantrouting algorithm without using virtual channels for2D Mesh NoC is proposed. Therouter design is presented, and then optimization methods and implementation steps ofproposed algorithm are discussed. On this basis, its deadlock freeness is proved usingChannel Dependency Graph (CDG) theory. Simulation results show that the proposedalgorithm can reduce communication latency and has better performance when the faultarea increases.
3. Links fault model based NoC tolerant algorithm without virtual channels hasbeen studied. According to the deficiency of both larger fault region and low utilizationratio of nodes that exists in the nodes fault model, a novel fault tolerant routingalgorithm without using virtual channels based on links fault model is proposed.Because of using the new model and the optimized fault tolerant strategy, detourdistance of faults can be reduced and utilization ratio of nodes can be increased.Simulation results show that the proposed algorithm can reduce transmission delay andincrease network throughput.
4. Development and application of the NoC simulation tool. By carrying on themodeling of the network domain, the node domain and the process domain in OPNET, amodular software simulation tool—OBNSP (OPNET Based NoC Simulation Platform)is constructed. We can use the models base of the platform to make simulations of NoC.The platform also supports secondary development, and the new topology, the routerarchitecture and the routing algorithms can be added by modifying correspondingmodules.
5. Design and Implementation of NOC hard ware emulation and evaluationplatform. Introduce the design methods and structure of the two hardware platforms.Simulations of the NoC topology, the router architecture and the routing algorithms canbe realized.
引文
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