FPGA低功耗设计相关技术研究
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摘要
摘要：现场可编程门阵列(Field Programmable Gate Array,FPGA)作为一种可编程逻辑器件,在短短二十多年里已从电子设计的外围器件逐渐演变为数字系统的核心,被广泛地应用在原型验证、计算机硬件、工业控制、通信、汽车电子、航空航天等各个领域。随着集成电路制造技术的不断提高,FPGA器件的速度、规模和复杂程度不断增加,FPGA的设计面临着一系列新的难题,功耗问题就是其中之一。
本文围绕FPGA的功耗设计问题展开研究,提出了一系列实用有效的低功耗设计技术和方法,主要研究内容涉及FPGA器件低功耗设计和FPGA应用逻辑低功耗设计两个方面,论文主要研究工作及创新性成果如下：
(1)在深入分析静态随机存取存储器(Static Random Access Memory, SRAM)单元泄漏电流来源的基础上,提出一种适合于FPGA的低功耗SRAM单元设计方法。该方法基于FPGA中SRAM单元在配置后存储值多数为“0”这一特点,综合应用双阈值电压技术和双栅氧化层厚度技术降低SRAM单元存储值为“0”时的泄漏功耗。其优点是在不增加SRAM单元面积和整体延时的情况下,能改善静态噪声容限、降低静态功耗。
(2)针对当前FPGA中多路选择器设计存在大量闲置晶体管这一现象,提出一种适合于FPGA的低功耗多路选择器设计方法。该方法采用反向体偏置技术对多路选择器中闲置晶体管的泄漏电流进行优化,在不影响电路性能的条件下降低多路选择器的泄漏功耗。
(3)在分析FPGA不同状态下功耗来源的基础上,结合双电压技术和电源门控技术各自的优点,提出一种低功耗FPGA结构设计方法。仿真结果表明,采用该结构设计FPGA器件能有效的降低FPGA的动态功耗和静态功耗,尤其适合应用于移动、便携式设备。
(4)在FPGA应用设计方面,针对传统寄存器堆设计方法占用较多布线资源和功耗高等缺点,提出一种基于块RAM的低功耗寄存器堆设计方法。仿真结果表明,与传统设计方法相比,该方法具有降低功耗、节约布线资源和易实现等优点。
(5)针对FPGA在航空航天等应用领域面临的可靠性和功耗问题,提出一种低功耗并具有容错能力有限状态机设计方法。该方法将状态机映射到FPGA内置块RAM,同时采用两块RAM构成双模冗余结构,通过比较两块RAM输出数据的一致性确定RAM中数据出错的情况,并结合奇偶校验进行检错与纠错。与传统的三模冗余设计方法相比,采用该方法设计的有限状态机具有更低的功耗和更高的可靠性,并能对一位错误实现在线纠错。
Abstract:Field programmable gate array (FPGA),as a programmable logic device,has gradually evolved over the last twenty years from a peripheral component of an electronic design to a core processing element of digital systems,which is widely used in various field of prototype,computer hardware,industrial controlling,communications, automotive electronics,aerospace,etc.With the constant improvement of the integrated circuit manufacturing technology and the growing increase of the speed,scale and complexity of FPGA device,the FPGA design is facing a series of new problems,one of which lies in the problem of power consumption.
This dissertation carries out a research into the design of FPGA power consumption and then puts forward many practical and effective technologies and methods for low power consumption. The main research work and innovative achievements are listed as follows:
(1)On the basis of deeply analyzing the source of static random access memory(SRAM) leakage current, a new design method of low power SRAM suitable for PFGA the paper is proposed. According to the characteristic that most SRAM cells is storing "0" when FPGA is configured,the proposed method reduces the leakage power dissipation of SRAM when the SRAM cell stores "0" by using dual threshold voltage technique and dual oxide thickness technique. The method has the advantages of improving the static noise margin of SRAM,together with reducing leakage power dissipation without increasing the circuit delay and area.
(2)Aiming at the phenomenon of the used multiplexers in FPGA containing many idle transistors,a new design method of multiplexers suitable for FPGA low power the paper is proposed. The proposed method optimizes the leakage power dissipation of idle transistors in multiplexer by using reverse body bias technique and reduces the total leakage power dissipation while maintaining performance.
(3)Based on the source analysis of FPGA power consumption in different states and combined with advantages of dual-Vdd and power gating technologies to reduce the power consumption of FPGA in different states, a new design method of FPGA lower-power architecture is proposed. The FPGA device designed with this architecture has the advantages of reducing the dynamic power consumption and static power consumption,which is especially suitable for application in mobile and handheld devices.
(4) In the aspect of FPGA application design,against the shortcomings of occupying more routing resource and high power in traditional register files implement method,a new design method of lower power register files based on block RAM in FPGA is proposed. The simulation results show that compared with the traditional ways the new method has the advantages of reducing power consumption,saving routing resource and being easy to implement.
(5)Considering the reliability and power consumption problems of FPGA in aviation and spaceflight application field,a new design method of low power and fault-tolerance finite state machine suitable for FPGA is proposed. The method is realized by mapping finite-state machines (FSM) into embedded blocks RAM of FPGA and employing two RAM blocks to compose the duple-redundancy structure to confirm data errors in RAM through comparing consistency of two blocks RAM output data and combining with parity check for error detection and correction. Compared with the traditional triple-redundancy method, the FSM designed with this method has the advantages of lower power,higher reliability,and achieving an error on-line error correction.
本文围绕FPGA的功耗设计问题展开研究,提出了一系列实用有效的低功耗设计技术和方法,主要研究内容涉及FPGA器件低功耗设计和FPGA应用逻辑低功耗设计两个方面,论文主要研究工作及创新性成果如下：
(1)在深入分析静态随机存取存储器(Static Random Access Memory, SRAM)单元泄漏电流来源的基础上,提出一种适合于FPGA的低功耗SRAM单元设计方法。该方法基于FPGA中SRAM单元在配置后存储值多数为“0”这一特点,综合应用双阈值电压技术和双栅氧化层厚度技术降低SRAM单元存储值为“0”时的泄漏功耗。其优点是在不增加SRAM单元面积和整体延时的情况下,能改善静态噪声容限、降低静态功耗。
(2)针对当前FPGA中多路选择器设计存在大量闲置晶体管这一现象,提出一种适合于FPGA的低功耗多路选择器设计方法。该方法采用反向体偏置技术对多路选择器中闲置晶体管的泄漏电流进行优化,在不影响电路性能的条件下降低多路选择器的泄漏功耗。
(3)在分析FPGA不同状态下功耗来源的基础上,结合双电压技术和电源门控技术各自的优点,提出一种低功耗FPGA结构设计方法。仿真结果表明,采用该结构设计FPGA器件能有效的降低FPGA的动态功耗和静态功耗,尤其适合应用于移动、便携式设备。
(4)在FPGA应用设计方面,针对传统寄存器堆设计方法占用较多布线资源和功耗高等缺点,提出一种基于块RAM的低功耗寄存器堆设计方法。仿真结果表明,与传统设计方法相比,该方法具有降低功耗、节约布线资源和易实现等优点。
(5)针对FPGA在航空航天等应用领域面临的可靠性和功耗问题,提出一种低功耗并具有容错能力有限状态机设计方法。该方法将状态机映射到FPGA内置块RAM,同时采用两块RAM构成双模冗余结构,通过比较两块RAM输出数据的一致性确定RAM中数据出错的情况,并结合奇偶校验进行检错与纠错。与传统的三模冗余设计方法相比,采用该方法设计的有限状态机具有更低的功耗和更高的可靠性,并能对一位错误实现在线纠错。
Abstract:Field programmable gate array (FPGA),as a programmable logic device,has gradually evolved over the last twenty years from a peripheral component of an electronic design to a core processing element of digital systems,which is widely used in various field of prototype,computer hardware,industrial controlling,communications, automotive electronics,aerospace,etc.With the constant improvement of the integrated circuit manufacturing technology and the growing increase of the speed,scale and complexity of FPGA device,the FPGA design is facing a series of new problems,one of which lies in the problem of power consumption.
This dissertation carries out a research into the design of FPGA power consumption and then puts forward many practical and effective technologies and methods for low power consumption. The main research work and innovative achievements are listed as follows:
(1)On the basis of deeply analyzing the source of static random access memory(SRAM) leakage current, a new design method of low power SRAM suitable for PFGA the paper is proposed. According to the characteristic that most SRAM cells is storing "0" when FPGA is configured,the proposed method reduces the leakage power dissipation of SRAM when the SRAM cell stores "0" by using dual threshold voltage technique and dual oxide thickness technique. The method has the advantages of improving the static noise margin of SRAM,together with reducing leakage power dissipation without increasing the circuit delay and area.
(2)Aiming at the phenomenon of the used multiplexers in FPGA containing many idle transistors,a new design method of multiplexers suitable for FPGA low power the paper is proposed. The proposed method optimizes the leakage power dissipation of idle transistors in multiplexer by using reverse body bias technique and reduces the total leakage power dissipation while maintaining performance.
(3)Based on the source analysis of FPGA power consumption in different states and combined with advantages of dual-Vdd and power gating technologies to reduce the power consumption of FPGA in different states, a new design method of FPGA lower-power architecture is proposed. The FPGA device designed with this architecture has the advantages of reducing the dynamic power consumption and static power consumption,which is especially suitable for application in mobile and handheld devices.
(4) In the aspect of FPGA application design,against the shortcomings of occupying more routing resource and high power in traditional register files implement method,a new design method of lower power register files based on block RAM in FPGA is proposed. The simulation results show that compared with the traditional ways the new method has the advantages of reducing power consumption,saving routing resource and being easy to implement.
(5)Considering the reliability and power consumption problems of FPGA in aviation and spaceflight application field,a new design method of low power and fault-tolerance finite state machine suitable for FPGA is proposed. The method is realized by mapping finite-state machines (FSM) into embedded blocks RAM of FPGA and employing two RAM blocks to compose the duple-redundancy structure to confirm data errors in RAM through comparing consistency of two blocks RAM output data and combining with parity check for error detection and correction. Compared with the traditional triple-redundancy method, the FSM designed with this method has the advantages of lower power,higher reliability,and achieving an error on-line error correction.
引文
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