MOS晶体管全区域噪声模型及其在低噪声运放设计中的应用
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摘要
CMOS运算放大器是模拟集成电路中最基本、最重要的模块,在汽车电子、通信、消费电子、军用电子系统等各个领域有着广泛的应用。近年来,随着深亚微米技术的发展,CMOS运算放大器的供电电源电压越来越低,并不断恶化电路的信噪比,这无疑对运算放大器的噪声性能提出了更高的要求。研究CMOS运算放大器的噪声与MOS晶体管的器件噪声是密切相关的。因此,研究深亚微米MOS晶体管噪声模型及低噪声运算放大器的设计方法已成为当今模拟电路设计中极具挑战的一个重要议题。
CMOS工艺进入深亚微米时代,带来了速度提高和晶体管沟道长度不断减小的明显优势。与此同时,这种进步也使得CMOS低噪声运算放大器的设计必须面临以下几个关键性问题:首先,研究运算放大器的噪声离不开器件的噪声模型,但传统的长沟道噪声模型已经不再能精确地预测短沟道器件的噪声特性,因此也不能精确地预测运算放大器的噪声特性。其次,随着电源电压降低,MOS晶体管也经常工作在弱反型或中度反型,这意味着传统的器件噪声模型需要扩展其有效范围由弱反型至强反型。最后,随着电源电压降低,运算放大器性能指标之间的相互折衷变得更为困难,这意味着为了提高电路的设计效率,在电路仿真前就需要将性能指标之间的折衷关系考虑进来。这几个问题相辅相承,共同为器件噪声模型及低噪声运算放大器设计的研究提出了更高的要求。
本文针对以上所存在的问题,对适用于深亚微米的MOS晶体管的全区域噪声模型、CMOS低噪声运算放大器的设计方法、高性能低噪声运算放大器的设计及噪声分析进行了研究。具体研究内容包括:
首先,基于噪声的物理机制,应用通用的噪声建模方法建立了在整个工作区域(即从弱反型到强反型,从线性区到饱和区)都有效的全区域沟道噪声模型。该模型由沟道热噪声、闪烁噪声和闪烁噪声转角频率的解析模型表达式所组成。该模型全面考虑了短沟道效应对噪声的影响。其中热噪声模型包括了热载流子、迁移率降低、沟道调制等短沟道效应对噪声的影响;闪烁噪声同时包含了迁移率浮动和载流子数量浮动两种噪声机制,并考虑了迁移率浮动对反型层载流子密度的依赖关系。测试结果验证了所提出的深亚微米MOS晶体管的沟道噪声模型在全区域都有效。
随后,在所建立噪声模型的基础上,以噪声性能为设计基点,以一个三级运算放大器的设计为例,提出了基于全区域噪声模型的CMOS低噪声运算放大器的设计方法。在设计过程中,基于所要求的设计目标,分别用所提出的深亚微米MOS晶体管全区域噪声模型和传统的长沟道噪声模型对三级运放的设计参数进行了计算。结果表明前者的计算结果较后者更接近于HSPICE仿真结果。测试结果满足设计目标要求。这些结果表明提出的设计方法可以有效指导电路的仿真设计,提高电路设计效率。运算放大器设计完成后,应用全区域噪声模型对该运放的等效输入噪声进行了计算。计算结果较仿真结果更接近于测试结果,这进一步验证了提出的深亚微米MOS晶体管全区域噪声模型可以较精确地预测噪声特性,为保证低噪声运放设计方法的有效性及精确性提供理论保障。
最后,在研究全区域噪声模型及低噪声运算放大器设计方法的基础上,给出了三种改进的低噪声运算放大器的设计电路:1)基于V-NPN晶体管的低噪声运放设计。该设计用V-NPN晶体管代替MOS晶体管作为输入差动对来改善噪声特性,同时提出了基极电流补偿电路来改善V-NPN晶体管较大的基极电流;2)基于DTMOS晶体管的低运设计。该设计用DTMOS晶体管代替MOS晶体管作为输入差动对来改善噪声特性,并且提出了用组合级联晶体管结构来改善DTMOS晶体管较低的输出阻抗,进而提高增益;3)具有Rail-to-Rail输入共模范围的恒跨导低噪声运放设计。该设计用同沟道的两对DTMOS晶体管输入差动对代替MOS晶体管差动对实现Rail-to-Rail输入共模范围的同时,也改善了噪声特性。此外,提出了电流调节器电路来调整交叠区输入差动对的尾电流,以保证Rail-to-Rail输入共模范围内跨导的恒定。以上述所讨论的三种运放设计为例,我们进一步验证了深亚微米MOS晶体管的全区域噪声模型及低噪声运算放大器的设计方法。为了验证噪声模型,我们用所提出的噪声模型分别对V-NPN低噪声运放及DTMOS低噪声运放的等效输入噪声电压进行了计算。前者计算结果与HSPICE仿真结果相当,后者与第四章的结果规律相似,计算结果略高于仿真结果(第四章已经证明计算结果较仿真结果更接近于测试结果)。这表明我们所提出的噪声模型可以较精确地预测噪声特性。此外,我们应用所提出的低噪声运放的设计方法对Rail-to-Rail低噪声运放的设计参数进行了计算,计算结果接近于仿真结果。这进一步表明我们所提出的设计方法可以有效指导电路的仿真设计,提高电路设计效率。
As an important circuit cell in analog integrated circuits, CMOS operational amplifiers (opamp) have been used in more and more practical applications, such as automotive electronics, communication, consumer electronics, and military system etc. With the continual improvement of deep-submicron CMOS technologies, low voltage CMOS operational amplifiers are paid more attention than ever in analog integrated circuits. However, the decreasing power supply voltage will degrade the signal-to-noise ratio of circuits, which means that it is indispensable to improve the noise performance of circuits. MOSFETs are the dominant noise sources in CMOS operational amplifiers. Therefore, it is becoming an important issue for studying the noise models of MOSFETs and the design procedure of CMOS low noise operational amplifiers.
Several problems have to be considered with CMOS technologies marching into deep-submicron era for improving speed and area etc. Firstly, the noise theory of operational amplifiers depends on the noise models of MOSFETs. Unfortunately, typical long channel noise models can not well predict the noise behavior of short channel MOSFETs, hence can not well predict the noise behavior of operational amplifiers. Secondly, with the power supply voltage decreasing, MOSFETs often operate under weak inversion or moderate inversion, which requires that the validity of typical noise models should be extended from weak inversion to strong inversion. Finally, the compromises between specifications become more evident with the power supply voltage decreasing, which means we should consider how to manually calculate the design parameters before simulation for coherent and timely circuit design.
Aiming at the present problems, the all-region noise models valid for deep-submicron MOSFETs, the design procedure for CMOS low noise operational amplifiers, and the design and the noise analysis of high performance low noise operational amplifiers were studied in this paper. The study includes in detail as following aspects:
Firstly, the all-region (from weak inversion to strong inversion, and from linear region to saturated region) noise models valid for deep-submicron MOSFETs were proposed using the generalized noise calculation methodology based on the physical mechanism of noise. The physics-based expressions for thermal and flicker noise, and flicker noise corner frequency constitute compact channel noise models. The noise models comprehensively considered the short channel effects. The carrier heating, channel length modulation, and mobility degradation due to the vertical and lateral electric field have been incorporated in the proposed thermal model. And the effect of the mobility and carrier number fluctuations on the flicker noise as well as the dependency of the mobility limited by Coulomb scattering on the inversion carrier density have been considered in the proposed flicker noise model. The measured results validate the proposed models.
Based on the proposed all-region noise models for deep-submicron MOSFETs, as an example using a three-stage operational amplifier, a noise-oriented design procedure for CMOS low noise operational amplifiers was proposed. In the design procedure, we calculated the design parameters of the three-stage operational amplifier starting from the expected specifications, using the proposed all-region deep-submicron thermal noise model and the typical long-channel thermal noise model, separately. The results show that the calculated results using the former are closer to the simulated results by HSPICE than the latter. And, the measured results also agree well with the expected specifications. These results show the proposed design procedure can effectively guide the simulated design of operational amplifiers, hence improve the design efficiency. Based on the operational amplifier design, the equivalent input noise spectrum density was calculated from the proposed all-region deep-submicron thermal noise model. The calculated results are closer to the measured result than the simulated results by HSPICE. It shows the proposed noise models can well predict the noise behavior of operational amplifiers, and provide the theoretical foundation for the validity and accuracy of the proposed design procedure.
Finally, three low noise operational amplifiers were proposed based on the proposed all-region deep-submicron noise models and the noise-oriented design procedure for low noise operational amplifiers: 1) A low noise operational amplifier design using V-NPN transistors. In this design, V-NPN transistors were used instead of typical MOS transistors as input differential pair for improving the noise performance. And a base-current compensation circuit was proposed for improving the larger base currents of V-NPN transistors. 2) A low noise operational amplifier design using DTMOS transistors. In this design, DTMOS transistors were used instead of typical MOS transistors as input differential pair for improving the noise performance. And combined cascade transistors were used for improving the lower output impedance of DTMOS transistors, hence increasing the gain of the operational amplifier. 3) A low noise constant transconductance operational amplifier design with rail-to-rail input range. In this design, the same-channel DTMOS transistors were used instead of typical MOS transistors as input differential pair for obtaining rail-to-rail input-common range and low noise performance. And a current adjustor was proposed for the constant transconductance in the whole rail-to-rail input range.
The proposed all-region noise models for deep-submicron MOSFETs and the design procedure for low noise operational amplifiers were further verified using the aforementioned three low noise operational amplifiers. For verifying the proposed noise models, the equivalent input noise spectrum densities of the operational amplifiers using V-NPN and DTMOS transistors as input differential pair were calculated using the proposed noise model. The calculated results of the former are very close to the simulated results by HSPICE, and the calculated results of the latter like those in Chapter 4 are slightly higher than the simulated results by HSPICE (the calculated results are closer to the measured results than the simulated results in Chapter 4) . These results show that the proposed noise models can well predict the noise performance of the operational amplifiers. Furthermore, the design parameters (sizes and biasing) of the rail-to-rail operational amplifier were calculated using the proposed design procedure for CMOS low noise operational amplifiers. The calculated results are very close to the simulated results by HSPICE, which shows the proposed design procedure can effectively guide the design of circuits, and improve the design efficiency of circuits.
CMOS工艺进入深亚微米时代,带来了速度提高和晶体管沟道长度不断减小的明显优势。与此同时,这种进步也使得CMOS低噪声运算放大器的设计必须面临以下几个关键性问题:首先,研究运算放大器的噪声离不开器件的噪声模型,但传统的长沟道噪声模型已经不再能精确地预测短沟道器件的噪声特性,因此也不能精确地预测运算放大器的噪声特性。其次,随着电源电压降低,MOS晶体管也经常工作在弱反型或中度反型,这意味着传统的器件噪声模型需要扩展其有效范围由弱反型至强反型。最后,随着电源电压降低,运算放大器性能指标之间的相互折衷变得更为困难,这意味着为了提高电路的设计效率,在电路仿真前就需要将性能指标之间的折衷关系考虑进来。这几个问题相辅相承,共同为器件噪声模型及低噪声运算放大器设计的研究提出了更高的要求。
本文针对以上所存在的问题,对适用于深亚微米的MOS晶体管的全区域噪声模型、CMOS低噪声运算放大器的设计方法、高性能低噪声运算放大器的设计及噪声分析进行了研究。具体研究内容包括:
首先,基于噪声的物理机制,应用通用的噪声建模方法建立了在整个工作区域(即从弱反型到强反型,从线性区到饱和区)都有效的全区域沟道噪声模型。该模型由沟道热噪声、闪烁噪声和闪烁噪声转角频率的解析模型表达式所组成。该模型全面考虑了短沟道效应对噪声的影响。其中热噪声模型包括了热载流子、迁移率降低、沟道调制等短沟道效应对噪声的影响;闪烁噪声同时包含了迁移率浮动和载流子数量浮动两种噪声机制,并考虑了迁移率浮动对反型层载流子密度的依赖关系。测试结果验证了所提出的深亚微米MOS晶体管的沟道噪声模型在全区域都有效。
随后,在所建立噪声模型的基础上,以噪声性能为设计基点,以一个三级运算放大器的设计为例,提出了基于全区域噪声模型的CMOS低噪声运算放大器的设计方法。在设计过程中,基于所要求的设计目标,分别用所提出的深亚微米MOS晶体管全区域噪声模型和传统的长沟道噪声模型对三级运放的设计参数进行了计算。结果表明前者的计算结果较后者更接近于HSPICE仿真结果。测试结果满足设计目标要求。这些结果表明提出的设计方法可以有效指导电路的仿真设计,提高电路设计效率。运算放大器设计完成后,应用全区域噪声模型对该运放的等效输入噪声进行了计算。计算结果较仿真结果更接近于测试结果,这进一步验证了提出的深亚微米MOS晶体管全区域噪声模型可以较精确地预测噪声特性,为保证低噪声运放设计方法的有效性及精确性提供理论保障。
最后,在研究全区域噪声模型及低噪声运算放大器设计方法的基础上,给出了三种改进的低噪声运算放大器的设计电路:1)基于V-NPN晶体管的低噪声运放设计。该设计用V-NPN晶体管代替MOS晶体管作为输入差动对来改善噪声特性,同时提出了基极电流补偿电路来改善V-NPN晶体管较大的基极电流;2)基于DTMOS晶体管的低运设计。该设计用DTMOS晶体管代替MOS晶体管作为输入差动对来改善噪声特性,并且提出了用组合级联晶体管结构来改善DTMOS晶体管较低的输出阻抗,进而提高增益;3)具有Rail-to-Rail输入共模范围的恒跨导低噪声运放设计。该设计用同沟道的两对DTMOS晶体管输入差动对代替MOS晶体管差动对实现Rail-to-Rail输入共模范围的同时,也改善了噪声特性。此外,提出了电流调节器电路来调整交叠区输入差动对的尾电流,以保证Rail-to-Rail输入共模范围内跨导的恒定。以上述所讨论的三种运放设计为例,我们进一步验证了深亚微米MOS晶体管的全区域噪声模型及低噪声运算放大器的设计方法。为了验证噪声模型,我们用所提出的噪声模型分别对V-NPN低噪声运放及DTMOS低噪声运放的等效输入噪声电压进行了计算。前者计算结果与HSPICE仿真结果相当,后者与第四章的结果规律相似,计算结果略高于仿真结果(第四章已经证明计算结果较仿真结果更接近于测试结果)。这表明我们所提出的噪声模型可以较精确地预测噪声特性。此外,我们应用所提出的低噪声运放的设计方法对Rail-to-Rail低噪声运放的设计参数进行了计算,计算结果接近于仿真结果。这进一步表明我们所提出的设计方法可以有效指导电路的仿真设计,提高电路设计效率。
As an important circuit cell in analog integrated circuits, CMOS operational amplifiers (opamp) have been used in more and more practical applications, such as automotive electronics, communication, consumer electronics, and military system etc. With the continual improvement of deep-submicron CMOS technologies, low voltage CMOS operational amplifiers are paid more attention than ever in analog integrated circuits. However, the decreasing power supply voltage will degrade the signal-to-noise ratio of circuits, which means that it is indispensable to improve the noise performance of circuits. MOSFETs are the dominant noise sources in CMOS operational amplifiers. Therefore, it is becoming an important issue for studying the noise models of MOSFETs and the design procedure of CMOS low noise operational amplifiers.
Several problems have to be considered with CMOS technologies marching into deep-submicron era for improving speed and area etc. Firstly, the noise theory of operational amplifiers depends on the noise models of MOSFETs. Unfortunately, typical long channel noise models can not well predict the noise behavior of short channel MOSFETs, hence can not well predict the noise behavior of operational amplifiers. Secondly, with the power supply voltage decreasing, MOSFETs often operate under weak inversion or moderate inversion, which requires that the validity of typical noise models should be extended from weak inversion to strong inversion. Finally, the compromises between specifications become more evident with the power supply voltage decreasing, which means we should consider how to manually calculate the design parameters before simulation for coherent and timely circuit design.
Aiming at the present problems, the all-region noise models valid for deep-submicron MOSFETs, the design procedure for CMOS low noise operational amplifiers, and the design and the noise analysis of high performance low noise operational amplifiers were studied in this paper. The study includes in detail as following aspects:
Firstly, the all-region (from weak inversion to strong inversion, and from linear region to saturated region) noise models valid for deep-submicron MOSFETs were proposed using the generalized noise calculation methodology based on the physical mechanism of noise. The physics-based expressions for thermal and flicker noise, and flicker noise corner frequency constitute compact channel noise models. The noise models comprehensively considered the short channel effects. The carrier heating, channel length modulation, and mobility degradation due to the vertical and lateral electric field have been incorporated in the proposed thermal model. And the effect of the mobility and carrier number fluctuations on the flicker noise as well as the dependency of the mobility limited by Coulomb scattering on the inversion carrier density have been considered in the proposed flicker noise model. The measured results validate the proposed models.
Based on the proposed all-region noise models for deep-submicron MOSFETs, as an example using a three-stage operational amplifier, a noise-oriented design procedure for CMOS low noise operational amplifiers was proposed. In the design procedure, we calculated the design parameters of the three-stage operational amplifier starting from the expected specifications, using the proposed all-region deep-submicron thermal noise model and the typical long-channel thermal noise model, separately. The results show that the calculated results using the former are closer to the simulated results by HSPICE than the latter. And, the measured results also agree well with the expected specifications. These results show the proposed design procedure can effectively guide the simulated design of operational amplifiers, hence improve the design efficiency. Based on the operational amplifier design, the equivalent input noise spectrum density was calculated from the proposed all-region deep-submicron thermal noise model. The calculated results are closer to the measured result than the simulated results by HSPICE. It shows the proposed noise models can well predict the noise behavior of operational amplifiers, and provide the theoretical foundation for the validity and accuracy of the proposed design procedure.
Finally, three low noise operational amplifiers were proposed based on the proposed all-region deep-submicron noise models and the noise-oriented design procedure for low noise operational amplifiers: 1) A low noise operational amplifier design using V-NPN transistors. In this design, V-NPN transistors were used instead of typical MOS transistors as input differential pair for improving the noise performance. And a base-current compensation circuit was proposed for improving the larger base currents of V-NPN transistors. 2) A low noise operational amplifier design using DTMOS transistors. In this design, DTMOS transistors were used instead of typical MOS transistors as input differential pair for improving the noise performance. And combined cascade transistors were used for improving the lower output impedance of DTMOS transistors, hence increasing the gain of the operational amplifier. 3) A low noise constant transconductance operational amplifier design with rail-to-rail input range. In this design, the same-channel DTMOS transistors were used instead of typical MOS transistors as input differential pair for obtaining rail-to-rail input-common range and low noise performance. And a current adjustor was proposed for the constant transconductance in the whole rail-to-rail input range.
The proposed all-region noise models for deep-submicron MOSFETs and the design procedure for low noise operational amplifiers were further verified using the aforementioned three low noise operational amplifiers. For verifying the proposed noise models, the equivalent input noise spectrum densities of the operational amplifiers using V-NPN and DTMOS transistors as input differential pair were calculated using the proposed noise model. The calculated results of the former are very close to the simulated results by HSPICE, and the calculated results of the latter like those in Chapter 4 are slightly higher than the simulated results by HSPICE (the calculated results are closer to the measured results than the simulated results in Chapter 4) . These results show that the proposed noise models can well predict the noise performance of the operational amplifiers. Furthermore, the design parameters (sizes and biasing) of the rail-to-rail operational amplifier were calculated using the proposed design procedure for CMOS low noise operational amplifiers. The calculated results are very close to the simulated results by HSPICE, which shows the proposed design procedure can effectively guide the design of circuits, and improve the design efficiency of circuits.
引文
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