恒跨导CMOS轨对轨运算放大器设计
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摘要
随着便携式电子产品的飞速发展,集成电路电源电压不断降低,迫使运算放大器(以下简称运放)输入输出信号摆幅不断减小,进而严重影响运放的工作性能,甚至不能正常工作。为了提高运放的信噪比,通常需要输入输出信号范围能够达到整个电源电压,即轨对轨(Rail-to-Rail)。
本论文在深入了解国内外轨对轨运放研究动态的基础上,基于标准CMOS工艺,研究如何实现低电压运放的输入输出达到全摆幅,以及如何实现输入级跨导恒定和输出级的高电源利用率。研究了各种电路的组成结构和工作原理,主要研究轨对轨输入／输出和恒跨导的实现方法。在吸收已有的相关技术成果基础上,自主提出设计方案,完成设计与验证。
本论文设计的是一种3.3V低压轨对轨运算放大器。该运算放大器采用三倍电流镜法控制互补差分对作为输入级,不但满足了轨对轨共模输入电压范围的要求,而且具有良好的恒跨导特性。运放采用浮动电流源控制的前馈式AB类输出级,在精确控制输出晶体管电流的同时,满足了轨对轨输出电压动态范围的要求。运放采用折叠式共源共栅电路作为中间增益级,除实现电流求和及稳定静态输出电流的功能外,还可提高环路增益。
对于所做的设计,基于CMOS工艺规范,采用Cadence Spectre工具进行了仿真。仿真结果表明：在电源电压3.3V、负载电阻5kΩ、负载电容10pF的情况下,运放直流开环增益为120dB,单位增益带宽为6.55MHz,相位裕度为66.4。,功耗为0.36mW,在整个共模范围内输入级跨导变化率仅为2.45%。整个电路结构简单紧凑,适合于低电压低功耗应用。
Integrated circuits continue to lower the supply voltage, with the rapid development of portable electronic devices, which will force the input and output signal swing of operational amplifier (here in after referred to as the op-amp) greatly reduced, and which can seriously affect the performance of op-amp, even not to work. In order to improve the signal-to-noise ratio of the op-amp, the input and output signal range of op-amp usually requires to reach the entire supply voltage, Rail-to-Rail.
Based on the understanding of the domestic and international research on Rail-to-Rail operational amplifiers, the paper studies how to accomplish the input signal scope and the output signal scope to achieve the entire amplitude of the low voltage op-amp and how to accomplish input stage with stable transconductance and output stage with high voltage efficiency, in the view of standard CMOS technology. It also studies the structure and the principles of electric circuits, including how achieves Rail-to-Rail input/output stage and the constant transconductance. On the basis of the related technical achievement, improved design proposal has been put forward and confirmed feasible implementation.
A Rail-to-Rail operational amplifier is designed at3.3V single power supply. The input stage which satisfies the demand of Rail-to-Rail common mode input range with significant constant transconductance characteristics is a complementary differential pair controlled by three-times current mirror; the op-amp employs a feed-forward biased class-AB output stage controlled by the floating current source, meeting the requirements of the Rail-to-Rail output voltage dynamic range with precise control of the output transistor current. The folded-cascode structure is used as intermediate amplifier stage, which can realize the function of summing circuit and the steady static output current and increase the loop gain.
Based on0.18um CMOS technology, Cadence Spectra tool is used for the simulation. With the supply voltage3.3V, the load resistance5KΩ, and the load capacitance10pF, the simulation results indicate that the operational amplifier has achieved open loop DC gain of120dB, unit gain bandwidth of6.55MHz, phase margin of66.4degree, power dissipation of0.36mW, and the transconductance variation over the common-mode input range of only about2.45%. For its simple and compact structure, this operational amplifier cell is suitable for low voltage and low power consumption application.
本论文在深入了解国内外轨对轨运放研究动态的基础上,基于标准CMOS工艺,研究如何实现低电压运放的输入输出达到全摆幅,以及如何实现输入级跨导恒定和输出级的高电源利用率。研究了各种电路的组成结构和工作原理,主要研究轨对轨输入／输出和恒跨导的实现方法。在吸收已有的相关技术成果基础上,自主提出设计方案,完成设计与验证。
本论文设计的是一种3.3V低压轨对轨运算放大器。该运算放大器采用三倍电流镜法控制互补差分对作为输入级,不但满足了轨对轨共模输入电压范围的要求,而且具有良好的恒跨导特性。运放采用浮动电流源控制的前馈式AB类输出级,在精确控制输出晶体管电流的同时,满足了轨对轨输出电压动态范围的要求。运放采用折叠式共源共栅电路作为中间增益级,除实现电流求和及稳定静态输出电流的功能外,还可提高环路增益。
对于所做的设计,基于CMOS工艺规范,采用Cadence Spectre工具进行了仿真。仿真结果表明：在电源电压3.3V、负载电阻5kΩ、负载电容10pF的情况下,运放直流开环增益为120dB,单位增益带宽为6.55MHz,相位裕度为66.4。,功耗为0.36mW,在整个共模范围内输入级跨导变化率仅为2.45%。整个电路结构简单紧凑,适合于低电压低功耗应用。
Integrated circuits continue to lower the supply voltage, with the rapid development of portable electronic devices, which will force the input and output signal swing of operational amplifier (here in after referred to as the op-amp) greatly reduced, and which can seriously affect the performance of op-amp, even not to work. In order to improve the signal-to-noise ratio of the op-amp, the input and output signal range of op-amp usually requires to reach the entire supply voltage, Rail-to-Rail.
Based on the understanding of the domestic and international research on Rail-to-Rail operational amplifiers, the paper studies how to accomplish the input signal scope and the output signal scope to achieve the entire amplitude of the low voltage op-amp and how to accomplish input stage with stable transconductance and output stage with high voltage efficiency, in the view of standard CMOS technology. It also studies the structure and the principles of electric circuits, including how achieves Rail-to-Rail input/output stage and the constant transconductance. On the basis of the related technical achievement, improved design proposal has been put forward and confirmed feasible implementation.
A Rail-to-Rail operational amplifier is designed at3.3V single power supply. The input stage which satisfies the demand of Rail-to-Rail common mode input range with significant constant transconductance characteristics is a complementary differential pair controlled by three-times current mirror; the op-amp employs a feed-forward biased class-AB output stage controlled by the floating current source, meeting the requirements of the Rail-to-Rail output voltage dynamic range with precise control of the output transistor current. The folded-cascode structure is used as intermediate amplifier stage, which can realize the function of summing circuit and the steady static output current and increase the loop gain.
Based on0.18um CMOS technology, Cadence Spectra tool is used for the simulation. With the supply voltage3.3V, the load resistance5KΩ, and the load capacitance10pF, the simulation results indicate that the operational amplifier has achieved open loop DC gain of120dB, unit gain bandwidth of6.55MHz, phase margin of66.4degree, power dissipation of0.36mW, and the transconductance variation over the common-mode input range of only about2.45%. For its simple and compact structure, this operational amplifier cell is suitable for low voltage and low power consumption application.
引文
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[2]Golden P. Mole, P. Harvey B. A+100dB gain, rail-to-rail output, low distortion, low noise amplifier in BiCMOS technology[C]. Solid State Circuits Conference.2007,448-451.
[3]Duque-Carrillo J F, Ausin J L, Torelli G, et al.1-V Rail-to-Rail Operational Amplifiers in Standard CMOS Technology [J]. IEEE Journal of Solid-State Circuits.2000,35(1):33-44.
[4]Tang Xiuqing, Liu Shibin, Feng Yong. Design of a rail-to-rail CMOS operational amplifier with constant transconductance[J]. Application of Electronic Technique.2008,34(04):44-46.
[5]Phillip E. Allen, Douglas R. Holberg著,冯军,李智群译CMOS模拟集成电路设计[M].北京：电子工业出版社.2005.
[6]Dusiters T A F, Dijlomans E C. A-90-dB THD rail-to-rail input opamp using a new local pump in CMOS[C]. IEEE Journal of Solid-State Circiuts Conference.1998,33(7):947-955.
[7]Yin Yongsheng, Liu Hong. Folded cascode operational amplifier with feedback bias[J]. Journal of Hefei University of Technology(Natural Seience).2008,31(9):1363-1364.
[8]Yang H C, Allstot D J. Considerations for fast settling operational amplifiers [J]. IEEE Journal of Solid-State Circuits.1990,37(3):326-334.
[9]Stockstad T, Yoshizawa H. A 0.9V 0.5μA Rail-to-Rail CMOS Operational Amplifier[J]. IEEE Journal of Solid-State Circuits.2002,37(3):286-292.
[10]Juan M. Carrillo, Guido Torelli, et al.1-V rail-to-rail CMOS OpAmp with improved bulk-driven input stage[J]. IEEE Journal of Solid-State Circuits.2007,42(3):508-517.
[11]Linsley-Hood, J. Gain stage investigations[J]. Electronics World.1998,104(1747):578-583.
[12]Huijsing J H, Linebarger D. Low-Voltage Operational Amplifier with Rail-to-Rail Input and Output Ranges[J]. IEEE Journal of Solid-State Circuits.1985,20(6):1144-1150.
[13]Thandri B K, Silva-Martinez J. A robust feedforward compensation scheme for multistage operational transconductance amplifiers with no miller capacitors[J].2003,38(2):237-243.
[14]毕查德·拉扎维.模拟CMOS集成电路设计[M].西安：西安交通大学出版社.2002.
[15]Phillip E. Allen, Douglas R. Holberg. CMOS Analog Circuit Design(Second Edition)[M]. Beijing:Publishing House of Electronics Industry.2007.
[16]Gray P R, Meyer R G. Analysis and design of analog integrated circuits(fourth edition)[M].北京：高等教育出版社.2003.
[17]Amerasekera A, Duvvury C. ESD in silicon integrated circuits[M]. NewYork:John Wiley and Sons.2002.
[18]Streetman B G, Banerjee S著,杨建红译,固体电子器件(第五版)[M].兰州：兰州大学出版社.2005.
[19]Allen P E, Sanchez-Sinencio E. Switched Capacitor Circuits[M]. NewYork:Van Nostrand Reinhold.1984.
[20]John P. Uyemura著,周润德译.超大规模集成电路与系统导论[M].北京：电子工业出版社.2004.
[21]陈贵灿,邵忠标,程军,林长贵CMOS集成电路设计[M].西安：西安交通大学出版 社,1999.
[22]李金平.模拟集成电路基础[M].北京：北方交通大学出版社.2003.
[23]Hwang C, Motamed A, Ismail M. A New implementation of constant-gm OpAmp input stage for CMOS low voltage applications[J]. Proc.of the 1995 IEEE Midwest svmp, CAS, Rio De Juneiro, Brazil.1995.
[24]Willy M. C. Sansen. Analog Design Essentials[M]. Netherlands:Springer.2006.
[25]魏延存,陈莹梅,胡正飞.模拟CMOS集成电路设计[M].北京：清华大学出版社.2010.
[26]李联.MOS运算放大器-原理、设计与应用[M].上海：复旦大学出版社1988.
[27]杨银堂,朱樟明,刘帘曦.现代半导体集成电路[M].北京：电子工业出版社.2009.
[28]Vinence V. C, Montoro C.G., Schneider M.C. A low-voltage CMOS class-AB operational amplifier[C]. IEEE Circuits and Systems Conference.2002,(3):601-612.
[29]Lu, C W, Hsiao, C M.1 V rail-to-rail constant-g(m) CMOS op amp[J]. Electronics Letters. 2009,45(11):529-564.
[30]王志功,陈莹梅.集成电路设计[M].北京：机械工业出版社.2009.
[31]Jonhan H. Huijsing运算放大器理论与设计(影印版)[M].北京：清华大学出版社.2003.
[32]何乐年,王忆.模拟集成电路设计与仿真[M].北京：科学出版社.2008.
[33]张扬.一种低压轨至轨输入／输出稳定跨导运算放大器的设计[硕士论文].成都：西南交通大学硕士论文.2008.
[34]Chang Changyuan, Li Xian, Yao Jiannan, et al. Rail-to-rail op-amp with constant transconductance, SR and gain[J]. Journal of Southeast University (English Edition).2008, 24(2):163-167.
[35]Ahmadi M M. An Adaptive Biased Single-Stage CMOS Operational Amplifier with a Novel Rail-to-Rail Constant-gm Input Stage[J]. Analog Integrated Circuits and Signal Processing.2005,45(1):71-78.
[36]Reary J, Kovacs G T A. An unconditionally stable two-stage CMOS amplifier[J]. IEEE Journal of Solid-State Circuits.1995,30(5):591-594.
[37]Ahuja B K. An improved frequency compensation technique for CMOS operational amplifiers[J].IEEE Journal of Solid-State Circuits,1983,18(6):629-633.
[38]曹三林,何乐年.一种1.8V Rail-to-Rail CMOS运算放大器的设计[J].微电子学与计算机.2006,23(11)：121-125.
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