基于CSMC0.6μm CMOS Rail-to-Rail运算放大器的芯片设计研究
|
摘要
近年来,集成电路设计中的低电压设计技术受到了人们越来越多的关注。运算放大器(运放),作为一种通用、重要的集成单元电路,其低电压设计,具有重要的参考价值和实际应用价值。但是,随着电源电压的降低,受阈值电压的影响,运放的输入输出动态范围将不断减小,进而严重影响后级电路的正常工作。为了提高运放的输入输出动态范围,Rail-to-Rail运放的设计成为了研究热点。
本文首先对运算放大器电路进行了分析和设计。输入级采用基于前馈补偿电路结构的恒跨导Rail-to-Rail输入级,偏置电路采用宽摆幅共源共栅电流漏,输出级采用浮动电流源控制的前馈甲乙类输出级,补偿电路采用改进型的密勒补偿电容。同时为运放设计了一种基于电流模式曲率补偿的带隙基准电压源,测试结果表明,在-55-125℃的温度范围内该带隙基准源具有较低的温度系数,仅为7.69ppm／℃。
其次,采用标准的上华科技CSMC 0.6μm CMOS工艺参数,对整体电路的直流特性、瞬态特性以及交流特性进行了仿真和分析。仿真结果表明,运放达到了Rail-to-Rail的输入输出要求,静态功耗1.079mW,开环增益123.5dB,单位带宽积10.6MHz,相位裕度为54.8°。
最后,根据版图设计基础理论,基于CSMC 0.6μm工艺,分析电路的具体要求,设计出了电路中的单元器件。同时,根据全芯片的ESD保护架构,设计了基于FOD的ESD侦测泄放电路和基于SCR技术的ESD保护器件。最后对所设计的运放整体版图进行了设计规则检查和版图与原理图一致性检查,验证了版图设计的合理性。
Recently, the low-voltage design techniques in Analog IC Design have attracted more and more attention. As a common and important integrated cell circuit, the low-voltage design of the operational amplifier (Op-amp) has important reference and practical values. With the decrease of the voltage, however, the input and output dynamic range of the Op-amp will continuously reduce in the influence of the threshold voltage, which can seriously affect the normal operation of the post-stage circuit. In order to enhance the input and output dynamic range of the Op-amp, the design of the Rail-to-Rail Op-amp has become research hotspots.
In this thesis, the Op-amp was designed and analyzed firstly. The constant transconductance of the Rail-to-Rail input stage, which is on the basis of the feed-forward compensation circuit, was performed for the input stage. The biasing circuit is with the wide-swing current-drain circuit. The output stage is with the feed-forward class AB output stage controlled by the floating current source. The compensating circuit is improved by the Miller compensation capacitor. Meanwhile, a voltage band-gap reference based on the current-mode curvature compensation was designed. The simulating results indicated that the temperature coefficient of the voltage band-gap reference is merely 7.69ppm/℃under the temperature range of-55 to 125℃.
Thirdly, the DC characteristic, transient characteristic and the AC characteristics of the designed circuit were simulated and analyzed by using the standard CSMC 0.6μm CMOS technology process parameters. The simulation results revealed that the Op-amp meet the Rail-to-Rail input and output requirements. The Static power consumption is 1.079mW, the open-loop gain is 123.5dB, the unit-bandwidth product is 10.6MHz. and the phase margin is 54.8°.
Finally, with the CSMC 0.6μm technology process, the cell unit of the circuit was designed on the basis of the basic theory of layout design and the specific requirements of the whole circuit. Meanwhile, according to full-chip ESD protection architecture, the ESD detection discharge circuit was designed based on the FOD. and the ESD protection device was also designed by using the SCR technology. Then the whole layout was verified by the design rule and the rationality was also checked.
本文首先对运算放大器电路进行了分析和设计。输入级采用基于前馈补偿电路结构的恒跨导Rail-to-Rail输入级,偏置电路采用宽摆幅共源共栅电流漏,输出级采用浮动电流源控制的前馈甲乙类输出级,补偿电路采用改进型的密勒补偿电容。同时为运放设计了一种基于电流模式曲率补偿的带隙基准电压源,测试结果表明,在-55-125℃的温度范围内该带隙基准源具有较低的温度系数,仅为7.69ppm／℃。
其次,采用标准的上华科技CSMC 0.6μm CMOS工艺参数,对整体电路的直流特性、瞬态特性以及交流特性进行了仿真和分析。仿真结果表明,运放达到了Rail-to-Rail的输入输出要求,静态功耗1.079mW,开环增益123.5dB,单位带宽积10.6MHz,相位裕度为54.8°。
最后,根据版图设计基础理论,基于CSMC 0.6μm工艺,分析电路的具体要求,设计出了电路中的单元器件。同时,根据全芯片的ESD保护架构,设计了基于FOD的ESD侦测泄放电路和基于SCR技术的ESD保护器件。最后对所设计的运放整体版图进行了设计规则检查和版图与原理图一致性检查,验证了版图设计的合理性。
Recently, the low-voltage design techniques in Analog IC Design have attracted more and more attention. As a common and important integrated cell circuit, the low-voltage design of the operational amplifier (Op-amp) has important reference and practical values. With the decrease of the voltage, however, the input and output dynamic range of the Op-amp will continuously reduce in the influence of the threshold voltage, which can seriously affect the normal operation of the post-stage circuit. In order to enhance the input and output dynamic range of the Op-amp, the design of the Rail-to-Rail Op-amp has become research hotspots.
In this thesis, the Op-amp was designed and analyzed firstly. The constant transconductance of the Rail-to-Rail input stage, which is on the basis of the feed-forward compensation circuit, was performed for the input stage. The biasing circuit is with the wide-swing current-drain circuit. The output stage is with the feed-forward class AB output stage controlled by the floating current source. The compensating circuit is improved by the Miller compensation capacitor. Meanwhile, a voltage band-gap reference based on the current-mode curvature compensation was designed. The simulating results indicated that the temperature coefficient of the voltage band-gap reference is merely 7.69ppm/℃under the temperature range of-55 to 125℃.
Thirdly, the DC characteristic, transient characteristic and the AC characteristics of the designed circuit were simulated and analyzed by using the standard CSMC 0.6μm CMOS technology process parameters. The simulation results revealed that the Op-amp meet the Rail-to-Rail input and output requirements. The Static power consumption is 1.079mW, the open-loop gain is 123.5dB, the unit-bandwidth product is 10.6MHz. and the phase margin is 54.8°.
Finally, with the CSMC 0.6μm technology process, the cell unit of the circuit was designed on the basis of the basic theory of layout design and the specific requirements of the whole circuit. Meanwhile, according to full-chip ESD protection architecture, the ESD detection discharge circuit was designed based on the FOD. and the ESD protection device was also designed by using the SCR technology. Then the whole layout was verified by the design rule and the rationality was also checked.
引文
[1]毕查德·拉扎维著,陈贵灿,程军,张瑞智等译。模拟CMOS集成电路设计[M],西安交通大学出版社,2003
[2]潘学文。低压低功耗全摆幅CMOS运放[D],长沙,中南大学,2009
[3]Gray P. R, Meyer R. G. Mos Operational Amplifier design-a tutorial overview[J], IEEE Journal of Solid-State Circuits,1982, (17)6:969-982
[4]程春来,柴常春,唐重林。一种低压低功耗CMOS折叠-共源共栅运算放大器的设计[J],现代电子技术,2007
[5]叶·赛米尔著,周元兴译。低压低功耗CMOS/BiCMOS超大规模集成电路[J],电子工业出版社,2003：2-25
[6]傅锐飞。一种低压低功耗CMOS轨对轨运算放大器的设计[D],成都,电子科技大学,2009
[7]俞佳。Si单片高精度低失调运算放大器的研制[D],成都,电子科技大学,2005
[8]高长征,郝景红。1-4GHz微封装宽带放大器[J],半导体情报,2001,38(5)：40-41
[9]Allen Phillip E., Holberg Douglas R.著,冯军,李智群译。CMOS Analog Circuit Design (Second Edition) [M],电子工业出版社,2002：251-356
[10]杨刚,汪道辉。SOC与芯片设计方法[J],微计算机信息,2003
[11]王召。CMOS Rail-to-Rail运算放大器的分析与设计[D],西安,西北大学,2008
[12]Huijsing Johan H., Operational Amplifiers-Theory and Design[M].Belgium:Kluwer Academic Publishers,2001
[13]李联。MOS运算放大器-原理、设计与应用[M],上海,复旦大学出版社,1988
[14]叶俊等。一种适合VLSI库的Rail-to-Rail运算放大器[J],固体电子学研究与进展,2002,22(1)：107-113
[15]曹三林,何乐年。一种1.8V Rail-to-Rail CMOS运算放大器的设计[J],微电子学与计算机,2006,23(11)：121-125
[16]郑学军。低电压高精度运算放大器的设计研究[D],上海,华东师范大学,2002
[17]李拥平。低电压恒定增益Rail-to-Rail CMOS运算放大器设计[J],电子产品世界,2001,5(B)：67
[18]Gray P. R., Meyer R. G, Analysis and design of analog integrated circuits (fourth edition)[M],北京,高等教育出版社,2003
[19]Vinenee V. C., Montoro C. G., Sehneider M. C., A low-voltage cmos class-AB operational amplifier[M]. IEEE International Symposium. Universidade Federal de Santa Catarina.2002,(3):601-612
[20]高德远。超大规模集成电路[M],高等教育出版社,2003：43-86
[21]张扬。一种低压轨至轨输入输出稳定跨导运算放大器的设计[D],成都,西南交通大学,2008
[22]Stockstad T, Yoshizawa H. A 0.9V 0.5pA Rail-to-Rail CMOS operational amplifier[J]. IEEE Journal of Solid-State Circuits,2002:123-125
[23]张建人。MOS集成电路分析与设计基础[M],电子工业出版社,1987
[24]谢强。CMOS低功耗运算放大器的研究与设计[D],长沙,湖南大学,2006
[25]Juliano P. A. Measurement, modeling, and simulation of fast transients in ESD devices[M], Urbana University of Illinois at Urbana-Champaign,2001
[26]Amerasekera A, Duvvury C. ESD in silicon integrated circuits[M]. New York:john Wiley and Sons,2002
[27]Salcedo J.A, Liou J.J, Liu Z W, et al. TCAD Methodology for Design of SCR Devices for Electrostatic Discharge(ESD)Applications[J]. IEEE Transactions on Electron Devices, 2007,(54):822-832
[28]臧佳峰,薛忠杰。深亚微米CMOS IC全芯片ESD保护技术[J],电子与封装,2005,(6)：7-30
[29]Ker M.D, Chen T.Y. Substrate-triggered ESD protection circuit without extra process modification [J].IEEE Journal of Solid-State Circuits,2003,(38):295-302
[30]朱科翰。CMOS集成电路偏上静电放电防护器件的设计与分析[D],无锡,江南大学,2008
[31]Liou J.J, Salcedo J.A, Liu Z W.Robust. ESD Protection Solutions in CMOS/BiCMOS Technologies.Proceeding of 2007 International Workshop on Electron Devices and Semiconductor Technology[J],2007:41-45
[32]王昊鹏。CMOS工艺下集成电路内部ESD保护电路结构研究与可靠性分析[D],天津,天津大学,2007
[33]李冰,王刚,杨袁渊。基于SCR的ESD保护电路防闩锁设计[J],微电子学,2009,(12)：786-789
[2]潘学文。低压低功耗全摆幅CMOS运放[D],长沙,中南大学,2009
[3]Gray P. R, Meyer R. G. Mos Operational Amplifier design-a tutorial overview[J], IEEE Journal of Solid-State Circuits,1982, (17)6:969-982
[4]程春来,柴常春,唐重林。一种低压低功耗CMOS折叠-共源共栅运算放大器的设计[J],现代电子技术,2007
[5]叶·赛米尔著,周元兴译。低压低功耗CMOS/BiCMOS超大规模集成电路[J],电子工业出版社,2003：2-25
[6]傅锐飞。一种低压低功耗CMOS轨对轨运算放大器的设计[D],成都,电子科技大学,2009
[7]俞佳。Si单片高精度低失调运算放大器的研制[D],成都,电子科技大学,2005
[8]高长征,郝景红。1-4GHz微封装宽带放大器[J],半导体情报,2001,38(5)：40-41
[9]Allen Phillip E., Holberg Douglas R.著,冯军,李智群译。CMOS Analog Circuit Design (Second Edition) [M],电子工业出版社,2002：251-356
[10]杨刚,汪道辉。SOC与芯片设计方法[J],微计算机信息,2003
[11]王召。CMOS Rail-to-Rail运算放大器的分析与设计[D],西安,西北大学,2008
[12]Huijsing Johan H., Operational Amplifiers-Theory and Design[M].Belgium:Kluwer Academic Publishers,2001
[13]李联。MOS运算放大器-原理、设计与应用[M],上海,复旦大学出版社,1988
[14]叶俊等。一种适合VLSI库的Rail-to-Rail运算放大器[J],固体电子学研究与进展,2002,22(1)：107-113
[15]曹三林,何乐年。一种1.8V Rail-to-Rail CMOS运算放大器的设计[J],微电子学与计算机,2006,23(11)：121-125
[16]郑学军。低电压高精度运算放大器的设计研究[D],上海,华东师范大学,2002
[17]李拥平。低电压恒定增益Rail-to-Rail CMOS运算放大器设计[J],电子产品世界,2001,5(B)：67
[18]Gray P. R., Meyer R. G, Analysis and design of analog integrated circuits (fourth edition)[M],北京,高等教育出版社,2003
[19]Vinenee V. C., Montoro C. G., Sehneider M. C., A low-voltage cmos class-AB operational amplifier[M]. IEEE International Symposium. Universidade Federal de Santa Catarina.2002,(3):601-612
[20]高德远。超大规模集成电路[M],高等教育出版社,2003：43-86
[21]张扬。一种低压轨至轨输入输出稳定跨导运算放大器的设计[D],成都,西南交通大学,2008
[22]Stockstad T, Yoshizawa H. A 0.9V 0.5pA Rail-to-Rail CMOS operational amplifier[J]. IEEE Journal of Solid-State Circuits,2002:123-125
[23]张建人。MOS集成电路分析与设计基础[M],电子工业出版社,1987
[24]谢强。CMOS低功耗运算放大器的研究与设计[D],长沙,湖南大学,2006
[25]Juliano P. A. Measurement, modeling, and simulation of fast transients in ESD devices[M], Urbana University of Illinois at Urbana-Champaign,2001
[26]Amerasekera A, Duvvury C. ESD in silicon integrated circuits[M]. New York:john Wiley and Sons,2002
[27]Salcedo J.A, Liou J.J, Liu Z W, et al. TCAD Methodology for Design of SCR Devices for Electrostatic Discharge(ESD)Applications[J]. IEEE Transactions on Electron Devices, 2007,(54):822-832
[28]臧佳峰,薛忠杰。深亚微米CMOS IC全芯片ESD保护技术[J],电子与封装,2005,(6)：7-30
[29]Ker M.D, Chen T.Y. Substrate-triggered ESD protection circuit without extra process modification [J].IEEE Journal of Solid-State Circuits,2003,(38):295-302
[30]朱科翰。CMOS集成电路偏上静电放电防护器件的设计与分析[D],无锡,江南大学,2008
[31]Liou J.J, Salcedo J.A, Liu Z W.Robust. ESD Protection Solutions in CMOS/BiCMOS Technologies.Proceeding of 2007 International Workshop on Electron Devices and Semiconductor Technology[J],2007:41-45
[32]王昊鹏。CMOS工艺下集成电路内部ESD保护电路结构研究与可靠性分析[D],天津,天津大学,2007
[33]李冰,王刚,杨袁渊。基于SCR的ESD保护电路防闩锁设计[J],微电子学,2009,(12)：786-789