嵌入式多通路10位SAR ADC设计
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摘要
系统级芯片(SoC: System on Chip)的不断发展,在推动微控制器(MCU)、数字信号处理器(DSP)、微机械电子系统(MEMS)的发展的同时,也推动了嵌入式模数转换技术的发展。作为自然界模拟信号与计算机可处理的数字信号的交互界面,嵌入式ADC涉及到通信、交通运输、医疗设备、数据采集系统、工业工程控制等诸多方面,成为嵌入式系统不可或缺的重要模块之一。
为了满足嵌入式系统对ADC的面积小、功耗小、易实现等要求,本文采用逐次逼近型电路结构,设计了一款10位8通路输入的模数转换器,设计整体分为模拟与数字两个子系统,模拟子系统包括模拟多路复用器、缓冲放大器、偏置电路、比较器、复合型DAC。其中,缓冲放大器采用轨至轨输入的电压跟随器结构,使其可在电源电压至地的范围内对信号进行无误差传输;比较器采用三级级联、自动较零的高速比较器结构,不仅实现了高增益,还减小了传输延迟,其比较精度为3mV;DAC采用了电阻分压及电荷分配相结合的复合结构,其中高七位采用等值电阻分压结构,低三位采用电荷分配结构。这种分段复合的结构不断避免了大电容引入的匹配性问题,还缓解了由于制造工艺带来的电阻误差所引起的精度下降问题。数字子系统包括逐次移位寄存器、状态机及时序控制逻辑,其中逐次移位寄存器为系统提供二进制逐次逼近算法;状态机根据需要,控制系统在系统空闲、缓冲放大器采样、缓冲放大器旁路采样、逐次逼近转换四个工作状态下工作;时序控制逻辑则根据系统的不同工作状态,来控制系统的工作时序。本设计由双电源供电,其中模拟电压为3.3V,数字电压为1.8V。电路版图采用和舰公司的0.18μm工艺完成了关键模拟子电路的版图设计。
The development of SoC(system on chip) promote the technology progresses of MCU, DSP, MEMS as well as the embedded analog-to digital converters. As the interface of analog signal in the nature and the digital signal that the computers can handle, embedded ADCs are involved in areas of communication, transportation, medical equipments, data acquisition systems industrial process control and so on. Embedded ADCs are already become a indispensable part of SoC.
Consider the demand of small area, low power, easy to implement from SoC, design and implement of an 8-channel 10-bit ADC is described in this paper. Successive Approximation Register (SAR) is the configuration adopted. The whole system is divided into two parts: analog sub-system and digital–sub-system. The analog sub-system is consists of analog multiplexing, buffer amplifier, bias circuit, comparator and compound DAC. There into, buffer amplifier is applied of Rail-to-Rail structure, it can track the input signal from power supply to ground potential; Comparator used three-state, automatic zero, high-speed structure, it can not only achieve a high gain, but also reduce the transmission delay; A structure of equal-valued resistors and rationed capacitors assembled is adopted in DAC implement, which avoids the mismatch of big capacitors and the linear error caused by application of resistors. The digital sub-system is consists of SAR, which applied the dichotomy arithmetic; state machine, which controls the whole system to work among the states of SM_IDLE, SM_BUF, SM_FINAL and SM_CONV; the timing logic, which control the timing in different states. The power of analog sub-system is 3.3V, and the power of digital sub-system is 1.8V. Layout of analog part is full custom designed through 0.18μm technology of HeJian Company.
为了满足嵌入式系统对ADC的面积小、功耗小、易实现等要求,本文采用逐次逼近型电路结构,设计了一款10位8通路输入的模数转换器,设计整体分为模拟与数字两个子系统,模拟子系统包括模拟多路复用器、缓冲放大器、偏置电路、比较器、复合型DAC。其中,缓冲放大器采用轨至轨输入的电压跟随器结构,使其可在电源电压至地的范围内对信号进行无误差传输;比较器采用三级级联、自动较零的高速比较器结构,不仅实现了高增益,还减小了传输延迟,其比较精度为3mV;DAC采用了电阻分压及电荷分配相结合的复合结构,其中高七位采用等值电阻分压结构,低三位采用电荷分配结构。这种分段复合的结构不断避免了大电容引入的匹配性问题,还缓解了由于制造工艺带来的电阻误差所引起的精度下降问题。数字子系统包括逐次移位寄存器、状态机及时序控制逻辑,其中逐次移位寄存器为系统提供二进制逐次逼近算法;状态机根据需要,控制系统在系统空闲、缓冲放大器采样、缓冲放大器旁路采样、逐次逼近转换四个工作状态下工作;时序控制逻辑则根据系统的不同工作状态,来控制系统的工作时序。本设计由双电源供电,其中模拟电压为3.3V,数字电压为1.8V。电路版图采用和舰公司的0.18μm工艺完成了关键模拟子电路的版图设计。
The development of SoC(system on chip) promote the technology progresses of MCU, DSP, MEMS as well as the embedded analog-to digital converters. As the interface of analog signal in the nature and the digital signal that the computers can handle, embedded ADCs are involved in areas of communication, transportation, medical equipments, data acquisition systems industrial process control and so on. Embedded ADCs are already become a indispensable part of SoC.
Consider the demand of small area, low power, easy to implement from SoC, design and implement of an 8-channel 10-bit ADC is described in this paper. Successive Approximation Register (SAR) is the configuration adopted. The whole system is divided into two parts: analog sub-system and digital–sub-system. The analog sub-system is consists of analog multiplexing, buffer amplifier, bias circuit, comparator and compound DAC. There into, buffer amplifier is applied of Rail-to-Rail structure, it can track the input signal from power supply to ground potential; Comparator used three-state, automatic zero, high-speed structure, it can not only achieve a high gain, but also reduce the transmission delay; A structure of equal-valued resistors and rationed capacitors assembled is adopted in DAC implement, which avoids the mismatch of big capacitors and the linear error caused by application of resistors. The digital sub-system is consists of SAR, which applied the dichotomy arithmetic; state machine, which controls the whole system to work among the states of SM_IDLE, SM_BUF, SM_FINAL and SM_CONV; the timing logic, which control the timing in different states. The power of analog sub-system is 3.3V, and the power of digital sub-system is 1.8V. Layout of analog part is full custom designed through 0.18μm technology of HeJian Company.
引文
1.苗长云,曹晓东,李鸿强. SoC及其IP核的设计与其在通信中的应用研究.天津工业大学学报. 2005,24(1):59～63
2.张惠泉,赵建忠,严晓浪.我国半导体的发展现状及新一轮发展的思考.中国集成电路. 2005,(72):7~8
3. J. L. Mc Creary, P. R. Gray. A high-speed All- MOS Successive-Approximation Weighted-Cpapcitor A/D Converter Technique. ISSCC Dig. Tech Papers. 1975:38~39
4. M. Steyaert, R. Roovers, and J. Craninckx. A 100MHz 8-bot CMOS Interpolating A/D Converter. IEEE Custom Integrated Circuits Conference, 1993,(5):11~14
5. M. Dessouky, A. Kaiser. A 1-V 1-mW Digital-AudioΣ-ΔModulator with 88-dB Dynamic Range using Local Switch Bootstrapping. IEEE Custom Integrated Circuits Conf. 2000:13~16
6. Jiren Yuan, Chirster Svensson. A 10-bit 5-MS/s Successive Ppproximation ADC Cell Used in a 70-MS/s ADC Array in 1.2μm COMS. IEEE J. Solid-State Circuits. 1994,(129):866~872
7. J. Doemberg, P Gray. A 10-bit 5-M sample/s CMOS Two-step Flash ADC. IEEE J. Solid-State Circuits. 1996,(2):320~321
8. R. T. Baird , T. S. Fiez. A Low Over Sampling Radio 14-b 500-KHzΣ-ΔADC with a Self-Calibrated Multibit DAC, IEEE J. Solid-State Circuits, 1996,(31):312~30
9. C. S. G.conroy, D.W. Cline, P. R. Gray. A 8-bit 85-MS/s Parallel Pipeline A/D Converter in 1-μm CMOS. IEEE J. Solid-State Circuits. 1991,(26):628~636
10. M. Choi, A. Abidi. A 6-b 1.3G sample/s A/D Converter in 0.35-μm CMOS. IEEE J. Solid-State Circuits, 2001,(36):1847~1858
11. Chong Min Kyung, Choong Ki Kim, Pipeline Analog to Digital Convertersion with Charge-Coupled Devices. IEEE J. Solid-State Circuits. 1980,(15):255~257
12. S. Mortezapour, E Lee. A 1-V 8-bit Successive Opproximation ADC in Standard CMOS Process. IEEE J. Solid-State Circuit. 2000,(35):642~646
13. R. H. Walden. Analog-to-Digital Converter Survey and Analysis. IEEE Journal on Selected Areas in Communications. 1999,(17):4~6
14.李彦旭,成立,巴大志.低电压、低功耗高速A/D转换器及其应用前景.半导体技术. 2002,27(7):6~9
15. P. E. Allen, D. R Holberg. CMOS Analog Circuit Design.电子工业出版社, 2005:553~554
16. B. Razavi. Principle of Data Convertion System Design. IEEE Press. 1995:19~20
17. S. V. Rylov, L. A Bunz, D. V. Gaidarenko. High Resolution ADC System. IEEE Transactions on Applied Superconductivity.1997,7(2):2649~2652
18. J. Raczkowycz, S. Allott. Embedded ADC Characterization Techniques. IEEE Proc-Circuit Device Syst.1995,142(3):145~152
19.洪权,林凌,李刚. 18位高速低有效位积分非线性逐次逼近ADC芯片AD7678.电子元器件应用. 2005,(11):93~97
20. Min-Jung Kim, Hyun-Sang Yoon. An 11-b 70MHz 1.2mm2 49mW 0.18μm CMOS ADC with On-Chip Current/Voltage Referefces. ESSCIRC. 2002:463~466
21. Kh. Handidi, Vincent S. Tso. An 8-b 1.3-MHz Successive Approximation A/D Converter, IEEE J. Solid-State Circuit. 1990,25(3):166~170
22.王树红.几种A/ D转换技术及性能特点的分析.山西电子技术. 2004,(5):34~38
23. Guo-Ruey Tsai, Min-Chuan Lin.high. Speed Signal Sampler by Multitiple-Path Algorithm. IEEE. 2004:29~31
24.鲁靖梅. 10位逐次逼近式模数转换器中的数模转换器实现.合肥工业大学硕士论文.2004:35~43
25. D. W. Cline, P. R. Gary. A Power Opimized 13-bits 5Msample Pipelined A/D Converter in 1.2μm CMOS. IEEE Solid State Circuit. 1996,31(3):294-303
26.菜俊,徐美华,冉峰. 10位逐次逼近型A/D转换器的芯片设计.半导体技术. 2004,29(4):73~76
27. Y. C. Lau. Error Correction of Capacitor Voltage Nonlinearity for a Charge Redistribution Analog-to-Digital Converter. M. S. Project Rep Univ. of California, Berkeley.1983.
28. K. S. Tan. Error Correction Techniques for High-Performance DifferentialA/D Converters. IEEE J. Solid-State Circuits. 1990,(25):1318-1327
29. P. Metal. A 25-Ms/s 8-bit CMOS A/D Converter for Embeded Application, JSSC. 1994, 29(8): 879~886
30.胡湘江,肖怀铁.一种多通道、高精度A/D、D/A转换电路的设计与实现.电子设计应用. 2003(11):78~80
31. J. M. Rabaey, A. Chandrakasan. Digital Integrated Circuits.电子工业出版社. 2006:194~196
32. B. Razavi. Design of Analog CMOS Intergrated Circuits.西安交通大学出版社. 2002:312~320
33.陈友福,李平,刘银.一种新型的BiCMOS带隙基准电压源设计.微电子学. 2006(36): 381~384
34. S. H. Lee, Y. Jee. A Temperature and Supply-Voltage Insensitive CMOS Current Reference. IEICE Trans. 1999,(82):1562-1566
35. S. Baswa, J. R. Angulo. Rail-to-Rail Super Class AB CMOS Operational Amplifiers. Electronics Lettera. 2005,(41):17~19
36. S. V. Rylov. Novel Architecture for Superconducting Flux-Quantizing A/D Converters. Extended Abstracts of ISEC. 1993:112~113
37.盛权为,陈实,谢长焱.一种低电压、全摆幅、恒跨导CMOS运算放大器.长沙医学院学报. 2006.12(6):43~46
38.李详生,陈殿玉,秦世才. 2.5V/0.25μm Rail-to\Rail运算放大器.南开大学学报(自然科学版). 2004,37(3):20~23
39. R. Hogrvost. A Compact Power-Efficient 3V CMOS Rail-to-Rail Input/Output Operational Amplifier for VLSI Cell Libraries[J]. IEEE Journal of Solid Circuits. 1994, 29:1505~1513
40. R. R. Hester. Fully differential ADC with Rail-to-Rail Common-Mode Range and Nonlinear Capacitor Compensation. IEEE J. Solid-State Circuits. 1990,(25):173~183
41. K. Hadidi, C. G. Temes. A High Resolution, Low Offset and High Speed Comparator. IEEE. 1992:161~164
42. Zhiliang Zheng, Un-Ku Moon. cap. Mismatch error Cancellation Technique for a Successive Approximation A/D Converter. IEEE. 1999:326~329
43. S. V. Rylov, L. A. Bunz, D. V. Gaidarenko. High Resolution ADC System. IEEE Transitional on Applied Superconductivity. 1997,7(2):2649~2652
44. B. Razavi. Design Techniques for High-Speed, High Resolution Comparators. IEEE Jssc. 1992,(27):56~60
45. T. M. Souders. Code Probability Distribution of A/D Convectors with Random Input Noise. IEEE Instrumentation and Measurement Technology Conference St. Paul, MN USA, May 1998:152~155
46. A. Shrivastava. 12-bit non-calibrating noise-immune redundant SAR ADC for System-on-a-Chip. IEEE. 2006:1515~1518
47. S. Jamal, D. Fu. A 10b 120MSample/s Time-Interleaved Analog-to-Digital Converter with Digital Background Calibration. ISSCC Dig. Tech. Paper. 2002, (2):172~173
2.张惠泉,赵建忠,严晓浪.我国半导体的发展现状及新一轮发展的思考.中国集成电路. 2005,(72):7~8
3. J. L. Mc Creary, P. R. Gray. A high-speed All- MOS Successive-Approximation Weighted-Cpapcitor A/D Converter Technique. ISSCC Dig. Tech Papers. 1975:38~39
4. M. Steyaert, R. Roovers, and J. Craninckx. A 100MHz 8-bot CMOS Interpolating A/D Converter. IEEE Custom Integrated Circuits Conference, 1993,(5):11~14
5. M. Dessouky, A. Kaiser. A 1-V 1-mW Digital-AudioΣ-ΔModulator with 88-dB Dynamic Range using Local Switch Bootstrapping. IEEE Custom Integrated Circuits Conf. 2000:13~16
6. Jiren Yuan, Chirster Svensson. A 10-bit 5-MS/s Successive Ppproximation ADC Cell Used in a 70-MS/s ADC Array in 1.2μm COMS. IEEE J. Solid-State Circuits. 1994,(129):866~872
7. J. Doemberg, P Gray. A 10-bit 5-M sample/s CMOS Two-step Flash ADC. IEEE J. Solid-State Circuits. 1996,(2):320~321
8. R. T. Baird , T. S. Fiez. A Low Over Sampling Radio 14-b 500-KHzΣ-ΔADC with a Self-Calibrated Multibit DAC, IEEE J. Solid-State Circuits, 1996,(31):312~30
9. C. S. G.conroy, D.W. Cline, P. R. Gray. A 8-bit 85-MS/s Parallel Pipeline A/D Converter in 1-μm CMOS. IEEE J. Solid-State Circuits. 1991,(26):628~636
10. M. Choi, A. Abidi. A 6-b 1.3G sample/s A/D Converter in 0.35-μm CMOS. IEEE J. Solid-State Circuits, 2001,(36):1847~1858
11. Chong Min Kyung, Choong Ki Kim, Pipeline Analog to Digital Convertersion with Charge-Coupled Devices. IEEE J. Solid-State Circuits. 1980,(15):255~257
12. S. Mortezapour, E Lee. A 1-V 8-bit Successive Opproximation ADC in Standard CMOS Process. IEEE J. Solid-State Circuit. 2000,(35):642~646
13. R. H. Walden. Analog-to-Digital Converter Survey and Analysis. IEEE Journal on Selected Areas in Communications. 1999,(17):4~6
14.李彦旭,成立,巴大志.低电压、低功耗高速A/D转换器及其应用前景.半导体技术. 2002,27(7):6~9
15. P. E. Allen, D. R Holberg. CMOS Analog Circuit Design.电子工业出版社, 2005:553~554
16. B. Razavi. Principle of Data Convertion System Design. IEEE Press. 1995:19~20
17. S. V. Rylov, L. A Bunz, D. V. Gaidarenko. High Resolution ADC System. IEEE Transactions on Applied Superconductivity.1997,7(2):2649~2652
18. J. Raczkowycz, S. Allott. Embedded ADC Characterization Techniques. IEEE Proc-Circuit Device Syst.1995,142(3):145~152
19.洪权,林凌,李刚. 18位高速低有效位积分非线性逐次逼近ADC芯片AD7678.电子元器件应用. 2005,(11):93~97
20. Min-Jung Kim, Hyun-Sang Yoon. An 11-b 70MHz 1.2mm2 49mW 0.18μm CMOS ADC with On-Chip Current/Voltage Referefces. ESSCIRC. 2002:463~466
21. Kh. Handidi, Vincent S. Tso. An 8-b 1.3-MHz Successive Approximation A/D Converter, IEEE J. Solid-State Circuit. 1990,25(3):166~170
22.王树红.几种A/ D转换技术及性能特点的分析.山西电子技术. 2004,(5):34~38
23. Guo-Ruey Tsai, Min-Chuan Lin.high. Speed Signal Sampler by Multitiple-Path Algorithm. IEEE. 2004:29~31
24.鲁靖梅. 10位逐次逼近式模数转换器中的数模转换器实现.合肥工业大学硕士论文.2004:35~43
25. D. W. Cline, P. R. Gary. A Power Opimized 13-bits 5Msample Pipelined A/D Converter in 1.2μm CMOS. IEEE Solid State Circuit. 1996,31(3):294-303
26.菜俊,徐美华,冉峰. 10位逐次逼近型A/D转换器的芯片设计.半导体技术. 2004,29(4):73~76
27. Y. C. Lau. Error Correction of Capacitor Voltage Nonlinearity for a Charge Redistribution Analog-to-Digital Converter. M. S. Project Rep Univ. of California, Berkeley.1983.
28. K. S. Tan. Error Correction Techniques for High-Performance DifferentialA/D Converters. IEEE J. Solid-State Circuits. 1990,(25):1318-1327
29. P. Metal. A 25-Ms/s 8-bit CMOS A/D Converter for Embeded Application, JSSC. 1994, 29(8): 879~886
30.胡湘江,肖怀铁.一种多通道、高精度A/D、D/A转换电路的设计与实现.电子设计应用. 2003(11):78~80
31. J. M. Rabaey, A. Chandrakasan. Digital Integrated Circuits.电子工业出版社. 2006:194~196
32. B. Razavi. Design of Analog CMOS Intergrated Circuits.西安交通大学出版社. 2002:312~320
33.陈友福,李平,刘银.一种新型的BiCMOS带隙基准电压源设计.微电子学. 2006(36): 381~384
34. S. H. Lee, Y. Jee. A Temperature and Supply-Voltage Insensitive CMOS Current Reference. IEICE Trans. 1999,(82):1562-1566
35. S. Baswa, J. R. Angulo. Rail-to-Rail Super Class AB CMOS Operational Amplifiers. Electronics Lettera. 2005,(41):17~19
36. S. V. Rylov. Novel Architecture for Superconducting Flux-Quantizing A/D Converters. Extended Abstracts of ISEC. 1993:112~113
37.盛权为,陈实,谢长焱.一种低电压、全摆幅、恒跨导CMOS运算放大器.长沙医学院学报. 2006.12(6):43~46
38.李详生,陈殿玉,秦世才. 2.5V/0.25μm Rail-to\Rail运算放大器.南开大学学报(自然科学版). 2004,37(3):20~23
39. R. Hogrvost. A Compact Power-Efficient 3V CMOS Rail-to-Rail Input/Output Operational Amplifier for VLSI Cell Libraries[J]. IEEE Journal of Solid Circuits. 1994, 29:1505~1513
40. R. R. Hester. Fully differential ADC with Rail-to-Rail Common-Mode Range and Nonlinear Capacitor Compensation. IEEE J. Solid-State Circuits. 1990,(25):173~183
41. K. Hadidi, C. G. Temes. A High Resolution, Low Offset and High Speed Comparator. IEEE. 1992:161~164
42. Zhiliang Zheng, Un-Ku Moon. cap. Mismatch error Cancellation Technique for a Successive Approximation A/D Converter. IEEE. 1999:326~329
43. S. V. Rylov, L. A. Bunz, D. V. Gaidarenko. High Resolution ADC System. IEEE Transitional on Applied Superconductivity. 1997,7(2):2649~2652
44. B. Razavi. Design Techniques for High-Speed, High Resolution Comparators. IEEE Jssc. 1992,(27):56~60
45. T. M. Souders. Code Probability Distribution of A/D Convectors with Random Input Noise. IEEE Instrumentation and Measurement Technology Conference St. Paul, MN USA, May 1998:152~155
46. A. Shrivastava. 12-bit non-calibrating noise-immune redundant SAR ADC for System-on-a-Chip. IEEE. 2006:1515~1518
47. S. Jamal, D. Fu. A 10b 120MSample/s Time-Interleaved Analog-to-Digital Converter with Digital Background Calibration. ISSCC Dig. Tech. Paper. 2002, (2):172~173