低压CMOS运放的可复用设计
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摘要
目前片上系统(SoC)大多是采用深亚微米工艺设计的。基于缩短IC设计周期的考虑,特别在数字电路系统设计中,IP设计复用(reuse)技术得到广泛的重视和发展,但对于模拟IP的设计复用技术的研究和应用则相对落后,迫切需要开展针对模拟IP的设计复用技术研究。同时随着便携式电子产品的普及,低电压设计已成为电路系统工作的基本要求。
本论文设计工作来源于西安电子科技大学电路设计研究所的科研项目“模拟IP设计复用和验证技术研究”,以模拟集成电路中最基本和最重要的单元——运算放大器作为研究对象,对其在片上系统设计中的可复用和低电压设计进行深入研究。首先详细介绍了IP设计复用的重要性以及模拟IP复用的发展局限,其次针对低电压CMOS运算放大器的可复用设计要求,分别讨论并设计实现了低压运算放大器的电路设计和版图设计。
基于台积电TSMC0.6umCMOS工艺,利用Cadence、Hspice等EDA工具,对所设计的低压可复用运算放大器进行了仿真验证。仿真结果表明,该运放的性能指标优良,电源电压工作范围可达5~2.5V。典型情况下,开环增益为102dB,增益带宽为6.25MHz,相位裕度88.77度,电源电压抑制比80dB,共模抑制比为72dB,可满足大多数数模混合电路及片上系统内的应用要求。本设计已成功应用于XDM02项目中,流片结果表明该低压运放工作正常。
The design of System on a chip (SoC) is mostly based on the deep sub-micronatpresent. In view of shortening the cycle of IC design, especially the design of digitalcircuit system, IP design reuse technology is broadly attached importance to anddeveloped, but the research and application of analog IP design reuse technology getsbehind for digital IP. It is urgent to research and develop analog IP reuse technology.With the popularizationof portable electronics at the same time, low voltage design hasbecometheessentialrequirementofcircuitsystemforworking.
The paper is based on the project, research of analog IP design reuse andverification technology, which comes from Institute of Electronic CAD of XidianUniversity.Taking operational amplifier(op amp), the most basic and important cellin the analog integrated circuit, for research object, the paper makes an intensivestudy of the reusabilityandlowvoltagedesign ofop ampinthe design of SoC.Firstly,thepaperpresentstheimportanceofIPreuse designandlimitationofanalogIPindetail;secondly, based on requirement for the reuse design of low voltage CMOS op amp, thepaper separately discusses and presents the low voltage op amp design of circuit andlayout.
TheICdesignoflowvoltageopamp isbasedontheTSMC0.6umCMOSprocess,andthepre-simulationoflowvoltage reusableop amphasbeen completedbyusingtheEDA tools, such as Cadence and Hspice. The results of simulation indicate thatperformance index of this op amp is good, operatingsupply voltage range is5~2.5V.Inthe typical model, open loop gain is 102dB, gain bandwidth is 6.25MHz, phase marginis 88.77o, PSRR is 80dB, CMRR is 72dB, so the low voltage op amp can be applied inmost digital-analog mixed circuitsand SoC.This design has been applied in the projectXDM02, and also it has been taped out. The result indicates low voltage op amp is ingoodworkingorder.
本论文设计工作来源于西安电子科技大学电路设计研究所的科研项目“模拟IP设计复用和验证技术研究”,以模拟集成电路中最基本和最重要的单元——运算放大器作为研究对象,对其在片上系统设计中的可复用和低电压设计进行深入研究。首先详细介绍了IP设计复用的重要性以及模拟IP复用的发展局限,其次针对低电压CMOS运算放大器的可复用设计要求,分别讨论并设计实现了低压运算放大器的电路设计和版图设计。
基于台积电TSMC0.6umCMOS工艺,利用Cadence、Hspice等EDA工具,对所设计的低压可复用运算放大器进行了仿真验证。仿真结果表明,该运放的性能指标优良,电源电压工作范围可达5~2.5V。典型情况下,开环增益为102dB,增益带宽为6.25MHz,相位裕度88.77度,电源电压抑制比80dB,共模抑制比为72dB,可满足大多数数模混合电路及片上系统内的应用要求。本设计已成功应用于XDM02项目中,流片结果表明该低压运放工作正常。
The design of System on a chip (SoC) is mostly based on the deep sub-micronatpresent. In view of shortening the cycle of IC design, especially the design of digitalcircuit system, IP design reuse technology is broadly attached importance to anddeveloped, but the research and application of analog IP design reuse technology getsbehind for digital IP. It is urgent to research and develop analog IP reuse technology.With the popularizationof portable electronics at the same time, low voltage design hasbecometheessentialrequirementofcircuitsystemforworking.
The paper is based on the project, research of analog IP design reuse andverification technology, which comes from Institute of Electronic CAD of XidianUniversity.Taking operational amplifier(op amp), the most basic and important cellin the analog integrated circuit, for research object, the paper makes an intensivestudy of the reusabilityandlowvoltagedesign ofop ampinthe design of SoC.Firstly,thepaperpresentstheimportanceofIPreuse designandlimitationofanalogIPindetail;secondly, based on requirement for the reuse design of low voltage CMOS op amp, thepaper separately discusses and presents the low voltage op amp design of circuit andlayout.
TheICdesignoflowvoltageopamp isbasedontheTSMC0.6umCMOSprocess,andthepre-simulationoflowvoltage reusableop amphasbeen completedbyusingtheEDA tools, such as Cadence and Hspice. The results of simulation indicate thatperformance index of this op amp is good, operatingsupply voltage range is5~2.5V.Inthe typical model, open loop gain is 102dB, gain bandwidth is 6.25MHz, phase marginis 88.77o, PSRR is 80dB, CMRR is 72dB, so the low voltage op amp can be applied inmost digital-analog mixed circuitsand SoC.This design has been applied in the projectXDM02, and also it has been taped out. The result indicates low voltage op amp is ingoodworkingorder.
引文
[1]林慧君.IP质量评估技术的研究.合肥:合肥工业大学硕士论文,2004.1-5
[2]赵梦恋.SPIC设计方法与IP设计技术研究.杭州:浙江大学博士学位论文,2004.7-9
[3]李加元、成立、王振宇等.系统芯片设计中的可复用IP技术.半导体技术.2006,1.31(1).15-16
[4]林灶生、刘绍汉.Verilog FPGA芯片设计.北京:北京航空航天大学出版社,2006.4-8
[5] P.Magashack . Improving SoC Design Quality through Reproducible Design Flow.IEEEDesign&TestofComputers,2002.76-83
[6]王自强.CMOS集成放大器设计.北京:国防工业出版社,2007.3-5,157-271
[7]吴金、姚建楠、常昌远.CMOS模拟IP线性集成电路.南京:东南大学出版社,2007.4-10
[8]毕查德·拉扎维.模拟CMOS集成电路设计.西安:西安交通大学出版社,2002.1-6,138-141
[9]吕蓉.IP核及其复用.微电子与基础产品.2001,5.27(8).55-56
[10]葛晨阳、徐维朴、孙飞.IP复用技术研究.微电子学.2002,8.32(4).257-260
[11]牛风举、朱明程.芯片设计中的IP技术.半导体技术.2001,10.26(10).21-25
[12] Jozwiak L.Quality-driven system-on-a-chip design.IEEE 2000 First InternationalSymposiumonQualityElectronicDesign,2000.93-102
[13] Savage W, Chilton L, Camposano R. IP reuse in the system on a chip era.Proceedingsofthe13thInternationalSymposiumonSystemSynthesis,2000.2-7
[14] Saleh. R ,Wilton .S, Mirabbasi .S. System on Chip: Reuse and integration.ProceedingsoftheIEEE,2006.1050-1068
[15]韩泽耀、叶润涛.模拟/混合信号硬件描述语言VHDL—AMS综述.微电子学.2001,4.32(2).83-86
[16]贾政亚、张丽燕、黄云川.一种轨至轨输入的低压低功耗运放的设计.成都电子机械高等专科学校学报.2005,6.31(2).13-16
[17] Phillip E.Allen, Douglas R.Holberg著.冯军、李智群译.CMOS模拟集成电路设计.北京:电子工业出版,2005.149-224
[18]贾政亚.低压微功耗CMOS运算放大器的研究与设计.成都:电子科技大学硕士论文,2005.23-25
[19]黄云川.低压微功耗轨至轨输出CMOS运放研究设计.成都:电子科技大学硕士论文,2005.15-17
[20]徐跃、傅兴华.低电压模拟集成电路设计技术.微电子学.2004,8.34(4).451-454
[21] R.Jacob Baker, Harry W.Li, David E.Boyce. CMOS电路设计·布局与仿真.北京:机械工业出版社,2006.358-368
[22]曾宏、曾璇、闵昊.超深亚微米下百万门级系统级芯片的物理设计方案.复旦学报(自然科学版).2006,2.45(1).26-29
[23] Rafael Castro-López, O. Guerra, E. Roca, An Integrated Layout-SynthesisApproach for Analog ICs. IEEE Transactions on Computer-Aided Design ofIntegrated CircuitsandSystems,2008.1179-1189
[24] Alan Hastings著.张为等译.模拟电路版图的艺术.北京:电子工业出版社,2007.232-243
[25]金善子.模拟电路版图设计中的匹配艺术.中国集成电路.2006,12.91.48-51
[26] Chung-Chih Hung, ChangKu Hwang, HalonenK.Design ofCMOS Analog Cellsfor Low-Voltage VLSI. IEEE39th Midwest Symposium on Circuits and Systems,1996.15-18
[27] Chih-MinYu, Zhi-Ming Lin, Jun-Da Chen. A Low Voltage High Unity-GainBandwidth CMOS Op-Amp. The 2004 IEEE Asia-Pacific Conference on CircuitsandSystems,2004.45-48
[28] S V Gopalaiah ,AP Shivaprasad. LowVoltage CMOS Op-Amp with Rail-to-RailInput/Output Swing. Proceedings of the Second IEEE International Workshop onElectronicDesign,TestandApplications,2004.349-354
[29]尹韬、朱樟明、杨银堂.衬底驱动MOSFET特征分析和超低压运算放大器的设计.半导体学报,2005,1.26(1).158-162
[30]HuseyinDinc,SeanChuang, PhillipAllen.ARailtoRail, slew-BoostedPre-chargeBuffer.IEEEInternationalSymposiumonCircuitsandSystems,2006.65-68
[31] A.Masoom, Kh.Hadidi.A 1.5V Constant-Gm Rail to Rail Input Stage OperationalAmplifier. Proceedings of the IEEE international Conference on Electronics,CircuitsandSystems,2006.632-635
[32] Li Xian, Chang Changyuan, Lijuan. A Rail to Rail Op Amp for VLSI Cell withConstant Performance. European Conference on Circuit Theory and Design,2007.16-19
[33] Sarkar.S, Shinde.S , Chandar. S. An Effective IP Reuse Methodology for QualitySoC Design Proceedings of International Symposium on System on Chip,2005.104-107
[2]赵梦恋.SPIC设计方法与IP设计技术研究.杭州:浙江大学博士学位论文,2004.7-9
[3]李加元、成立、王振宇等.系统芯片设计中的可复用IP技术.半导体技术.2006,1.31(1).15-16
[4]林灶生、刘绍汉.Verilog FPGA芯片设计.北京:北京航空航天大学出版社,2006.4-8
[5] P.Magashack . Improving SoC Design Quality through Reproducible Design Flow.IEEEDesign&TestofComputers,2002.76-83
[6]王自强.CMOS集成放大器设计.北京:国防工业出版社,2007.3-5,157-271
[7]吴金、姚建楠、常昌远.CMOS模拟IP线性集成电路.南京:东南大学出版社,2007.4-10
[8]毕查德·拉扎维.模拟CMOS集成电路设计.西安:西安交通大学出版社,2002.1-6,138-141
[9]吕蓉.IP核及其复用.微电子与基础产品.2001,5.27(8).55-56
[10]葛晨阳、徐维朴、孙飞.IP复用技术研究.微电子学.2002,8.32(4).257-260
[11]牛风举、朱明程.芯片设计中的IP技术.半导体技术.2001,10.26(10).21-25
[12] Jozwiak L.Quality-driven system-on-a-chip design.IEEE 2000 First InternationalSymposiumonQualityElectronicDesign,2000.93-102
[13] Savage W, Chilton L, Camposano R. IP reuse in the system on a chip era.Proceedingsofthe13thInternationalSymposiumonSystemSynthesis,2000.2-7
[14] Saleh. R ,Wilton .S, Mirabbasi .S. System on Chip: Reuse and integration.ProceedingsoftheIEEE,2006.1050-1068
[15]韩泽耀、叶润涛.模拟/混合信号硬件描述语言VHDL—AMS综述.微电子学.2001,4.32(2).83-86
[16]贾政亚、张丽燕、黄云川.一种轨至轨输入的低压低功耗运放的设计.成都电子机械高等专科学校学报.2005,6.31(2).13-16
[17] Phillip E.Allen, Douglas R.Holberg著.冯军、李智群译.CMOS模拟集成电路设计.北京:电子工业出版,2005.149-224
[18]贾政亚.低压微功耗CMOS运算放大器的研究与设计.成都:电子科技大学硕士论文,2005.23-25
[19]黄云川.低压微功耗轨至轨输出CMOS运放研究设计.成都:电子科技大学硕士论文,2005.15-17
[20]徐跃、傅兴华.低电压模拟集成电路设计技术.微电子学.2004,8.34(4).451-454
[21] R.Jacob Baker, Harry W.Li, David E.Boyce. CMOS电路设计·布局与仿真.北京:机械工业出版社,2006.358-368
[22]曾宏、曾璇、闵昊.超深亚微米下百万门级系统级芯片的物理设计方案.复旦学报(自然科学版).2006,2.45(1).26-29
[23] Rafael Castro-López, O. Guerra, E. Roca, An Integrated Layout-SynthesisApproach for Analog ICs. IEEE Transactions on Computer-Aided Design ofIntegrated CircuitsandSystems,2008.1179-1189
[24] Alan Hastings著.张为等译.模拟电路版图的艺术.北京:电子工业出版社,2007.232-243
[25]金善子.模拟电路版图设计中的匹配艺术.中国集成电路.2006,12.91.48-51
[26] Chung-Chih Hung, ChangKu Hwang, HalonenK.Design ofCMOS Analog Cellsfor Low-Voltage VLSI. IEEE39th Midwest Symposium on Circuits and Systems,1996.15-18
[27] Chih-MinYu, Zhi-Ming Lin, Jun-Da Chen. A Low Voltage High Unity-GainBandwidth CMOS Op-Amp. The 2004 IEEE Asia-Pacific Conference on CircuitsandSystems,2004.45-48
[28] S V Gopalaiah ,AP Shivaprasad. LowVoltage CMOS Op-Amp with Rail-to-RailInput/Output Swing. Proceedings of the Second IEEE International Workshop onElectronicDesign,TestandApplications,2004.349-354
[29]尹韬、朱樟明、杨银堂.衬底驱动MOSFET特征分析和超低压运算放大器的设计.半导体学报,2005,1.26(1).158-162
[30]HuseyinDinc,SeanChuang, PhillipAllen.ARailtoRail, slew-BoostedPre-chargeBuffer.IEEEInternationalSymposiumonCircuitsandSystems,2006.65-68
[31] A.Masoom, Kh.Hadidi.A 1.5V Constant-Gm Rail to Rail Input Stage OperationalAmplifier. Proceedings of the IEEE international Conference on Electronics,CircuitsandSystems,2006.632-635
[32] Li Xian, Chang Changyuan, Lijuan. A Rail to Rail Op Amp for VLSI Cell withConstant Performance. European Conference on Circuit Theory and Design,2007.16-19
[33] Sarkar.S, Shinde.S , Chandar. S. An Effective IP Reuse Methodology for QualitySoC Design Proceedings of International Symposium on System on Chip,2005.104-107