摘要
随着各种手持嵌入式智能设备的广泛普及和应用,人们的生活质量得到了大幅度提升,但由此而引起的资源和环境问题也越来越严重。以低能耗、低污染为主要目标的绿色需求已经成为现代社会可持续发展的必然选择。
为降低嵌入式系统的能耗,提高嵌入式设备中各种资源的利用率,减少不必要的设备损耗,降低电子垃圾等有害物质的排放速度,一方面需要从材料的选取、设备的制造工艺等硬件部分进行改进,另一方面更需要对其上运行的软件进行相关优化,以充分发挥各种低能耗硬件设备的功效,适应不断增长的绿色需求。编译器作为软件开发和语言转换的工具,不但能够结合具体的嵌入式系统各部分硬件的特性进行针对性的优化,以指导生成的目标程序具有较高的绿色指标,而且能够利用其对源程序的分析结果,帮助程序员在程序开发过程中尽早的发现源程序中可能存在的能耗等绿色相关错误,提高软件的质量,减少其开发过程中因测试和调试而造成的资源和能源消耗。要系统化、自动化的对软件进行优化,必然离不开编译器的支持。
但传统编译优化技术主要以性能优化为主,较少的考虑能耗、资源等绿色相关因素的影响。而性能优化与绿色优化并不总是一致的。通常情况下,性能优化是以资源和能源的消耗为代价的(如使用较多的寄存器资源,提高处理器运行速率),因而不能仅仅依靠传统编译优化来满足绿色优化的需求。其次,传统编译辅助信息主要集中于对程序语言语法错误以及可能的空指针、数组越界等功能性错误的检测。而能耗错误等绿色相关错误并非功能性错误,传统编译器给出的信息对于检测这类错误,提高软件开发效率以及质量几乎无能为力。为弥补传统编译器在绿色优化中的不足,本文将对嵌入式系统的绿色需求进行分析,通过在编译的过程中对嵌入式系统中的软件进行针对性优化,减少其运行时的能耗,均衡设备中各种资源的使用,提高系统整体资源的利用度,以满足日益增长的绿色需求。主要研究内容和创新点包括以下四个方面:
1、结合了现有绿色需求的相关概念以及编译器本身的主要功能,给出了一种绿色编译器的定义,明确了该编译器优化的主要目标及其特点。同时,在该定义的指导下,对编译器指导的总体绿色评估模型进行了形式化描述,以有效的指导和评估绿色编译优化的顺利进行。
2、为充分发挥时序推测处理器的低能耗特性,减少其因为流水线的数据向前推送机制而导致的时序错误,降低因此而消耗的无效能源,对形式化的绿色评估模型进行了具体化,构建了以数据依赖为主要指标的时序推测处理器的绿色评估指标,并在此基础上提出了一种基于图博弈模型的指令调度算法。通过提高数据之间“写后读”依赖的时钟周期,减少因此而产生的数据向前推送操作,获得时序推测处理器绿色指标的大幅度提升。此外,针对带有总线翻转编码的总线系统,分析了绿色评估模型中总线相关的绿色评估指标,并以此为标准,设计了一种反馈信息指导的绿色指令调度算法。利用程序执行的动态反馈信息,结合总线翻转编码的特点,充分减少相邻总线之间的翻转次数,均衡各根总线之间的翻转负载,以提高该系统的绿色指标。
3、不同的数据分配方案对存储资源的使用、系统总的能源消耗等绿色相关指标将产生重要影响。为进一步提高系统的绿色指标,针对存储器层次存储单元的特点,分析了绿色评估模型中影响存储系统绿色指标的相关因子,设计了可交换类指令重排优化方法、基于扩展图着色的寄存器重分配优化方法和栈数据重分配方法,对编译器后端的寄存器以及栈数据进行重新调整,以获得较均衡的寄存器访问频度和栈存储单元访问频度,减少指令数据总线的动态翻转能耗。同时,为进一步提升系统的绿色指标,在前两种优化的基础上增加了迭代式优化,通过迭代优化使得寄存器使用更加均衡,相邻指令间的动态能耗更小。
4、为提高软件开发的质量,减少能耗错误导致的无用能源损耗,总结了能耗相关错误的相关特征,并以该特征为基础,结合符号执行技术,设计了能耗错误检测和定位方法。该方法首先利用过程内分析,获得单个函数的符号执行信息,然后利用过程间分析对单个函数的符号执行信息进行全局分析,以获得较为准确的执行开销、锁变量匹配等相关信息,检测出对应的能耗相关错误。同时,符号执行记录了对应的分支路径信息,利用该信息不但能够较好的生成对应的测试用例,而且可以结合约束求解器快速定位错误位置,为开发出高绿色指标的软件提供保障。
As the widely popularization and application of portable smart embedded devices, the quality of people's life has been greatly improved. However, it makes the problems of resources and environments get worse. The green demands with the target of low energy and low pollution has become the inevitable choice for sustainable development of modern society.
To reduce the energy consumption of embedded systems, improve the utilization of various resources, and reduce unnecessary equipment wear and tear for reducing e-waste and other harmful substances emission rates, on the one hand, we need to improve the materials and manufacturing of hardware devices. On the other hand, suitable software optimizations are also needed to maximize the effectiveness of various low-power hardware devices to meet the growing demand for green. As the software development and language translation tools, compiler can not only apply the suitable optimizations to guide the generated program has a high green indeicators by combining the specific embedded system hardware characteristics, but also help the programmer find the green-related errors such as energy bug as early as possible by using the analysis results form the program translation. It can improve the software quality and reduce resource and energy consumption by testing and debugging. To optimize the software systemically and automatically, compiler is one of best selection.
However, tranditional compilers mainly focus on the performance of software and fewer consider the green factors such as energy and utilization of resource. Performance optimization and green optimization are not always the same. Performance optimization often needs to sacrifice the green targets that need more registers and higher processor's voltage to increase the running speed. We cannot simply apply the traditional optimization methods to get the green factors improved. Secondly, the traditional auxiliary information supplied by compiler mainly concentrated on programming language syntax errors and other security related information such as null pointer, array bounds and other functional errors. The green related errors such as energy bug are often, not functional errors, the information given in the traditional compiler is useless for the detection of such errors, so the new detecting methods needed to further studied. To compensate for the drawback of traditional compiler in green optimization, the paper analyzes the green demands of embedded systems and optimizes the software in compiling processes to meet the growing demand for green such as getting low energy consumption, balancing the utilization of varied resources to increase the resources utilizations. The mainly contents and innovations are as follows.
1. Combining with green related conception and the functional of compiler itself, it gives the definition of green compiler and illustrate the mainly objection of optimizations and features. Then, the formal green evaluation model is described according to the definition to effectively guide the green compilation optimization.
2. To maximize the energy efficiency of timing speculative processor, reduce the timing errors caused by forwarding, a data dependency based green evaluation factor is constructed and a game model based instruction scheduling method is proposed. It formalizes the instruction scheduling to strategies selection in game model and increases the clock cycle of read-after-write dependency that can reduce the forwarding to improve the power efficiency of timing speculative processor. And for bus system by bus-invert coding, the invert information based green evaluation model is constructed and a feedback guided instruction scheduling method is proposed. It combines the characteristical of bus-invert coding and dynamic feedback profiling information to reduce the frequency of buses and also balance the inverts between buses which can improve the green indicator significantly.
3. Different data assignment strategies significantly influence the utilization of storage resourses and also total energy. In order to further improve the green indicator of the system, memory hierarchy characteristics and green related factors of memory are analyzed. Based on the green evaluation model, the exchangeable class instruction reordering optimization method, extended graph coloring register reallocation optimization method and stack data reallocation method are designed to reorder the memory cells and registers in the backend of compiler. It can obtain a more balanced access frequency to registers and stack memory cell, reduce the dynamic power of instruction data bus invert. Meanwhile, to further improve green indicators of the system, the iterative optimization on the first two optimization method is applied which makes the utilization of registers get more balanced and dynamic energy get lower.
4. In order to improve the green quality of software, reduce the energy consumption caused energy bug, the paper concludes the characteristics of energy bugs, and designs the energy bug detection and location methods combined with the symbolic execution technology. It firstly analyzes one single function to get its symbolic execution information. And then based on the single function symbol information, the interprocedural analysis is processed to obtain the global accurate execution overhead, lock variable matching and other related information to detect the corresponding energy bugs. Meanwhile, the symbolic execution records corresponding branch path information. It can not only be used to generate the corresponding test cases, and also to locate the position of errors combined with constraint solver which helps to develop the high green indicator software.
引文
[1]王艳.源码未知类软件能耗评估技术研究[D].中国科学院研究生院(长春光学精密机械与物理研究所),2012.
[2]Murugesan S. Harnessing green IT:Principles and practices[J]. IT professional.2008,10(1): 24-33.
[3]Capra E, Formenti G, Francalanci C, et al. The impact of MIS software on IT energy consumption[J].2010.
[4]McKinsey, http://icfre.gov.in/For%20FT%20IFC%20paper/subtheme5.1/green%20comp%20VIV EK%20IFGTB-CBE%2022-11-11.pdf,2012
[5]UNEP, http://www.unep.org/Documents.Multilingual/Default.asp?DocumentID=612&ArticleI D=6471,2010
[6]Fuji Chimera Research Institute, http://www.fcr.co.jp/en/,2012.
[7]过敏意.绿色计算:内涵及趋势[J].计算机工程.2010,36(010):1-7.
[8]SAMSUNG,http://www.samsung.com/global/business/semiconductor/minisite/Greenmmor y/main.htmh,2013
[9]NOKIA,http://www.nokia.com/global/about-nokia/people-and-planet/impact/environmental-and-social-impact/,2013
[10]SONY, http://www.sony.net/SonyInfo/procurementinfo/green.html,2013
[11]Hong S, Narayanan U, Chung K S, et al. Bus-invert coding for low-power I/O-a decomposition approach[C].//Midwest Symposium on Circuits and Systems:Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems. Lansing, MI, United States, Aug 8-11,2000. NJ:IEEE,2000:750-753.
[12]Benini L, De Micheli G, Macii E. Designing low-power circuits:practical recipes[J]. Circuits and Systems Magazine, IEEE.2001,1(1):6-25.
[13]Raghunathan A, Jha N K, Dey S. High-level power analysis and optimization[M]. Kluwer Academic,1998.
[14]Stan M R, Burleson W P. Bus-invert coding for low-power I/O[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems.1995,3(1):49-58.
[15]Lv T, Henkel J, Lekatsas H, et al. A dictionary-based en/decoding scheme for low-power data buses[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems.2003, 11(5):943-951.
[16]Suresh D C, Agrawal B, Yang J, et al. Tunable and energy efficient bus encoding techniques[J]. IEEE Transactions on Computers.2009,58(8):1049-1062.
[17]Benini L, De Micheli G, Macii E, et al. Asymptotic zero-transition activity encoding for address busses in low-power microprocessor-based systems[C].//Proceedings of the IEEE Great Lakes Symposium on VLSI:Proceedings of the 1997 7th Great Lakes Symposium on VLSI. Urbana-Champaign, IL, USA. Mar 13-15,1997. Los Alamitos:IEEE,1997:77-82.
[18]Mehta H, Owens R M, Irwin M J. Some issues in gray code addressing[C]. Proceedings of the IEEE Great Lakes Symposium on VLSI:Proceedings of the 1996 6th Great Lakes Symposium on VLSI. Ames, IA, USA. Mar 22-23,1996. Los Alamitos:IEEE,1996: 178-181.
[19]Guo H, Parameswaran S. Shifted gray encoding to reduce instruction memory address bus switching for low-power embedded systems[J]. Journal of Systems Architecture.2010,56(4): 180-190.
[20]Parikh A, Kim S, Kandemir M, et al. Instruction scheduling for low power[J]. The Journal of VLSI Signal Processing.2004,37(1):129-149.
[21]Lee C, Lee J K, Hwang T, et al. Compiler optimization on VLIW instruction scheduling for low power[J]. ACM Transactions on Design Automation of Electronic Systems (TODAES). 2003,8(2):252-268.
[22]Shao Z, Zhuge Q, Zhang Y, et al. Efficient scheduling for low-power high-performance DSP applications[J]. International Journal of High Performance Computing and Networking IJHCN.2004,1:3-16.
[23]Chabini N, Wolf M C. Reordering the assembly instructions in basic blocks to reduce switching activities on the instruction bus[J]. Computers & Digital Techniques, IET.2011, 5(5):386-392.
[24]Duan C, Calle V H C, Khatri S P. Efficient on-chip crosstalk avoidance codec design[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems.2009,17(4):551-560.
[25]Moll F, Roca M, Isern E. Analysis of dissipation energy of switching digital cmos gates with coupled outputs[J]. Microelectronics journal.2003,34(9):833-842.
[26]Guihai Y, Yinhe H, Xiaowei L I, et al. BAT:Performance-Driven Crosstalk Mitigation Based on Bus-Grouping Asynchronous Transmission[J]. IEICE transactions on electronics. 2008,91(10):1690-1697.
[27]Sotiriadis P P, Chandrakasan A. Bus energy minimization by transition pattern coding (TPC) in deep sub-micron technologies[C].//IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers:IEEE/ACM International Conference on Computer Aided Design (ICCAD). San Jose, CA, USA,2000. Los Alamitos:IEEE,2000: 322-328.
[28]Wu X, Yan Z. Efficient CODEC designs for crosstalk avoidance codes based on numeral systems[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems.2011,19(4): 548-558.
[29]Zhang J, Friedman E G. Effect of shield insertion on reducing crosstalk noise between coupled interconnects[C].//IEEE International Symposium on Circuits and Systems: Proceedings of the 2004 International Symposium on Circuits and Systems (ISCAS). Vancouver, BC, Canada, May 23-26,2004. Canada:IEEE,2004:Ⅱ529-Ⅱ532.
[30]Mutyam M. Selective shielding technique to eliminate crosstalk transitions[J]. ACM Transactions on Design Automation of Electronic Systems (TODAES).2009,14(3):43.
[31]Gupta U, Ranganathan N. A Utilitarian Approach to Variation Aware Delay, Power, and Crosstalk Noise Optimization[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems.2011,19(9):1723-1726.
[32]Hanchate N, Ranganathan N. Simultaneous interconnect delay and crosstalk noise optimization through gate sizing using game theory[J]. IEEE Transactions on Computers. 2006,55(8):1011-1023.
[33]Macii E, Poncino M, Salerno S. Combining wire swapping and spacing for low-power deep-submicron buses[C].//Proceedings of the IEEE Great Lakes Symposium on VLSI: Proceedings of the 2003 ACM Great Lakes Symposium on VLSI. Washington, DC, USA, Apr 28-29,2003. Washington:IEEE,2003:198-202.
[34]Weng T H, Lin C H, Shann J J J, et al. Power reduction by register relabeling for crosstalk-toggling free instruction bus coding[C].//International Computer Symposium: 2010 International conference on Computer Symposium (ICS). Tainan, Dec 16-18. NJ:IEEE Computer Society,2010:676-681.
[35]Kuo W A, Chiang Y L, Hwang T T, et al. Performance-driven crosstalk elimination at post-compiler level[C].//Proceedings-IEEE International Symposium on Circuits and Systems:2006 IEEE International Symposium on Circuits and Systems (ISCAS). Kos, Greece, May 21-24,2006. NJ:IEEE,2006:3041-3044.
[36]Dhiman G, Ayoub R, Rosing T. PDRAM:A hybrid PRAM and DRAM main memory system[C].//Proceedings-Design Automation Conference:46th ACM/IEEE on Design Automation Conference, San Francisco, July 26-31,2009. NJ:IEEE,2009:664-669.
[37]Ferreira A P, Zhou M, Bock S, et al. Increasing pcm main memory lifetime[C].// Proceedings -Design, Automation and Test in Europe:Design, Automation and Test in Europe Conference and Exhibition, DATE 2010. Dresden, Germany, Mar 8-12,2010. NJ: IEEE,2010:914-919.
[38]Liu D, Wang T, Wang Y, et al. PCM-FTL:a write-activity-aware NAND flash memory management scheme for PCM-based embedded systems[C].//Proceedings-Real-Time Systems Symposium:2011 IEEE 32nd Real-Time Systems Symposium (RTSS). Vienna, Austria, Nov 29-Dec 2,2011. NJ:IEEE,2011:357-366.
[39]Qureshi M K, Karidis J, Franceschini M, et al. Enhancing lifetime and security of pcm-based main memory with start-gap wear leveling[C].//Proceedings of the Annual International Symposium on Microarchitecture:42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO). New York, NY, United states, Dec 12-16,2009. NJ:IEEE Computer Society,2009:14-23.
[40]Qureshi M K, Srinivasan V, Rivers J A. Scalable high performance main memory system using phase-change memory technology[C].//Proceedings-International Symposium on Computer Architecture:36th Annual International Symposium on Computer Architecture (ISCA). Austin, TX, United states, Jun 20-24,2009. New York:IEEE,2009:24-33.
[41]Xu W, Liu J, Zhang T. Data manipulation techniques to reduce phase change memory write energy[C].//Proceedings of the International Symposium on Low Power Electronics and Design:Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design (ISLPED). San Fancisco, CA, United states, Aug 19-21,2009. NJ: IEEE,2009:237-242.
[42]Zhou P, Zhao B, Yang J, et al. A durable and energy efficient main memory using phase change memory technology[J]. ACM SIGARCH-Computer Architecture News.2009,37(3): 14.
[43]Zhou X, Yu C, Petrov P. Compiler-driven register re-assignment for register file power-density and temperature reduction[C].//Proceedings-Design Automation Conference:Proceedings of the 45th annual Design Automation Conference (DAC). Anaheim, CA, United states, Jun 8-13,2008. NJ:IEEE,2008:750-753.
[44]Yang C, Orailoglu A. Processor reliability enhancement through compiler-directed register file peak temperature reduction[C]. Proceedings of the International Conference on Dependable Systems and Networks:IEEE/IFIP International Conference on Dependable Systems & Networks (DSN). Lisbon, Portugal, Jun 29-July 2,2009. NJ:IEEE Computer Society,2009:468-477.
[45]Liu T, Orailoglu A, Xue C J, et al. Register allocation for simultaneous reduction of energy and peak temperature on registers[C].//Proceedings -Design, Automation and Test in Europe:Design, Automation & Test in Europe Conference & Exhibition (DATE). Grenoble, France, Mar 14-18,2011. NJ:IEEE,2011:1-6.
[46]Li H, Chen Y. An overview of non-volatile memory technology and the implication for tools and architectures[C].//Proceedings -Design, Automation and Test in Europe:Design, Automation & Test in Europe Conference & Exhibition (DATE). Nice, France, Apr 20-24, 2009. NJ:IEEE,2009:731-736.
[47]Hu J, Xue C J, Tseng W C, et al. Minimizing write activities to non-volatile memory via scheduling and recomputation[C].//Proceedings of the 2010 IEEE 8th Symposium on Application Specific Processors:2010 IEEE 8th Symposium on Application Specific Processors (SASP). Anaheim, CA, United states, Jun 13-14,2010. NJ:IEEE Computer Society,2010:101-106.
[48]Hu J, Xue C J, Tseng W C, et al. Reducing write activities on non-volatile memories in embedded CMPs via data migration and recomputation[C].//Proceedings-Design Automation Conference:2010 47th ACM/IEEE on Design Automation Conference (DAC). Anaheim, CA, United states, Jun 13-18,2010. NJ:IEEE,2010:350-355.
[49]Huang Y, Liu T, Xue C J. Register allocation for write activity minimization on non-volatile main memory for embedded systems[J]. Journal of Systems Architecture.2011.
[50]Li Q, Li J, Shi L, et al. Compiler-Assisted Refresh Minimization for Volatile STT-RAM Cache[Z]. Yokohama, Japan:2013273-278.
[51]Li Q, Zhao M, Xue C J, et al. Compiler-assisted preferred caching for embedded systems with STT-RAM based hybrid cache[C].//Proceedings of the ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems:Proceedings of the 13th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, Tools and Theory for Embedded Systems. Beijing, China, Jun 12-13,2012. NY:Association for Computing Machinery,2012:109-118.
[52]Li Q, Li J, Shi L, et al. Mac:Migration-aware compilation for stt-ram based hybrid cache in embedded systems[C].//Proceedings of the International Symposium on Low Power Electronics and Design:Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design. Redondo Beach, CA, United states, Jul 30- Aug 1,2012. NJ:IEEE,2012:351-356.
[53]Chen Y T, Cong J, Huang H, et al. Static and dynamic co-optimizations for blocks mapping in hybrid caches[C].//Proceedings of the International Symposium on Low Power Electronics and Design:Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design. Redondo Beach, CA, United States, Jul 30-Aug 1,2012. NJ:IEEE,2012:237-242.
[54]Yang Y, Wang M, Yan H, et al. Dynamic scratch-pad memory management with data pipelining for embedded systems[J]. Concurrency and Computation:Practice and Experience. 2010,22(13):1874-1892.
[55]Cho D, Pasricha S, Issenin I, et al. Adaptive scratch pad memory management for dynamic behavior of multimedia applications[J]. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on.2009,28(4):554-567.
[56]Kannan A, Shrivastava A, Pabalkar A, et al. A software solution for dynamic stack management on scratch pad memory[C].//Proceedings of the Asia and South Pacific Design Automation Conference:Proceedings of the 2009 Asia and South Pacific Design Automation Conference. Yokohama, Japan, Jan 19-22,2009. NJ:IEEE,2009:612-617.
[57]Li L, Xue J, Knoop J. Scratchpad memory allocation for data aggregates via interval coloring in superperfect graphs[J]. ACM Transactions on Embedded Computing Systems (TECS). 2010,10(2):28.
[58]Li L, Wu H, Feng H, et al. Towards data tiling for whole programs in scratchpad memory allocation[J]. Advances in Computer Systems Architecture.2007:63-74.
[59]Yang X, Wang L, Xue J, et al. Improving scratchpad allocation with demand-driven data tiling[C].//Embedded Systems Week 2010:Proceedings of the 2010 international conference on Compilers, architectures and synthesis for embedded systems. Scottsdale, AZ, United states, Oct 24-29,2010. New York:Association for Computing Machinery,2010: 127-136.
[60]Hu W, Chen T, Shi Q, et al. Efficient utilization of scratch-pad memory for embedded systems[C].//7th Annual IEEE International Conference on Pervasive Computing and Communications:IEEE International Conference on Pervasive Computing and Communications (PerCom 2009). Galveston, TX, United states, Mar 9-13,2009. NJ:IEEE Computer Society,2009:1-6.
[61]Hu J, Xue C J, Zhuge Q, et al. Towards energy efficient hybrid on-chip scratch pad memory with non-volatile memory[C].//Proceedings -Design, Automation and Test in Europe: Design, Automation & Test in Europe Conference & Exhibition (DATE). Grenoble, France, Mar 14-18,2011.NJ:IEEE,2011:1-6.
[62]Takase H, Tomiyama H, Takada H. Partitioning and allocation of scratch-pad memory for priority-based preemptive multi-task systems[C].//Proceedings -Design, Automation and Test in Europe:Design, Automation & Test in Europe Conference & Exhibition (DATE). Dresden, Germany, Mar 8-12,2010. NJ:IEEE,2010:1124-1129.
[63]Gauthier L, Ishihara T, Takase H, et al. Placing Static and Stack Data into a Scratch-Pad Memory for Reducing the Energy Consumption of Multi-task Applications[C].//Workshop on Synthesis And System Integration of Mixed Information technologies:The 16th Workshop on Synthesis And System Integration of Mixed Information technologies, Taipei, Taiwan, Oct 18-19,2010. Japan:SASIMI Workshop,2010:7-12
[64]Ozturk O, Kandemir M, Son S W, et al. Shared scratch pad memory space management across applications[J]. International Journal of Embedded Systems.2009,4(1):54-65.
[65]Bathen L A, Dutt N. HaVOC:A hybrid memory-aware virtualization layer for on-chip distributed Scratchpad and Non-Volatile Memories[C].//Proceedings-Design Automation Conference:2012 49th ACM/EDAC/IEEE Design Automation Conference (DAC). San Francisco, CA, United states, Jun 3-7,2012. NJ:IEEE,2012:447-452.
[66]汪黎.大容量软件管理片上存储器分配技术综述[J].计算机工程与科学.2009,31(z1):138-142.
[67]罗飞,过敏意,陈英.MPSoc上动静态结合的SPM分配策略[J]. Computer Engineering.2010,36(21).
[68]·胡志刚,石金锋,蒋湘涛.针对能耗热点的SPM静态分配管理策略[J].计算机工程与应用.2010,46(3):58-75.
[69]Yong C, Yanxiang H, Ximi L, et al. Dynamic probability based instruction scheduling for low-power embedded system[C].//ICCASM 2010:2010 International Conference on Computer Application and System Modeling (ICCASM). Shanxi, Taiyuan, China, Oct 22-24, 2010. NJ:IEEE Computer Society,2010:V215-V219.
[70]Duggirala P S, Mitra S, Kumar R, et al. On the theory of Stochastic processors[C].// Proceedings-7th International Conference on the Quantitative Evaluation of Systems, QEST 2010. Williamsburg, VA, United states, Sep 15-18,2010. NY:Association for Computing Machinery,292-301.
[71]Narayanan S, Sartori J, Kumar R, et al. Scalable stochastic processors[C].//Proceedings-Design, Automation and Test in Europe:Proceedings of the Conference on Design, Automation and Test in Europe. Dresden, Germany, Mar 8-12,2010. NJ:IEEE,2010: 335-338.
[72]Shanbhag N R, Abdallah R A, Kumar R, et al. Stochastic computation[C].//Proceedings-Design Automation Conference:2010 47th ACM/IEEE Design Automation Conference (DAC). Anaheim, CA, United states, Jun 13-18,2010. NJ:IEEE,2010:859-864.
[73]Sloan J, Sartori J, Kumar R. On software design for stochastic processors[C].// Proceedings-Design Automation Conference:Proceedings of the 49th Annual Design Automation Conference, San Francisco, CA, United states, Jun 3-7,2012. NJ:IEEE,2012: 918-923.
[74]Carbin M, Kim D, Misailovic S, et al. Proving acceptability properties of relaxed nondeterministic approximate programs [C].//Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation:33rd ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI 2012). Beijing, China, Jun 11-16,2012. NY:Association for Computing Machinery,2012:169-180.
[75]Ernst D, Kim N S, Das S, et al. Razor:A low-power pipeline based on circuit-level timing speculation[C].//19th Symposium on Integrated Circuits and Systems Design:Proceedings of 36th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-36). Minas Gerais, Brazil, Aug 28-Sep 1,2003. NY:Association for Computing Machinery,2003: 7-18.
[76]Greskamp B, Torrellas J. Paceline:Improving single-thread performance in nanoscale CMPs through core overclocking[C].//Parallel Architectures and Compilation Techniques:16th International Conference on Parallel Architecture and Compilation Techniques (PACT). Brasov, Romania, Sep 15-19,2007. NJ:IEEE,2007:213-224.
[77]Greskamp B, Wan L, Karpuzcu U R, et al. Blueshift:Designing processors for timing speculation from the ground up.[C].//Proceedings-International Symposium on High-Performance Computer Architecture:2009 IEEE 15th International Symposium on High Performance Computer Architecture (HPCA). Takamatsu, Japan, Aug 5-8,2009. NJ: IEEE,2009:213-224.
[78]Kahng A B, Kang S, Kumar R, et al. Designing a processor from the ground up to allow voltage/reliability tradeoffs[C].//Proceedings-International Symposium on High-Performance Computer Architecture:2010 IEEE 16th International Symposium on High Performance Computer Architecture (HPCA). Bangalore, India, Jan 9-14,2010. NJ: IEEE Computer Society,2010:1-11.
[79]Xin J, Joseph R. ldentifying and predicting timing-critical instructions to boost timing speculation[C].//Proceedings of the Annual International Symposium on Microarchitecture: Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture. Porto Alegre, RS, Brazil, Dec 4-7,2011. NJ:IEEE Computer Society,2011:128-139.
[80]Hoang G, Findler R B, Joseph R. Exploring circuit timing-aware language and compilation[J]. ACM SIGPLAN Notices.2011,46(3):345-356.
[81]Sartori J, Kumar R. Compiling for energy efficiency on timing speculative processors[C].// Proceedings Design Automation Conference:49th Annual Design Automation Conference (DAC). San Francisco, CA, United states, Jun 3-7,2012. NJ:IEEE,2012:1297-1304.
[82]Myers G J, Sandier C, Badgett T. The art of software testing[M]. Wiley,2011.
[83]Godefroid, P, Klarlund, N, Sen P. DART:directed automated random testing[C].// Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation:2005 ACM SIGPLAN Conference on Programming Language Design and Implementation. Chicago, IL, United states, Jun 12-15,2005. NY:Association for Computing Machinery,2005:213-223.
[84]Hong H S, Cha S D, Lee I, et al. Data flow testing as model checking[C]. Proceedings-International Conference on Software Engineering:Proceedings of 25th International Conference on Software Engineering. Portland, OR, United states, May 3-10,2003. NJ: IEEE,2003:232-242.
[85]Alshraideh M, Mahafzah B A, Al-Sharaeh S. A multiple-population genetic algorithm for branch coverage test data generation[J]. Software Quality Journal.2011,19(3):489-513.
[86]Andrews J H, Menzies T, Li F C H. Genetic algorithms for randomized unit testing[J]. IEEE Transactions on Software Engineering,2011,37(1):80-94.
[87]薛云志,陈伟,王永吉,等.一种基于Messy GA的结构测试数据自动生成方法[J].软件学报.2006,17(8):1688-1697.
[88]Nayak N, Mohapatra D P. Automatic test data generation for data flow testing using particle swarm optimization[J]. Contemporary Computing.2010:1-12.
[89]Tung Y H, Tseng S S, Lee T J, et al. A novel approach to automatic test case generation for web applications[C].//Proceedings-International Conference on Quality Software:2010 10th International Conference on Quality Software (QSIC). Zhangjiajie, China, Jul 14-15, 2010. NJ:IEEE Computer Society,2010:399-404.
[90]Traver V J. On compiler error messages:what they say and what they mean[J]. Advances in Human-Computer Interaction.2010,2010.
[91]Jeffery C L. Generating LR syntax error messages from examples[J]. ACM Transactions on Programming Languages and Systems (TOPLAS).2003,25(5):631-640.
[92]何炎祥,陈勇,吴伟,等.基于编译支持错误跟踪的测试用例自动化生成方法[J].计算机研究与发展.2012,49(9):1843-1851.
[93]Pathak A, Hu Y C, Zhang M. Bootstrapping energy debugging on smartphones:a first look at energy bugs in mobile devices[C].//Proceedings of the 10th ACM Workshop on Hot Topics in Networks:Proceedings of the 10th ACM Workshop on Hot Topics in Networks. Cambridge, MA, United states, Nov 14-15,2011. Spain:Adalia Farma,2011:5.
[94]Pathak A, Jindal A, Hu Y C, et al. What is keeping my phone awake?:characterizing and detecting no-sleep energy bugs in smartphone apps[C].//Proceedings of the 10th International Conference on Mobile Systems, Applications, and Services:Proceedings of the 10th international conference on Mobile systems, applications, and services, Low Wood Bay, Lake District, United kingdom, Jun 25-29,2012. NY:Association for Computing Machinery, 2012:267-280.
[95]P Vekris, R Jhala, S Lerner et al. Towards Verifying Android Apps for the Absence of No-Sleep Energy Bugs. Proceedings of the 2012 USENIX conference on Power-Aware Computing and Systems.2012.3-8.
[96]AJ Oliner, A Iyer, E Lagerspet et al. Collaborative energy debugging for mobile devices. Proceedings of the Eighth USENIX conference on Hot Topics in System Dependability.2012. 6-10
[97]Zhu R, Sun Z, Hu J. Editorial:Special section:Green computing[J]. Future Generation Computer Systems.2012,28(2):368-370.
[98]郭兵,沈艳,邵子立.绿色计算的重定义与若干探讨[J].计算机学报.2009(012):2311-2319.
[99]林闯,田源,姚敏.绿色网络和绿色评价:节能机制,模型和评价[J].计算机学报.2011,34(4):593-612.
[100]马科.绿色存储技术[J].现代电信科技,2009:8,5-9.
[101]孟庆余.绿色IT与绿色操作系统[J].微型机与应用.2009,28(8):1-4.
[102]Tseng C K, Huang S Y, Weng C C, et al. Black-box leakage power modeling for cell library and SRAM compiler[C]//Design, Automation & Test in Europe Conference & Exhibition (DATE),2011. IEEE,2011:1-6.
[103]More S, Fulde M, Chouard F, et al. Reducing impact of degradation on analog circuits by chopper stabilization and autozeroing[C]//Quality Electronic Design (ISQED),2011 12th International Symposium on. IEEE,2011:1-6.
[104]Kearns M, Littman M L, Singh S. Graphical models for game theory[C]//Proceedings of the Seventeenth conference on Uncertainty in artificial intelligence. Morgan Kaufmann Publishers Inc.,2001:253-260.
[105]Schwartz E J, Avgerinos T, Brumley D. All you ever wanted to know about dynamic taint analysis and forward symbolic execution (but might have been afraid to ask)[C].//2010 IEEE Symposium on Security and Privacy, Oakland, California:IEEE,2010:317-331.
[106]Anand S, Pasareanu C S, Visser W. JPF-SE:A symbolic execution extension to java pathfinder[M]//Tools and Algorithms for the Construction and Analysis of Systems. Springer Berlin Heidelberg,2007:134-138.
[107]Cadar C, Dunbar D, Engler D R. KLEE:Unassisted and Automatic Generation of High-Coverage Tests for Complex Systems Programs[C]//OSDI.2008,8:209-224.
[108]Cadar C, Ganesh V, Pawlowski P M, et al. EXE:automatically generating inputs of death[J]. ACM Transactions on Information and System Security (TISSEC),2008,12(2):10.
[109]Sen K, Marinov D, Agha G. CUTE:a concolic unit testing engine for C[M]. ACM, 2005.
[110]陆伯鹰,尹宝林.一个基于DAG图的指令调度优化算法[J].计算机工程与应用,2001,12:027.
[111]Aho A V. Compilers:principles, techniques,& tools[M]. Pearson Education India, 2007.