基于DVS的节能编译技术研究
摘要
近年来，随着半导体和芯片技术的快速发展，集成了越来越多的硬件、软件和应用程序的系统级芯片变得越来越重要。随之而来的，是可移动嵌入式设备，如手机(Cell-Phone)，个人掌上电脑(PDA)等设备的性能大幅度地提升，带来对电池的需求不断呈上升趋势。电池的容量与使用时间已经是制约便携嵌入式设备发展的一个重要问题。使用合理的硬件和软件的办法，降低应用程序和系统的功耗，成为嵌入式系统设计的一个重要课题。
当前的节能的方面的研究，在操作系统调度方面取得了很多的成果。通过操作系统调度和硬件结合的办法，通常是对历史记录进行判断，准确度成为一个问题。本文认为通过编译器和硬件技术相结合，可以获得更准确的调度信息。
本文结合硬件上的动态电压缩放技术(Dynamic Voltage Scaling，DVS)和编译技术，提出了基于DVS的节能编译框架，利用编译器对代码的了解和修改能力，采用时间与功耗判断的算法，为不同的代码段设定不同的电压，从而达到节能的目的。本框架分为静态编译和动态编译两种，通过静态节能编译框架验证编译器和DVS技术结合的有效，通过动态节能编译框架，考虑到系统运行过程中多程序并行的实际情况，以及系统的电压限制和性能要求，让节能框架更加准确和实用。
通过在SimpleScalar软件模拟平台和Intel XScale硬件平台上分别了实现静态和动态节能编译软件。能耗测试结果表明，静态节能编译器在代码性能下降5％的可允许范围以内，能够获得最高37％的功耗节省；动态节能编译器在实验平台上上可得到最高28％平均23％的功耗节省。
本文提出的基于DVS的节能编译框架，经验证确实可以达到平均23％的节能效果，并保持性能不下降。
With the fast development of semiconductor and the fast growth of capacity of chips, more and more new technique is available on the embedded systems, especially the mobile embedded systems. The result of fast development of the application on the embedded system is that the battery of become the limitation of the system. The life and capacity of the battery is now a big problem for the reason that these applications consume more and more energy. As the development of Chemistry is on the bottle neck, to reduce the energy consumption by software and hardware become the main issue of design of embedded system.
Lots of research on reducing energy in the embedded systems has been done. Most of these research focuses on scheduling of tasks in the OS level. Due to the limitation of OS, the schedule is not accurate for the reason that the basis of the schedule is the trace of the tasks in the OS, without inner information from the instructions of the tasks. To schedule the tasks more accurately than OS level, there is some research on the compiler and DVS.
In this paper we present a compiler framework to reduce the energy consumption on embedded systems. Firstly the Dynamic Voltage Scaling (DVS) technology was applied on the static compiler and then it was integrated in the dynamic compiler. The Framework of Runtime Dynamic Compiler based DVS (RDCD) contains 3 steps, firstly it selects the candidate block which may suitable for DVS and then the runtime judging algorithm select the suitable blocks, finally the RDCD insert the DVS instruction at the beginning and end of these blocks.
The framework is realized in a simulator and a real-system. Simulation results on the simple scalar with a new energy testing module show that CPU energy can save to 13%-15% for the Intel Xscale PXA270 benchmark with a time performance penalty of at most 5%. And the result from the real system shows that the dynamic compiler with DVS can save at most 23%.
当前的节能的方面的研究，在操作系统调度方面取得了很多的成果。通过操作系统调度和硬件结合的办法，通常是对历史记录进行判断，准确度成为一个问题。本文认为通过编译器和硬件技术相结合，可以获得更准确的调度信息。
本文结合硬件上的动态电压缩放技术(Dynamic Voltage Scaling，DVS)和编译技术，提出了基于DVS的节能编译框架，利用编译器对代码的了解和修改能力，采用时间与功耗判断的算法，为不同的代码段设定不同的电压，从而达到节能的目的。本框架分为静态编译和动态编译两种，通过静态节能编译框架验证编译器和DVS技术结合的有效，通过动态节能编译框架，考虑到系统运行过程中多程序并行的实际情况，以及系统的电压限制和性能要求，让节能框架更加准确和实用。
通过在SimpleScalar软件模拟平台和Intel XScale硬件平台上分别了实现静态和动态节能编译软件。能耗测试结果表明，静态节能编译器在代码性能下降5％的可允许范围以内，能够获得最高37％的功耗节省；动态节能编译器在实验平台上上可得到最高28％平均23％的功耗节省。
本文提出的基于DVS的节能编译框架，经验证确实可以达到平均23％的节能效果，并保持性能不下降。
With the fast development of semiconductor and the fast growth of capacity of chips, more and more new technique is available on the embedded systems, especially the mobile embedded systems. The result of fast development of the application on the embedded system is that the battery of become the limitation of the system. The life and capacity of the battery is now a big problem for the reason that these applications consume more and more energy. As the development of Chemistry is on the bottle neck, to reduce the energy consumption by software and hardware become the main issue of design of embedded system.
Lots of research on reducing energy in the embedded systems has been done. Most of these research focuses on scheduling of tasks in the OS level. Due to the limitation of OS, the schedule is not accurate for the reason that the basis of the schedule is the trace of the tasks in the OS, without inner information from the instructions of the tasks. To schedule the tasks more accurately than OS level, there is some research on the compiler and DVS.
In this paper we present a compiler framework to reduce the energy consumption on embedded systems. Firstly the Dynamic Voltage Scaling (DVS) technology was applied on the static compiler and then it was integrated in the dynamic compiler. The Framework of Runtime Dynamic Compiler based DVS (RDCD) contains 3 steps, firstly it selects the candidate block which may suitable for DVS and then the runtime judging algorithm select the suitable blocks, finally the RDCD insert the DVS instruction at the beginning and end of these blocks.
The framework is realized in a simulator and a real-system. Simulation results on the simple scalar with a new energy testing module show that CPU energy can save to 13%-15% for the Intel Xscale PXA270 benchmark with a time performance penalty of at most 5%. And the result from the real system shows that the dynamic compiler with DVS can save at most 23%.
引文
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[2] Stemm M, Katz RH. Measuring and reducing energy consumption of networ k interfaces in hand-held devices. IEEE Trans, on Communications, 1997,E80-B (8):1125-1131
[3] Ravindra Jejurikar, Rajesh Gupta. Dynamic Voltage Scaling for System wide Energy Minimization in Real-Time Embedded Systems. ISLPED'04, August 9- 11, 2004, Newport Beach, California, USA.
[4] Fen Xie, Margaret Martonosi, Sharad Malik. Efficient Behavior driven Runti me Dynamic Voltage Scaling Policies. CODES+ISSS'05, Sept. 19-21, 2005, Jersey City, New Jersey, USA.
[5] Linwei Niu, Gang Quan. Reducing Both Dynamic and Leakage Energy Con sumption for Hard RealTime Systems. CASES'04, September 22-25, 2004, Was hington, DC, USA.
[6] tefan Valentin Gheorghita, Twan Basten and Henk Corporaal. Intra-task Scen ario-aware Voltage Scheduling. CASES'05, September 24?27, 2005, San Francisco, California, USA.
[7] FEN XIE, MARGARET MARTONOSI, and SHARAD MALIK. Intra-program Dynamic Voltage Scaling: Bounding Opportunities with Analytic Modeling. A CM Transactions on Architecture and Code Optimization, Vol. 1, No. 3, September 2004, Pages 323-367.
[8] Feihui Li, Guangyu Chen, Mahmut Kandemir, and Mary Jane Irwin. Compiler Directed Proactive Power Management for Networks. CASES'05, September 24-27, 2005, San Francisco.
[9] Chaeseok Im and Soonhoi Ha. Dynamic Voltage Scaling for Real-Time Multi-task Scheduling Using Buffers. LCTES'04, June 11-13, 2004, Washington, DC, USA.
[10] Seung Woo Son, Mahmut Kandemir. Energy Aware Data Prefetching for Multi Speed Disks. CF'06, May 3-5, 2006, Ischia, Italy.
[11] M. Kandemir, N. Vijaykrishnan, M. J. Irwin, and W. Ye. Influence of com piler optimizations on system power. DAC 2000, Los Angeles, California.
[12] Madhavi Valluri and Lizy John. Is Compiling for Performance == Compililing for Power
[13] Chingren Lee, Jenq Kuen Lee, TingTing Hwang. Compiler Optimization on Instruction Scheduling for Low Power.
[14] AKHILESH TYAGI, GYUNGHO LEE. A compiler optimization paradigm for dynamic energy management.
[15] I. KADAYIF, M. KANDEMIR, G CHEN, N. VIJAYKRISHNAN, M. J. IR WIN, and A. SIVASUBRAMANIAM. Compiler-Directed High-Level Energy Esti mation and Optimization. ACM Transactions on Embedded Computing Systems, Vol. 4, No. 4, November 2005, Pages 819-850.
[16] Chung-Hsing Hsu, Ulrich Kremer, Michael Hsiao. Compiler-Directed Dyna mic VF Scheduling for Energy Reduction in Microprocessors. ISLPED'01, August 6-7, 2001, Huntington Beach, California, USA.
[17] Ana Azevedo, Ilya Issenin, Radu Cornea. Profile-based Dynamic Voltage Scheduling using Program Checkpoints. Proceedings of the 2002 Design, Automation and Test in Europe Conference and Exhibition (DATE?02).
[18] Saurabh Chheda, Osman Unsal. Combining Compiler and Runtime IPC predictions to Reduce Energy in Next Generation. CF'04, April 14 - 16, 2004, Ischia, Italy.
[19] H. Saputra, M. Kandemir, N. Vijaykrishnan, M. J. Irwin, J. S. Hu, C-H. Hsu, U. Kremer. Energy-Conscious Compilation Based on Voltage Scaling. LCTES'02-SCOPES'02, June 19-21, 2002, Berlin, Germany.
[20] Nevine AbouGhazaleh, Bruce Childers, Daniel Moss' e, Rami Melhem, Matthew Craven. Energy Management for Real-Time Embedded Applications with Compiler Support. LCTES'03, June 11-13, 2003, San Diego, California, USA.
[21] Yifan Zhu, Frank Mueller. Feedback EDF Scheduling Exploiting Hardware-Assisted Asychronous Dynamic Voltage Scaling . LCTES'05, June 15?17, 2005, Chicago, Illinois, USA.
[22] NEVINE ABOUGHAZALEH, DANIEL MOSSE' , BRUCE R. CHILDERS, and RAMI MELHEM. Collaborative Operating System and Compiler Power Management for Real-Time Applications. ACM Transactions on Embedded Computing Systems, Vol. 5, No. 1, February 2006, Pages 82-115.
[23] Ripal Nathuji, Balasubramanian Seshasayee, Karsten Schwan. Combing Compiler and Operating System Support for Energy Efficient IO on Embedded Platforms. SCOPES'05, September 29-October 1, 2005, Dallas, TX USA.
[24] Chi-Keung Luk, Robert Cohn, Robert Muth, Harish Patil, Artur Klauser, and Geoff Lowney. PIN Bulding Cutomized Program Analysis Tools with Dynamic Instrucmenation. PLDI'05 June 12-15,2005,Chicago,Illinois,USA.
[25] Qiang Wu, V.J. Reddi, Youfeng Wu, Jin Lee, Dan Connors, David Brooks, Margaret Martonosi, Douglas W. Clark. A Dynamic Compilation Framework for Controlling Microprocessor Energy and Performance. Proceedings of the 38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'05).
[26] SUMESH UDAYAKUMARAN, ANGEL DOMINGUEZ, and RAJEEV BARUA. Dynamic Allocation for Scratch-Pad Memory Using Compile-Time Decisions. ACM Transactions on Embedded Computing Systems, Vol. 5, No. 2, May 2006, Pages 472-511.
[27] P. Unnikrishnan, M. Kandemir, and F. Li. Reducing Dynamic Compilation Overhead by Overlapping Compilation and Execution. 11th Asia and South Pacific Design Automation Conference, January, 2006.
[28] P. Grun, N. Dutt and A. Nicolau, "Memory-aware Compilation through Accurate Timing Extraction," Proc. 37th Design Automation Conference, 2000.
[29] I. Kadayif, M. Kandemir, N. Vijaykrishnan, M. J. Irwin, and A. Sivasubra maniam. EAC A Compiler Framework for High-Level Energy Estimation and O ptimization. Proceedings of the 2002 Design, Automation and Test in Europe C onference and Exhibition (DATE 02).
[30] D. Burger and T. Austin. The SimpleScalar tool set version 2.0. Technical Report 1342, Computer Science Department, University of Wisconsin, June 1997.
[31] D. Brooks, V. Tiwari and M. Martonosi, "Wattch: A Framework for Archit ectural-Level Power Analysis and Optimizations," Proc. 27th International Symp osium on Computer Architecture, 2000.
[32] W. Ye, N. Vijaykrishna, M. Kandemir, and M.J. Irwin. The design and use of SimplePower: A cycle-accurate energy estimation tool. In Design Automation Conference , June 2000.
[33] Markus Lorenz, Lars Wehmeyer, Thorsten Drager. Energy aware Compilation for DSPs with SIMD Instructions. LCTES'02-SCOPES'02, June 19-21, 2002, Berlin, Germany.
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