1024点浮点FFT处理器的研究与实现
摘要
FFT处理器在语音识别,图像处理和频谱分析等有着广泛的应用,在OFDM系统中各子载波的调制解调采用一个实时的快速傅里叶变换FFT处理器来实现,在OFDM系统中数据传输的速率一般是在6Mbps到155Mbpd之间,在速度上对FFT处理器提出了很高的要求。随着集成电路制造水平的不断进步,自主研发的高性能FFT处理器成为可能,根据项目要求,对专用FFT实现方法进行研究,通过选用不同硬件结构,在综合考虑硬件特性和满足系统设计要求的前提下,采用ASIC设计方法学进行设计,设计自由度大,也能够很好地符合SOC片上系统的设计要求。
论文采用自顶向下的设计方法设计了1024点的浮点数傅里叶变换FFT处理器,在RTL级给出了完整的设计描述,编写测试平台对于每个模块都进行了前仿真和时序分析,基于DC完成ASIC综合和时序约束,在顶层完成功能验证和随机性测试,得到的结果和由C语言搭建的仿真模块进行比较和对照,在matlab中进一步验证,最后应用于OFDM系统当中。
设计和验证过程中主要的创新点有:采用CSA进位保留加法器加速浮点数加法运算和浮点数乘法运算,蝶形运算单元采用纯组合逻辑设计,综合时认为是一条长周期路径,占用3个时钟周期的计算时间;各级旋转因子表大小不同,节省ROM的存储空间,RAM采用双口RAM设计,可以同时读写,增加一个RAM完成信号,用于实现蝶形单元的迭代控制;每一个中间级采用双状态机加计数器对运算进行控制和读写地址使能的生成;建立测试平台,对于流水线中间级测试平台可以重用,编写结构化Testbench实现测试模块的可重用性;提出新的针对于FFT处理器的详细验证方案,编写浮点数和实数间转换的软件接口,基于C语言平台编写FFT仿真模块,和RTL级顶层模块输出的数值进行比较,并利用matlab输出最终波形。
最后总结论文中主要的研究进展,展望在数字信号处理领域的进一步研究方向,并基于FPGA验证完成FFT处理器的研究与实现。设计的浮点数FFT处理器和别的FFT处理器相比具有很多方面的优点,输入输出数据的范围得到很大的拓宽,十级流水线大幅增加吞吐量满足实时性转换要求,1024点的FFT精度满足在高性能的通信系统里面的要求。
FFT processor has a wide range of applications in speech recognition, image processing and spectrum analysis, and in the OFDM system we use the real-time FFT processor to achieve the sub carrier modulation and demodulation, another way the OFDM system also has the high request of FFT processor with the general rate between 6Mps to 155Mps. With the level of IC manufacturers continue to progress, independent research and development of high-performance FFT processor is possible, according to project requirements we study the FFT method, choose the structures of hardware and design under the premise of ASIC design methodology, also able to meet the SOC system-on-chip design requirements.
In this article we use the top-down design methodology to design the 1024-point floating-point FFT processor. First we complete the description in RTL-level design and the testbench of each module for timing analysis; second base on DC we complete the ASIC synthesis and timing constraints; third the mainly job is the completion of top-level functional verification and random test, the results is compared with the simulation module built by C language and constrast further validation in matlab; Finally the FFT processor applied in OFDM systems.
The main points of innovation in design and verification are: the application of CSA to speed up floating point adder and multiplication operations; the design of radix module with combinational logic is a long cycle path, occupied by three the calculation of clock cycle time; for saving the storage space table size of ROM in different levels is different, RAM design using dual-port RAM, you can read and write at the same time to increase the speed; an intermediate level of each state machine plus dual counter to read and write operations to control and enable the generation of address; set up a testbench for the middle-level testbench assembly line can be reused, the preparation of a structured test module testbench to achieve reusability; based on the C language platform for the preparation of FFT simulation module, and RTL-level top-level module to compare the output value and the ultimate use of matlab output waveform.
In conclusion, we verify the completion of FPGA-based FFT processor research and implementation. Floating-point FFT processor compared to other FFT processors has many merits, the scope of input and output data have been greatly expand, and 10 pipeline levels satisfy the conversion requirements of real-time, 1024 points FFT accuracy meet the communication system in which high-performance requirements.
论文采用自顶向下的设计方法设计了1024点的浮点数傅里叶变换FFT处理器,在RTL级给出了完整的设计描述,编写测试平台对于每个模块都进行了前仿真和时序分析,基于DC完成ASIC综合和时序约束,在顶层完成功能验证和随机性测试,得到的结果和由C语言搭建的仿真模块进行比较和对照,在matlab中进一步验证,最后应用于OFDM系统当中。
设计和验证过程中主要的创新点有:采用CSA进位保留加法器加速浮点数加法运算和浮点数乘法运算,蝶形运算单元采用纯组合逻辑设计,综合时认为是一条长周期路径,占用3个时钟周期的计算时间;各级旋转因子表大小不同,节省ROM的存储空间,RAM采用双口RAM设计,可以同时读写,增加一个RAM完成信号,用于实现蝶形单元的迭代控制;每一个中间级采用双状态机加计数器对运算进行控制和读写地址使能的生成;建立测试平台,对于流水线中间级测试平台可以重用,编写结构化Testbench实现测试模块的可重用性;提出新的针对于FFT处理器的详细验证方案,编写浮点数和实数间转换的软件接口,基于C语言平台编写FFT仿真模块,和RTL级顶层模块输出的数值进行比较,并利用matlab输出最终波形。
最后总结论文中主要的研究进展,展望在数字信号处理领域的进一步研究方向,并基于FPGA验证完成FFT处理器的研究与实现。设计的浮点数FFT处理器和别的FFT处理器相比具有很多方面的优点,输入输出数据的范围得到很大的拓宽,十级流水线大幅增加吞吐量满足实时性转换要求,1024点的FFT精度满足在高性能的通信系统里面的要求。
FFT processor has a wide range of applications in speech recognition, image processing and spectrum analysis, and in the OFDM system we use the real-time FFT processor to achieve the sub carrier modulation and demodulation, another way the OFDM system also has the high request of FFT processor with the general rate between 6Mps to 155Mps. With the level of IC manufacturers continue to progress, independent research and development of high-performance FFT processor is possible, according to project requirements we study the FFT method, choose the structures of hardware and design under the premise of ASIC design methodology, also able to meet the SOC system-on-chip design requirements.
In this article we use the top-down design methodology to design the 1024-point floating-point FFT processor. First we complete the description in RTL-level design and the testbench of each module for timing analysis; second base on DC we complete the ASIC synthesis and timing constraints; third the mainly job is the completion of top-level functional verification and random test, the results is compared with the simulation module built by C language and constrast further validation in matlab; Finally the FFT processor applied in OFDM systems.
The main points of innovation in design and verification are: the application of CSA to speed up floating point adder and multiplication operations; the design of radix module with combinational logic is a long cycle path, occupied by three the calculation of clock cycle time; for saving the storage space table size of ROM in different levels is different, RAM design using dual-port RAM, you can read and write at the same time to increase the speed; an intermediate level of each state machine plus dual counter to read and write operations to control and enable the generation of address; set up a testbench for the middle-level testbench assembly line can be reused, the preparation of a structured test module testbench to achieve reusability; based on the C language platform for the preparation of FFT simulation module, and RTL-level top-level module to compare the output value and the ultimate use of matlab output waveform.
In conclusion, we verify the completion of FPGA-based FFT processor research and implementation. Floating-point FFT processor compared to other FFT processors has many merits, the scope of input and output data have been greatly expand, and 10 pipeline levels satisfy the conversion requirements of real-time, 1024 points FFT accuracy meet the communication system in which high-performance requirements.
引文
田耘,徐文波,张延伟,等.2008.无线通信FPGA设计[M].北京:电子工业出版社,110-120.
夏宇闻,编著.2007.数字系统设计-verilog实现[M].北京:高等教育出版社,20-50.
谭浩强,著.2002.C程序设计[M].北京:清华大学出版社.
吴继华,王诚,编著.2006.Verilog HDL设计与验证[M].北京:人民邮电出版社.
孙海平,译.2007.VHDL代码编写和基于SYNOPSYS工具的逻辑综合[M].清华大学出版社.156-226
李广军,李林等译.2007.Verilog数字系统设计—RTL综合,测试平台与验证[M].北京:电子工业出版社,140-161
宽带无线通信OFDM技术[M].王文博,郑侃,编著.北京:人民邮电出版社,6-19.
陶金.2006.OFDM调制中的高效FFT处理器的设计与FPGA实现[D]:硕士.上海:上海交通大学,4-8.
赵亮.2006.宽带OFDM系统研究及FPGA实现[D]:硕士.杭州:浙江大学,64-66.
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王旭姣,梁利平.2007.一种基于事务的IP功能验证环境[J].微电子学与计算机.第24卷第7期.
董玲,张松,于宗光,陶建中,2006.基于Verilog的一种高效验证平台的研究及应用[J].微电子学与计算机.第23卷第1期.
欧海,赵明生.2007.基于FPGA的多制式高速QAM调制器设计[J].微计算机信息.第23卷第2-2期.
刘伟,高勇.2008.16QAM差分调制技术及DSP实现[J].太原理工大学学报.
张爱良.2007.基于IEEE-754变异型浮点数数制转换的程序设计[J].重庆文理学院学报.第26期.
汪润来.2007.1024点复数专用FFT处理器的ASIC实现[D]:硕士.成都:电子科技大学,11-21.
高瞻.2006.FFT处理器设计及其应用研究[D]:硕士.西南交通大学,50-61.
连冰.2004.FFT的FPGA实现及MIMO系统性能仿真[D]:硕士.西安:西安电子科技大学,7-22.
杨贵.2004.FPGA在数字信号处理中的应用与研究[D]:硕士.长沙:湖南大学,2-3.
韩泽耀.2002.高速高性能FFT处理器的VLSI实现研究[D]:博士.杭州:浙江大学,28-33.
邓学禹.2005.基于FPGA的1024点流水线工作方式的FFT实现[D]:硕士.成都:电子科技大学,31-50.
宋军江.2007.基于FPGA的32位浮点数据FFT及IFFT的设计与实现[D]:硕士.广州:中山大学.
于效宇.2005.基于FPGA的FFT处理器的实现[D]:硕士.哈尔滨:哈尔滨理工大学,50-52.
蔡可红.2006.基于FPGA的FFT设计与实现[D]:硕士.南京:南京理工大学,54-62.
刘亚海.2005.基于FPGA的FFT数字处理器的硬件实现[D]:硕士:同济大学,42-57.
George, K,Chen, C.I.H.2007.Configurable and Expandable FFT Processor for Wideband Communication[J]. IEEE CNF.
Saidi, A.1994.Decimation-in-time-frequency FFT algorithm[J]. IEEE CNF.
Yuke Wang, Yiyan Tang, Yingtao Jiang, Jin-Gyun Chung; Sang-Seob Song, Myoung-Seob Lim.2008.Novel Memory Reference Reduction Methods for FFT Implementations on DSP Processors[J]. IEEE JNL.
Johnston, J.1983. Parallel pipeline fast fourier transformer[J].IET JNL.
Chin-Teng Lin; Yuan-Chu Yu; Lan-Da Van. A low-power 64-point FFT/IFFT design for IEEE 802.11a WLAN application[J]. IEEE CNF.
Yu-Wei Lin; Chen-Yi Lee.2007.Design of an FFT/IFFT Processor for MIMO OFDM Systems[J]. IEEE JNL.
Mahdavi, N.; Teymourzadeh, R.; Bin Othman, M.2007.VLSI Implementation of High Speed and High Resolution FFT Algorithm Based on Radix 2 for DSP Application[J].IEEE CNF.
Shiqun Zhang; Dunshan Yu. 2004. Design and implementation of a parallel real-time FFT processor[J].IEEE CNF.
夏宇闻,编著.2007.数字系统设计-verilog实现[M].北京:高等教育出版社,20-50.
谭浩强,著.2002.C程序设计[M].北京:清华大学出版社.
吴继华,王诚,编著.2006.Verilog HDL设计与验证[M].北京:人民邮电出版社.
孙海平,译.2007.VHDL代码编写和基于SYNOPSYS工具的逻辑综合[M].清华大学出版社.156-226
李广军,李林等译.2007.Verilog数字系统设计—RTL综合,测试平台与验证[M].北京:电子工业出版社,140-161
宽带无线通信OFDM技术[M].王文博,郑侃,编著.北京:人民邮电出版社,6-19.
陶金.2006.OFDM调制中的高效FFT处理器的设计与FPGA实现[D]:硕士.上海:上海交通大学,4-8.
赵亮.2006.宽带OFDM系统研究及FPGA实现[D]:硕士.杭州:浙江大学,64-66.
庞景先,温坚,赵明晶.1995.时域抽取基2快速傅里叶变换(FFT)算法[J].光学精密工程.第3卷第3期:43-50
杜宁,郑建宏.2008.一种可重用的SOC验证平台[J].微计算机信息.第24卷第2-2期.
王旭姣,梁利平.2007.一种基于事务的IP功能验证环境[J].微电子学与计算机.第24卷第7期.
董玲,张松,于宗光,陶建中,2006.基于Verilog的一种高效验证平台的研究及应用[J].微电子学与计算机.第23卷第1期.
欧海,赵明生.2007.基于FPGA的多制式高速QAM调制器设计[J].微计算机信息.第23卷第2-2期.
刘伟,高勇.2008.16QAM差分调制技术及DSP实现[J].太原理工大学学报.
张爱良.2007.基于IEEE-754变异型浮点数数制转换的程序设计[J].重庆文理学院学报.第26期.
汪润来.2007.1024点复数专用FFT处理器的ASIC实现[D]:硕士.成都:电子科技大学,11-21.
高瞻.2006.FFT处理器设计及其应用研究[D]:硕士.西南交通大学,50-61.
连冰.2004.FFT的FPGA实现及MIMO系统性能仿真[D]:硕士.西安:西安电子科技大学,7-22.
杨贵.2004.FPGA在数字信号处理中的应用与研究[D]:硕士.长沙:湖南大学,2-3.
韩泽耀.2002.高速高性能FFT处理器的VLSI实现研究[D]:博士.杭州:浙江大学,28-33.
邓学禹.2005.基于FPGA的1024点流水线工作方式的FFT实现[D]:硕士.成都:电子科技大学,31-50.
宋军江.2007.基于FPGA的32位浮点数据FFT及IFFT的设计与实现[D]:硕士.广州:中山大学.
于效宇.2005.基于FPGA的FFT处理器的实现[D]:硕士.哈尔滨:哈尔滨理工大学,50-52.
蔡可红.2006.基于FPGA的FFT设计与实现[D]:硕士.南京:南京理工大学,54-62.
刘亚海.2005.基于FPGA的FFT数字处理器的硬件实现[D]:硕士:同济大学,42-57.
George, K,Chen, C.I.H.2007.Configurable and Expandable FFT Processor for Wideband Communication[J]. IEEE CNF.
Saidi, A.1994.Decimation-in-time-frequency FFT algorithm[J]. IEEE CNF.
Yuke Wang, Yiyan Tang, Yingtao Jiang, Jin-Gyun Chung; Sang-Seob Song, Myoung-Seob Lim.2008.Novel Memory Reference Reduction Methods for FFT Implementations on DSP Processors[J]. IEEE JNL.
Johnston, J.1983. Parallel pipeline fast fourier transformer[J].IET JNL.
Chin-Teng Lin; Yuan-Chu Yu; Lan-Da Van. A low-power 64-point FFT/IFFT design for IEEE 802.11a WLAN application[J]. IEEE CNF.
Yu-Wei Lin; Chen-Yi Lee.2007.Design of an FFT/IFFT Processor for MIMO OFDM Systems[J]. IEEE JNL.
Mahdavi, N.; Teymourzadeh, R.; Bin Othman, M.2007.VLSI Implementation of High Speed and High Resolution FFT Algorithm Based on Radix 2 for DSP Application[J].IEEE CNF.
Shiqun Zhang; Dunshan Yu. 2004. Design and implementation of a parallel real-time FFT processor[J].IEEE CNF.