系统级封装的电源完整性分析和电磁干扰研究
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摘要
随着人们对电子产品需求的不断增大,微电子封装正向小型化、高速、高密度和系统化的方向发展,系统级封装(System-in-Package, SiP)技术在集成电路产品中扮演着越来越重要的角色。在电子系统高速、高密度、高功耗、低电压和大电流的发展趋势下,电源完整性(Power Integrity, PI)分析对新产品的成败起到关键性的作用。系统级封装中的电源分布网络(Power Delivery Network, PDN)设计和电源完整性研究的挑战日益严峻。
本论文系统研究了系统级封装的电源完整性分析,电源分布网络设计以及三维混合芯片堆叠引起的近场耦合问题。对封装级PDN结构设计,宽频带、高隔离深度的噪声隔离抑制技术以及新型混合芯片三维堆叠屏蔽结构进行了重点研究上。论文的主要内容和研究成果如下：
1)在总结和消化前人研究成果的基础上,首先从PDN的噪声源和PDN设计的作用出发,阐述了PDN各个组成部分的特性和相关技术问题。针对系统级PDN设计,总结了目标阻抗设计方法的新解释：考虑到芯片工作电流随时间变化时,可使用自适应目标阻抗方法；多芯片系统目标阻抗设计方法还需考虑芯片间噪声耦合等方面。从基本原理上说明了电源完整性与信号完整性(Signal Integrity, SI)、电磁干扰(Electromagnetic Interference, EMI)以及制造工艺的关系。针对封装设计,尤其三维混合芯片堆叠封装,提出了PI与SI、EMI以及制造工艺协同设计的思路,并应用到高密度、大功耗专用集成芯片的低成本封装设计和三维混合芯片堆叠屏蔽设计中。
2)针对高密度、大功耗数字电路或高速数字电路中的瞬态开关噪声(Simultaneous Switching Noise, SSN)抑制问题,研究了封装级电源分布网络的低阻抗设计。首先从谐振腔模型法入手分析了电源／地平面谐振特性和降低输入阻抗的方法。通过电路建模和电磁场模型仿真,讨论了封装级连接线对电源波动的影响。对典型的连接线结构建立等效电路图,并结合电磁场方法分段拟合提取电路参数,指出降低连接线电感的具体设计方法。并将低阻抗PDN的设计方法应用到实际的封装设计中。
3)系统级封装中芯片间的噪声抑制是封装级PDN设计的另一个重点。为了解决噪声在PDN中的传导性耦合问题,本论文提出了新型π型低通滤波器结构,并建立了相应的电路模型。新型结构具有结构简单、成本低,抑制频带宽,与现有制造工艺兼容等特点,非常适用于系统级的PDN设计。将新型π型滤波器结构用于高速多芯片PDN设计中,实现了相同供电系统0.3GHz到10GHz宽频内低于-40dB的噪声隔离深度,不同供电系统DC到10GHz的宽频内能够达低于-70dB的噪声隔离深度。PDN作为信号线的回流路径时,任何不连续点都能直接造成传输线的阻抗不匹配,影响信号的传输质量。本论文将新型π型低通滤波器和回流过孔用于封装PDN设计,为传输线提供很好的低噪声回路。
4)除了由PDN谐振引起基板边缘辐射带来的EMI问题外,三维混合芯片堆叠封装的近场干扰问题也很严重。本论文的EMI问题特指混合芯片堆叠封装的近场电感性耦合问题。将晶体管间的电流回路等效成电流环,定性的分析了混合芯片间或者噪声源芯片与键合线间的近场耦合。并提出了一种新型三维屏蔽堆叠结构用于近场电感性噪声的屏蔽。新型三维屏蔽结构在有限封装空间内具有很好的噪声屏蔽效果和一定的热传导作用,以及制造工艺与现有工艺兼容的特点。另外,敏感芯片放置可在芯片堆叠的底层,有效的减小了敏感芯片的键合线长度,提高信号线的传输质量。新型三维屏蔽堆叠结构的屏蔽效能可达150dB,某些频段甚至达到了240dB。
With the vastly boosting demands of human beings for electronic products, the new trends of miniaturization, multi-function, high-integration and environmental protection are playing a key role in the microelectronic packages evolvement. System-in-Package (SiP) is the main role on this stage. The high speed, high density, high power consumption, low voltage and high current propose a significant challenge towards the Power Delivery Network (PDN) and Power Integrity (PI) which are critical to the quality of products where market demand happens.
This thesis digs into the Power Integrity analysis, Power Delivery Network design and near field coupling effects within the 3D SiP package. The keystone is the study of structure design of PDN, as well as wide-band, high isolating depth and new 3D shielding configuration. The contents and results are concluded as below:
1) Based on the previous research work, the characteristics and related technical issues have been discussed according to the PDN noise source and SiP PDN design application. The problems to be specially noticed in target impedance method are also presented including adaptive target impedance method when current changes with the time and noise coupling considerations with multi-chip target impedance method etc. Focus on package design, especially 3D mixed chips stacking system, the relations between PI, Signal Integrity (SI), Electromagnetic Interference (EMI), and fabrication processes are illustrated theoretically, and the collaborative designs are discussed, such as a high density, high power consumption, low cost ASIC package and 3D mixed chips stacking.
2) With the issue of Simultaneous Switching Noise (SSN) in high density, high power consumption or high speed digital circuit, the low impedance design of the package level PDN is studied. Firstly, the power/ground resonance and low input impedance with method of cavity model is discussed. The voltage fluctuation coming from the connction structure is discussed with the ciruit analysis and elctromagneitic simulation. Equivalent circuit schematic is built for typical connection structure, combining the Electromagnetic simulator results in fitting circuit parameters, to approach the lower connection inductance. The low impedance of low inductance and high capacitance are also applicable in the practical package design.
3) The noise suppression in SiP PDN design is another main issue in this thesis. To solve the noise transmitting coupling problems in PDN, a novelπ-type Low-Pass-Filter (LPF) structure is proposed and corresponding circuit model is built and discussed. The new device has the merits of simple structure, low-cost, wide suppression bandwidth, compatible with current process etc. and is very suitable for SiP PDN design. The novel designedπ-type LPF structure is applied in high-speed multi-chips PDN design and implements the-40dB isolation from 0.3GHz to 10GHz, and lower than-70dB within different powering systems with frequency from DC to 10GHz. When PDN is treated as the signal return path, any discontinuous points lead to mismatching of transmission line and degrade the signal quality. The newπ-type LPF and return path via design is applicable in package PDN design, and is validated to provide very low noise return path.
4) Besides the Electromagnetic interference (EMI) problem caused by edge radiation on baseboard due to the PDN resonance, the near field interference problem, which is focoused on in this article, within 3D mixed chips stacking is also severe. The thesis equivalents the current return paths among the transistors to be the current ring, and qualitatively analyses the inductive coupling between mixed chips or chip and bonding wire. Accordingly a new 3D shielding structure applicable for shielding near-field inductive coupling is proposed. This structure has the merits of shielding noises, thermal relief and compatibility with the modern shielding materials and processes. The sensitive chip is placed at the bottom of the stacking structure because the bonding wires with sensitive signals are shortened. The isolation of the structure is up to 150dB, and at certain point of frequency, the extraordinary 240dB can be achieved.
本论文系统研究了系统级封装的电源完整性分析,电源分布网络设计以及三维混合芯片堆叠引起的近场耦合问题。对封装级PDN结构设计,宽频带、高隔离深度的噪声隔离抑制技术以及新型混合芯片三维堆叠屏蔽结构进行了重点研究上。论文的主要内容和研究成果如下：
1)在总结和消化前人研究成果的基础上,首先从PDN的噪声源和PDN设计的作用出发,阐述了PDN各个组成部分的特性和相关技术问题。针对系统级PDN设计,总结了目标阻抗设计方法的新解释：考虑到芯片工作电流随时间变化时,可使用自适应目标阻抗方法；多芯片系统目标阻抗设计方法还需考虑芯片间噪声耦合等方面。从基本原理上说明了电源完整性与信号完整性(Signal Integrity, SI)、电磁干扰(Electromagnetic Interference, EMI)以及制造工艺的关系。针对封装设计,尤其三维混合芯片堆叠封装,提出了PI与SI、EMI以及制造工艺协同设计的思路,并应用到高密度、大功耗专用集成芯片的低成本封装设计和三维混合芯片堆叠屏蔽设计中。
2)针对高密度、大功耗数字电路或高速数字电路中的瞬态开关噪声(Simultaneous Switching Noise, SSN)抑制问题,研究了封装级电源分布网络的低阻抗设计。首先从谐振腔模型法入手分析了电源／地平面谐振特性和降低输入阻抗的方法。通过电路建模和电磁场模型仿真,讨论了封装级连接线对电源波动的影响。对典型的连接线结构建立等效电路图,并结合电磁场方法分段拟合提取电路参数,指出降低连接线电感的具体设计方法。并将低阻抗PDN的设计方法应用到实际的封装设计中。
3)系统级封装中芯片间的噪声抑制是封装级PDN设计的另一个重点。为了解决噪声在PDN中的传导性耦合问题,本论文提出了新型π型低通滤波器结构,并建立了相应的电路模型。新型结构具有结构简单、成本低,抑制频带宽,与现有制造工艺兼容等特点,非常适用于系统级的PDN设计。将新型π型滤波器结构用于高速多芯片PDN设计中,实现了相同供电系统0.3GHz到10GHz宽频内低于-40dB的噪声隔离深度,不同供电系统DC到10GHz的宽频内能够达低于-70dB的噪声隔离深度。PDN作为信号线的回流路径时,任何不连续点都能直接造成传输线的阻抗不匹配,影响信号的传输质量。本论文将新型π型低通滤波器和回流过孔用于封装PDN设计,为传输线提供很好的低噪声回路。
4)除了由PDN谐振引起基板边缘辐射带来的EMI问题外,三维混合芯片堆叠封装的近场干扰问题也很严重。本论文的EMI问题特指混合芯片堆叠封装的近场电感性耦合问题。将晶体管间的电流回路等效成电流环,定性的分析了混合芯片间或者噪声源芯片与键合线间的近场耦合。并提出了一种新型三维屏蔽堆叠结构用于近场电感性噪声的屏蔽。新型三维屏蔽结构在有限封装空间内具有很好的噪声屏蔽效果和一定的热传导作用,以及制造工艺与现有工艺兼容的特点。另外,敏感芯片放置可在芯片堆叠的底层,有效的减小了敏感芯片的键合线长度,提高信号线的传输质量。新型三维屏蔽堆叠结构的屏蔽效能可达150dB,某些频段甚至达到了240dB。
With the vastly boosting demands of human beings for electronic products, the new trends of miniaturization, multi-function, high-integration and environmental protection are playing a key role in the microelectronic packages evolvement. System-in-Package (SiP) is the main role on this stage. The high speed, high density, high power consumption, low voltage and high current propose a significant challenge towards the Power Delivery Network (PDN) and Power Integrity (PI) which are critical to the quality of products where market demand happens.
This thesis digs into the Power Integrity analysis, Power Delivery Network design and near field coupling effects within the 3D SiP package. The keystone is the study of structure design of PDN, as well as wide-band, high isolating depth and new 3D shielding configuration. The contents and results are concluded as below:
1) Based on the previous research work, the characteristics and related technical issues have been discussed according to the PDN noise source and SiP PDN design application. The problems to be specially noticed in target impedance method are also presented including adaptive target impedance method when current changes with the time and noise coupling considerations with multi-chip target impedance method etc. Focus on package design, especially 3D mixed chips stacking system, the relations between PI, Signal Integrity (SI), Electromagnetic Interference (EMI), and fabrication processes are illustrated theoretically, and the collaborative designs are discussed, such as a high density, high power consumption, low cost ASIC package and 3D mixed chips stacking.
2) With the issue of Simultaneous Switching Noise (SSN) in high density, high power consumption or high speed digital circuit, the low impedance design of the package level PDN is studied. Firstly, the power/ground resonance and low input impedance with method of cavity model is discussed. The voltage fluctuation coming from the connction structure is discussed with the ciruit analysis and elctromagneitic simulation. Equivalent circuit schematic is built for typical connection structure, combining the Electromagnetic simulator results in fitting circuit parameters, to approach the lower connection inductance. The low impedance of low inductance and high capacitance are also applicable in the practical package design.
3) The noise suppression in SiP PDN design is another main issue in this thesis. To solve the noise transmitting coupling problems in PDN, a novelπ-type Low-Pass-Filter (LPF) structure is proposed and corresponding circuit model is built and discussed. The new device has the merits of simple structure, low-cost, wide suppression bandwidth, compatible with current process etc. and is very suitable for SiP PDN design. The novel designedπ-type LPF structure is applied in high-speed multi-chips PDN design and implements the-40dB isolation from 0.3GHz to 10GHz, and lower than-70dB within different powering systems with frequency from DC to 10GHz. When PDN is treated as the signal return path, any discontinuous points lead to mismatching of transmission line and degrade the signal quality. The newπ-type LPF and return path via design is applicable in package PDN design, and is validated to provide very low noise return path.
4) Besides the Electromagnetic interference (EMI) problem caused by edge radiation on baseboard due to the PDN resonance, the near field interference problem, which is focoused on in this article, within 3D mixed chips stacking is also severe. The thesis equivalents the current return paths among the transistors to be the current ring, and qualitatively analyses the inductive coupling between mixed chips or chip and bonding wire. Accordingly a new 3D shielding structure applicable for shielding near-field inductive coupling is proposed. This structure has the merits of shielding noises, thermal relief and compatibility with the modern shielding materials and processes. The sensitive chip is placed at the bottom of the stacking structure because the bonding wires with sensitive signals are shortened. The isolation of the structure is up to 150dB, and at certain point of frequency, the extraordinary 240dB can be achieved.
引文
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