异构多核处理芯片设计及优化
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摘要
异构多核是当今多核处理器设计的主流趋势。其核心思想是处理器中只有一个(或几个)通用的核心完成任务调度功能,主要的计算任务(如浮点运算、信号处理、图像处理等)则由专门的高性能计算核心来完成,从而大幅度提升处理器执行效率和性能。影响异构多核处理器性能的因素有很多,最主要的是架构和计算核心的性能。本文详细介绍了一款异构多核处理芯片。该芯片顶层架构为NoC(片上网络),集成了52个异构核,包括ARM处理器、协处理器、FFT/IFFT加速单元和转置加速单元。在FPGA上实现该芯片的结果表明,它能够满足实时成像算法的实时性要求,成像效果良好。
在原有的异构多核处理芯片的设计基础上,本文针对其中3个关键技术点进行了优化。
针对NI(网络接口),本文提出了一种基于微码控制器的设计方法,实现了一款同时支持3种链路通信协议的网络接口。可编程的设计使得该网络接口具有很强的灵活性、适应性。相比于传统的基于FSM(有限状态机)的网络接口设计,新的设计消耗的硬件资源减少了约10%。
针对Sin/Cos运算模块,本文从理论上分析了原有设计的误差,并提出了一种通过补偿求余来提高相位精度的方法。基于这种方法,本文设计出一款高精度的Sin/Cos运算模块,大幅度提高了求Sin函数值和Cos函数值的精度。为了节省的硬件资源消耗,改进的设计对中间数据的表示格式做了一定的优化。逻辑综合结果表明,硬件资源消耗量减少了约32%。
针对转置加速单元,本文一方面论述了在分布式存储系统下转置大矩阵的方法,另一方面改进了原有的转置簇(含转置加速单元)。理论分析和实验结果表明,新的设计大幅度提高了转置的速度,硬件资源的消耗却减少了约15%。影响转置效率的因素有很多,例如矩阵的规模、矩阵的形状、拆分矩阵的方式、缓冲区大小等等,在实验过程中进行了分组测试,分别统计出各种因素的影响程度,为高效的使用转置簇提供了参考。
Heterogeneous multi-core is the trend of today's multi-core processor design. Its key idea is that one (or several) general-purpose core in the processor handles the task scheduling, while dedicated computing cores handle main computing tasks (such as floating-point operations, signal processing, image processing, etc.) to improve the efficiency and performance of processor. There are many factors that can affect the performance of heterogeneous multi-core processors, architecture and functionality of the cores are the most important. In this paper, a heterogeneous multi-core processing chip is introduced. Using NoC(Network on Chip) as its top-level architecture, this chip integrates52heterogeneous cores including ARM, Coprocessor, FFT/IFFT Accelerator and Matrix Transpose Accelerator. Experiment results of implementing this chip on FPGAs show that it meets the real-time requirements of the imaging algorithm.
Based on the original designs of this heterogeneous multi-core processing chip, some optimizations have been done in this paper.
For the NI (Network Interface), this paper presents a design method based on micro-code controller and the realization of a new NI that supports three kinds of link communication protocol. Because it can be programmed using micro-code, this NI has strong flexibility and adaptability. Compared to the original design based on FSM(Finite State Machine), the overall hardware resource consumption of the new NI is reduced by about10%.
For the Sin/Cos Computing Unit, this paper theoretically analyzes the computing deviation of the original design and proposed a new algorithm which improves the precise of phase by compensation. Based on this algorithm, a high-precision Sin/Cos computing module is proposed, and this module improves the accuracy of Sin and Cos significantly. Optimization on the representation format of data has been done in order to save hardware resource. Logic synthesis results show this new design reduces about32%hardware resource consumption.
For the Matrix-Transpose Accelerator, this paper discusses the method of transposing large matrix in a distributed memory system and shows a improved design of the Transpose Cluster (including the Matrix-Transpose Accelerator). Theoretical analysis and experimental results are both indicating the new design can increase the speed of transposing matrices greatly while reducing about15%hardware resource consumption. As there are many factors (such as the size and shape of transposed matrix, method chosen to divide large matrix into smaller ones, the depth of Buffer, etc.) affecting the performance of Transpose Cluster, some statistical results on them have been derived from experiments providing a reference for the efficient utilization of this cluster.
在原有的异构多核处理芯片的设计基础上,本文针对其中3个关键技术点进行了优化。
针对NI(网络接口),本文提出了一种基于微码控制器的设计方法,实现了一款同时支持3种链路通信协议的网络接口。可编程的设计使得该网络接口具有很强的灵活性、适应性。相比于传统的基于FSM(有限状态机)的网络接口设计,新的设计消耗的硬件资源减少了约10%。
针对Sin/Cos运算模块,本文从理论上分析了原有设计的误差,并提出了一种通过补偿求余来提高相位精度的方法。基于这种方法,本文设计出一款高精度的Sin/Cos运算模块,大幅度提高了求Sin函数值和Cos函数值的精度。为了节省的硬件资源消耗,改进的设计对中间数据的表示格式做了一定的优化。逻辑综合结果表明,硬件资源消耗量减少了约32%。
针对转置加速单元,本文一方面论述了在分布式存储系统下转置大矩阵的方法,另一方面改进了原有的转置簇(含转置加速单元)。理论分析和实验结果表明,新的设计大幅度提高了转置的速度,硬件资源的消耗却减少了约15%。影响转置效率的因素有很多,例如矩阵的规模、矩阵的形状、拆分矩阵的方式、缓冲区大小等等,在实验过程中进行了分组测试,分别统计出各种因素的影响程度,为高效的使用转置簇提供了参考。
Heterogeneous multi-core is the trend of today's multi-core processor design. Its key idea is that one (or several) general-purpose core in the processor handles the task scheduling, while dedicated computing cores handle main computing tasks (such as floating-point operations, signal processing, image processing, etc.) to improve the efficiency and performance of processor. There are many factors that can affect the performance of heterogeneous multi-core processors, architecture and functionality of the cores are the most important. In this paper, a heterogeneous multi-core processing chip is introduced. Using NoC(Network on Chip) as its top-level architecture, this chip integrates52heterogeneous cores including ARM, Coprocessor, FFT/IFFT Accelerator and Matrix Transpose Accelerator. Experiment results of implementing this chip on FPGAs show that it meets the real-time requirements of the imaging algorithm.
Based on the original designs of this heterogeneous multi-core processing chip, some optimizations have been done in this paper.
For the NI (Network Interface), this paper presents a design method based on micro-code controller and the realization of a new NI that supports three kinds of link communication protocol. Because it can be programmed using micro-code, this NI has strong flexibility and adaptability. Compared to the original design based on FSM(Finite State Machine), the overall hardware resource consumption of the new NI is reduced by about10%.
For the Sin/Cos Computing Unit, this paper theoretically analyzes the computing deviation of the original design and proposed a new algorithm which improves the precise of phase by compensation. Based on this algorithm, a high-precision Sin/Cos computing module is proposed, and this module improves the accuracy of Sin and Cos significantly. Optimization on the representation format of data has been done in order to save hardware resource. Logic synthesis results show this new design reduces about32%hardware resource consumption.
For the Matrix-Transpose Accelerator, this paper discusses the method of transposing large matrix in a distributed memory system and shows a improved design of the Transpose Cluster (including the Matrix-Transpose Accelerator). Theoretical analysis and experimental results are both indicating the new design can increase the speed of transposing matrices greatly while reducing about15%hardware resource consumption. As there are many factors (such as the size and shape of transposed matrix, method chosen to divide large matrix into smaller ones, the depth of Buffer, etc.) affecting the performance of Transpose Cluster, some statistical results on them have been derived from experiments providing a reference for the efficient utilization of this cluster.
引文
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[9]H.Kondo, M.Nakajima, N.Masui et al. Design and Implementation of a Configurable Heterogeneous Multi-core SoC with Nine CPUs and Two Matrix Processors. IEEE Journal of Solid-State Circuits, Vol.43, Issue 4, pp.892-901,2008.
[10]L.Benini and G.De Micheli, "Networks on chips: A new SoC paradigm", IEEE Computer, vol. 35, no.1, pp.70-78, Jan.2002.
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[16]苗澎.并行DSP开发系统在SAR成像算法应用中的研究.硕士学位论文,南京航空航天大学,2002.
[17]施慧莉.基于多DSP的机载SAR雷达距离相处理研究.硕士学位论文,西北工业大学,2001.
[18]王俊.全数字式高分辨率SAR实时处理机研究.博士学位论文,北京航空航天大学,2001.
[19]张德峰.高速DSP板的开发及其在合成孔径雷达实时信号处理中的应用研究.博士学位论文,中国科学院,2001.
[20]肖欣.SAR实时处理机的FPGA实现.硕士学位论文,电子科技大学,2004.
[21]赵博FPGA在实时SAR成像系统中的应用.硕士学位论文,西安电子科技大学,2010.
[22]李晓飞.基于FPGA的SAR实时成像实现技术研究.硕士学位论文,电子科技大学,2009.
[23]Sumant Sat he, Daniel Wiklund, Dake Liu. Design of a Switching Node(Router) for On-Chip Networks, Proceedings of the 5th International Conference on ASIC, Beijing,2003, pp.75-78.
[24]"AMBATM Specification Revision 2.0", May 13,1999.
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