高电源抑制比低压差线性稳压器的设计与研究
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摘要
随着手机的不断普及和手机功能的不断增加，对电源管理的要求也更加复杂和严格。目前，电源管理集成电路市场大部分被国外产品占据，研究和开发国内的电源管理电路产品，能夺回巨大的市场。因此，开展本课题的研究具有特别重大的现实意义。
本文设计了一款高电源抑制比低压差线性稳压器芯片，它采用TSMC 0.6微米CMOS工艺设计，有良好的电源抑制比(低频超过90dB，高频40dB左右)，支持较宽的输入电压范围(3.0V-5.5V)，输出电压为2.8V，在典型电流(150mA)情况下，压差为160mv。该电路主要用作对电源敏感的后级电路(如射频电路、VCO等)的电源电压。此外，芯片中还集成了过流保护电路和过热保护电路，保证电路的安全工作。基于以上技术优势，该芯片具有高电源抑制比、低输出噪声的特点，同时外围电路简单，大大降低了设计成本，适用于手机、数码相机、MP3播放器、PDA等手提移动设备的供电模块。
在本文中首先阐述了低压差线性稳压器的基本理论，包括基本工作原理和主要的电路指标；然后根据性能需要进行了深入的技术研究和完整的电路设计；最后详细分析并解决了低压差线性稳压器设计中的难点和关键点。借助设计软件Cadence和Spectra对电路进行了完整的设计和仿真，给出了合理的电路数据。仿真结果表明该电路实现了设计功能，达到了设计之初制定的设计指标。
最后对全文进行了总结，并结合已经完成的研究内容提出了对下一步工作的展望。
With the prevalence of handsets, the requirement for power management is becoming more complex and more rigid. At present, many aboard companies still occupy the most market of power management ICs. And it has much great importance to require such a big market. Therefore, it is of great importance to study the low-dropout (LDO) linear voltage regulator circuit.
The object of this thesis is to design a high power supply rejection ratio (PSRR) low-dropout (LDO) linear voltage regulator. It adopts TSMC 0.6μm CMOS process, which has the high power supply rejection ratio (more than 90dB at low frequency, around 40dB at high frequency), wide input voltage range (3.0V-5.5V). The output voltage is 2.8V. When the load current is 150mA, the dropout voltage is only 160mv. The circuit is primarily used to power supply of the circuit, which is sensitive to power ripple, such as RF, VCO and so on. In addition, the thermal shutdown and current limit sub-blocks are also integrated in this chip, which guarantee the electric circuit working in safe operation area. The IC has high PSRR and low output noise based on the above technical advantages. At the same time, it has the most simple outer circle circuit, greatly reducing the cost. It is used as power supply for those systems: handset, MP3 player, PDA, numeral camera and so on.
During circuit designing, the basic theory of LDO linear voltage regulator, including basic working principle and the main circuit parameters, is given first. Then the technique is studied and the whole circuit of the IC is designed based on the performance requirement. Finally, the keys and difficulties of LDO linear voltage regulator are studied and solved. Applying Cadence and Spectra, the whole chip and its sub-block circuits are simulated, and more, the reasonable electric circuit datas are given. The simulation results indicate that the IC has achieved their function object.
At the end of this thesis, a conclusion is drawn and the prospect of future work is given combined with finished research.
本文设计了一款高电源抑制比低压差线性稳压器芯片，它采用TSMC 0.6微米CMOS工艺设计，有良好的电源抑制比(低频超过90dB，高频40dB左右)，支持较宽的输入电压范围(3.0V-5.5V)，输出电压为2.8V，在典型电流(150mA)情况下，压差为160mv。该电路主要用作对电源敏感的后级电路(如射频电路、VCO等)的电源电压。此外，芯片中还集成了过流保护电路和过热保护电路，保证电路的安全工作。基于以上技术优势，该芯片具有高电源抑制比、低输出噪声的特点，同时外围电路简单，大大降低了设计成本，适用于手机、数码相机、MP3播放器、PDA等手提移动设备的供电模块。
在本文中首先阐述了低压差线性稳压器的基本理论，包括基本工作原理和主要的电路指标；然后根据性能需要进行了深入的技术研究和完整的电路设计；最后详细分析并解决了低压差线性稳压器设计中的难点和关键点。借助设计软件Cadence和Spectra对电路进行了完整的设计和仿真，给出了合理的电路数据。仿真结果表明该电路实现了设计功能，达到了设计之初制定的设计指标。
最后对全文进行了总结，并结合已经完成的研究内容提出了对下一步工作的展望。
With the prevalence of handsets, the requirement for power management is becoming more complex and more rigid. At present, many aboard companies still occupy the most market of power management ICs. And it has much great importance to require such a big market. Therefore, it is of great importance to study the low-dropout (LDO) linear voltage regulator circuit.
The object of this thesis is to design a high power supply rejection ratio (PSRR) low-dropout (LDO) linear voltage regulator. It adopts TSMC 0.6μm CMOS process, which has the high power supply rejection ratio (more than 90dB at low frequency, around 40dB at high frequency), wide input voltage range (3.0V-5.5V). The output voltage is 2.8V. When the load current is 150mA, the dropout voltage is only 160mv. The circuit is primarily used to power supply of the circuit, which is sensitive to power ripple, such as RF, VCO and so on. In addition, the thermal shutdown and current limit sub-blocks are also integrated in this chip, which guarantee the electric circuit working in safe operation area. The IC has high PSRR and low output noise based on the above technical advantages. At the same time, it has the most simple outer circle circuit, greatly reducing the cost. It is used as power supply for those systems: handset, MP3 player, PDA, numeral camera and so on.
During circuit designing, the basic theory of LDO linear voltage regulator, including basic working principle and the main circuit parameters, is given first. Then the technique is studied and the whole circuit of the IC is designed based on the performance requirement. Finally, the keys and difficulties of LDO linear voltage regulator are studied and solved. Applying Cadence and Spectra, the whole chip and its sub-block circuits are simulated, and more, the reasonable electric circuit datas are given. The simulation results indicate that the IC has achieved their function object.
At the end of this thesis, a conclusion is drawn and the prospect of future work is given combined with finished research.
引文
[1] Leung K N, Mok P K T. A capacitor-free CMOS low-dropout regulator with damping-factor-control frequency compensation
[2] Leung K N, Mok P K T, Ki W H. A novel frequency compensation technique for low-voltage low-dropout regulator
[3] Kwok K C, Mok P K T. Pole-Zero tracking frequency compensation for low dropout regulator. IEEE International Symposium on Circuits and Systems, Arizona: Scottsdale, May 2002, vol. 4: 735-738.
[4] Rincon-Mora G A, Allen P A. A low-voltage, low-quiescent current, low-dropout regulator, IEEE J. of Solid-State Circuits, 1998, 33(1): 36-44.
[5] Chava C K, Silva-Martinez J. A frequency compensation scheme for LDO voltage regulators, IEEE Trans, On Circuits Syst, Ⅰ: regulator paper, 2004, 51(6): 1041-1050
[6] R. Perez, "A Comparative Assessment between Linear and Switching Power Supplies in Portable Electronic Devices", IEEE Symposium on Electromagnetic Compatibility, vol.2, 2000, pp.839-843
[7] Keith Billings, "Switching Power Supply Handbook", 2nded. Mc. Graw Hill, 1999
[8] 曾健平，田涛，刘利辉，晏敏，低功耗高电源抑制比CMOS带隙基准源设计，湖南大学学报(自然科学版)，2005年10月
[9] Chester Simpson, "Linear and Switching Voltage Regulator Fundamentals", Applications Note, National Semiconductor Inc.
[10] Bang S. Lee, "Understanding the Terms and Definitions of LDO Voltage Regulators", Application Reports, Texas Instruments Inc, literature number SLVA079
[11] Thomas Kugelstadt, "Fundamental Theory of PMOS Low-Dropout Linear Regulators", Application Reports, Texas Instruments Inc., literature number SLVA068
[12] Everett Rogers, "Stability analysis of low-dropout linear regulators with a PMOS pass element", Application Specialist, Power Management,, Texas Instruments Inc.
[13] Jeff Falin, "ESR, Stability, and the LDO Regulator", SLVA115, Texas Instruments, May 2002
[14] Thomas Szepesi, "Cell Phone Power Management Requires Small Regulators with Fast Response", Planet Analog, 21, Mar. 2002
[15] John C. Teel, "Understanding power supply ripple rejection in linear regulators", Power Management, Texas Instrument Inc.
[16] Philip E．Allen，Douglas R．Holberg，CMOS模拟电路设计，电子工业出版社，2002
[17] P. R. Gray and R. G. Meyer, Analysis and Design of Analog Integrated Circuits. New York: John Wiley & Sons, Inc., 1993
[18] 来新泉，刘鸿雁，魏荣峰，一种高电源抑制比低噪声快速启动的CMOS带隙基准电路设计，中国集成电路，设计开发，2005年9月。
[19] 任明岩，RF电路中LDO电源抑制比和噪声的选择，技术长廊
[20] Christopher Saint and Judy Saint, 集成电路版图设计(影印版), 清华大学出版社，2004
[21] Robert A. Pease, "A New Production Technique for Trimming Voltage Regulators", National Semiconductor, Linear Brief 46, July 1979
[22] 袁文师，吴建辉，基准电压源设计．半导体技术，第29卷第4期，91-94
[23] 拉扎维．毕查德，模拟CMOS集成电路设计[M]。西安：西安交通大学出版社，2003：309-319
[24] 程晓洁，冯全源，一种低功耗高可靠性的过流保护电路设计，微电子学与计算机，2006年第23卷第1期
[25] 石国韬，蒋国平，“一种高稳定低功耗CMOS过热保护电路的设计”，电子器件，第29卷第2期，2006年6月
[26] R. H. Charles and D. A. Hodges, "Charge Circuits for Analog LSI,"IEEE Trans. Circuits Syst, Vol. CAS-25, No.7, pp.490-497, July 1978
[27] X. Hu and K. W. Martin, "A Switched-Current Sample-and-Hold Circuit," IEEE J. Solid-State Circuits, Vol.32, N0.6, pp.898-904, Jan. 1997
[28] I. Mehr and T. L Sculley, "A 16-bit Current Sample/Hold Circuit Using a Digital CMOS Process," Proceedings of the IEEE International Symposium on Circuits and Systems, pp.5.417-5.420, 1994
[29] S. A Trotter, Introduction to Discrete-Time Signal Processing, New York: Wiley, 1976
[30] J. Doernberg, H. S. Lee, and D. A. Hodges, "Full-Speed Testing of A/D Converters," IEEE J. Solid-State Circuits, Vol.SC-19, No.6, pp.820o827, Dec. 1984
[31] [美]John．P．Uyemure著，周润德 译。超大规模集成电路与系统导论[D]．北京：电子工业出版社，2004
[32] [美]Christopher Saint／Judy Saint著，周润德，金申美译。集成电路掩模 设计—基础版图技术．北京：清华大学出版社
[33] LANDA PHAM，“选择LDO的方法”，今日电子，2004年第2期
[34] Texas Instruments, TPS71719 datasheet, "Low Noise, High-Bandwidth PSRR Low-Dropout 150mA Linear Regulator", 2006-2007
[2] Leung K N, Mok P K T, Ki W H. A novel frequency compensation technique for low-voltage low-dropout regulator
[3] Kwok K C, Mok P K T. Pole-Zero tracking frequency compensation for low dropout regulator. IEEE International Symposium on Circuits and Systems, Arizona: Scottsdale, May 2002, vol. 4: 735-738.
[4] Rincon-Mora G A, Allen P A. A low-voltage, low-quiescent current, low-dropout regulator, IEEE J. of Solid-State Circuits, 1998, 33(1): 36-44.
[5] Chava C K, Silva-Martinez J. A frequency compensation scheme for LDO voltage regulators, IEEE Trans, On Circuits Syst, Ⅰ: regulator paper, 2004, 51(6): 1041-1050
[6] R. Perez, "A Comparative Assessment between Linear and Switching Power Supplies in Portable Electronic Devices", IEEE Symposium on Electromagnetic Compatibility, vol.2, 2000, pp.839-843
[7] Keith Billings, "Switching Power Supply Handbook", 2nded. Mc. Graw Hill, 1999
[8] 曾健平，田涛，刘利辉，晏敏，低功耗高电源抑制比CMOS带隙基准源设计，湖南大学学报(自然科学版)，2005年10月
[9] Chester Simpson, "Linear and Switching Voltage Regulator Fundamentals", Applications Note, National Semiconductor Inc.
[10] Bang S. Lee, "Understanding the Terms and Definitions of LDO Voltage Regulators", Application Reports, Texas Instruments Inc, literature number SLVA079
[11] Thomas Kugelstadt, "Fundamental Theory of PMOS Low-Dropout Linear Regulators", Application Reports, Texas Instruments Inc., literature number SLVA068
[12] Everett Rogers, "Stability analysis of low-dropout linear regulators with a PMOS pass element", Application Specialist, Power Management,, Texas Instruments Inc.
[13] Jeff Falin, "ESR, Stability, and the LDO Regulator", SLVA115, Texas Instruments, May 2002
[14] Thomas Szepesi, "Cell Phone Power Management Requires Small Regulators with Fast Response", Planet Analog, 21, Mar. 2002
[15] John C. Teel, "Understanding power supply ripple rejection in linear regulators", Power Management, Texas Instrument Inc.
[16] Philip E．Allen，Douglas R．Holberg，CMOS模拟电路设计，电子工业出版社，2002
[17] P. R. Gray and R. G. Meyer, Analysis and Design of Analog Integrated Circuits. New York: John Wiley & Sons, Inc., 1993
[18] 来新泉，刘鸿雁，魏荣峰，一种高电源抑制比低噪声快速启动的CMOS带隙基准电路设计，中国集成电路，设计开发，2005年9月。
[19] 任明岩，RF电路中LDO电源抑制比和噪声的选择，技术长廊
[20] Christopher Saint and Judy Saint, 集成电路版图设计(影印版), 清华大学出版社，2004
[21] Robert A. Pease, "A New Production Technique for Trimming Voltage Regulators", National Semiconductor, Linear Brief 46, July 1979
[22] 袁文师，吴建辉，基准电压源设计．半导体技术，第29卷第4期，91-94
[23] 拉扎维．毕查德，模拟CMOS集成电路设计[M]。西安：西安交通大学出版社，2003：309-319
[24] 程晓洁，冯全源，一种低功耗高可靠性的过流保护电路设计，微电子学与计算机，2006年第23卷第1期
[25] 石国韬，蒋国平，“一种高稳定低功耗CMOS过热保护电路的设计”，电子器件，第29卷第2期，2006年6月
[26] R. H. Charles and D. A. Hodges, "Charge Circuits for Analog LSI,"IEEE Trans. Circuits Syst, Vol. CAS-25, No.7, pp.490-497, July 1978
[27] X. Hu and K. W. Martin, "A Switched-Current Sample-and-Hold Circuit," IEEE J. Solid-State Circuits, Vol.32, N0.6, pp.898-904, Jan. 1997
[28] I. Mehr and T. L Sculley, "A 16-bit Current Sample/Hold Circuit Using a Digital CMOS Process," Proceedings of the IEEE International Symposium on Circuits and Systems, pp.5.417-5.420, 1994
[29] S. A Trotter, Introduction to Discrete-Time Signal Processing, New York: Wiley, 1976
[30] J. Doernberg, H. S. Lee, and D. A. Hodges, "Full-Speed Testing of A/D Converters," IEEE J. Solid-State Circuits, Vol.SC-19, No.6, pp.820o827, Dec. 1984
[31] [美]John．P．Uyemure著，周润德 译。超大规模集成电路与系统导论[D]．北京：电子工业出版社，2004
[32] [美]Christopher Saint／Judy Saint著，周润德，金申美译。集成电路掩模 设计—基础版图技术．北京：清华大学出版社
[33] LANDA PHAM，“选择LDO的方法”，今日电子，2004年第2期
[34] Texas Instruments, TPS71719 datasheet, "Low Noise, High-Bandwidth PSRR Low-Dropout 150mA Linear Regulator", 2006-2007