摘要
MPEG-2编码是一种成熟而复杂的技术,它是利用图像信号的统计特性及人类视觉的生理学及心理学特性对图像高效编码的。MPEG-2标准只给出了框架准则,其具体实现方案由开发人员确定。本文编码器采用Fujitsu公司的MPEG-2编码芯片MB86390用硬件来实现视频信号的压缩,编成MPEG-2码流,可应用于DVD、数字电视、DVB-C及视频的网络传输等。本文重点阐述了MPEG-2标准的视频压缩编原理和编码器的设计及调试两部分。
视频压缩原理部分介绍了视频序列的相邻帧之间的“相似”而存在大量的时间冗余度,帧内各相邻象素的“相似”而存在大量的空间冗余度。通过使用DPCM、DCT和Huffman编码去除了时间、空间及统计冗余度,从而实现了视频的压缩。
编码器的设计中,模拟/电源块主要实现的功能是对输入的模拟视频信号进行A/D转换,解码芯片采用Philips公司SAA7113。编码块实现了视频的MPEG-2压缩编码,芯片MB86390是编码块的核心,FPGA主要作系统控制用,辅助MB86390完成编码过程。编码器的调试主要包括SAA7113的I~2C总线配置、MB86390初始化配置数据的串口下载、FPGA控制程序的模块化设计及时序仿真。
The technology of MPEG-2 (Moving Picture Experts Group) coding is mature and complicated Which realizes encoding for picture by taking advantage of statistical character of picture signal and human vision character in physiology and psychology. The rules of framework are provided for by MPEG-2 standard, but devisers can decide on the detailed schemes. Using the MPEG-2 encoding chip MB86390 made in Fujitsu, This coder can reduce the video signal with hardware and encode it into MPEG-2 bit stream. It has application in DVD and HTDV and DVB-C and video transmission in network, etc. Two parts the principle of video reduced on MPEG-2 standard and the designing of encoder and debugging on encoder are primarily expatiated on in this dissertation.
What the part of the principle of video reduced narrates mainly is that there is plentiful temporal redundancy between adjacent frames in a video sequence for their "Similarity" and there is a lot of spatial redundancy in each pixel within a frame for their "Similarity", the video is compressed by reducing spatial and temporal and statistical redundancy with the technology of DPCM and DCT and Huffman encoding.
On designing of the encoder, by using the decoding for video chip SAA7113 made in Philips, analog video signal inputted realizes A/D conversion in analog/power block. Digital video is compressed to bit stream in encoder block, Chip MB86390 is kernel in this block, FPGA is used to controlling and it assists MB86390 to encode. The part of debugging the encoder describes mainly SAA7113 being configured by I~2C bus and MB86390 being configured by downloading from serial interface and designing of FPGA blocking program and emulating the timing order.
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