基于MPEG-2的视频编码器的研制
摘要
MPEG-2编码是一种成熟而复杂的技术，它是利用图像信号的统计特性及人类视觉的生理学及心理学特性对图像高效编码的。MPEG-2标准只给出了框架准则，其具体实现方案由开发人员确定。本文编码器采用Fujitsu公司的MPEG-2编码芯片MB86390用硬件来实现视频信号的压缩，编成MPEG-2码流，可应用于DVD、数字电视、DVB-C及视频的网络传输等。本文重点阐述了MPEG-2标准的视频压缩编原理和编码器的设计及调试两部分。
视频压缩原理部分介绍了视频序列的相邻帧之间的“相似”而存在大量的时间冗余度，帧内各相邻象素的“相似”而存在大量的空间冗余度。通过使用DPCM、DCT和Huffman编码去除了时间、空间及统计冗余度，从而实现了视频的压缩。
编码器的设计中，模拟/电源块主要实现的功能是对输入的模拟视频信号进行A/D转换，解码芯片采用Philips公司SAA7113。编码块实现了视频的MPEG-2压缩编码，芯片MB86390是编码块的核心，FPGA主要作系统控制用，辅助MB86390完成编码过程。编码器的调试主要包括SAA7113的I~2C总线配置、MB86390初始化配置数据的串口下载、FPGA控制程序的模块化设计及时序仿真。
The technology of MPEG-2 (Moving Picture Experts Group) coding is mature and complicated Which realizes encoding for picture by taking advantage of statistical character of picture signal and human vision character in physiology and psychology. The rules of framework are provided for by MPEG-2 standard, but devisers can decide on the detailed schemes. Using the MPEG-2 encoding chip MB86390 made in Fujitsu, This coder can reduce the video signal with hardware and encode it into MPEG-2 bit stream. It has application in DVD and HTDV and DVB-C and video transmission in network, etc. Two parts the principle of video reduced on MPEG-2 standard and the designing of encoder and debugging on encoder are primarily expatiated on in this dissertation.
What the part of the principle of video reduced narrates mainly is that there is plentiful temporal redundancy between adjacent frames in a video sequence for their "Similarity" and there is a lot of spatial redundancy in each pixel within a frame for their "Similarity", the video is compressed by reducing spatial and temporal and statistical redundancy with the technology of DPCM and DCT and Huffman encoding.
On designing of the encoder, by using the decoding for video chip SAA7113 made in Philips, analog video signal inputted realizes A/D conversion in analog/power block. Digital video is compressed to bit stream in encoder block, Chip MB86390 is kernel in this block, FPGA is used to controlling and it assists MB86390 to encode. The part of debugging the encoder describes mainly SAA7113 being configured by I~2C bus and MB86390 being configured by downloading from serial interface and designing of FPGA blocking program and emulating the timing order.
视频压缩原理部分介绍了视频序列的相邻帧之间的“相似”而存在大量的时间冗余度，帧内各相邻象素的“相似”而存在大量的空间冗余度。通过使用DPCM、DCT和Huffman编码去除了时间、空间及统计冗余度，从而实现了视频的压缩。
编码器的设计中，模拟/电源块主要实现的功能是对输入的模拟视频信号进行A/D转换，解码芯片采用Philips公司SAA7113。编码块实现了视频的MPEG-2压缩编码，芯片MB86390是编码块的核心，FPGA主要作系统控制用，辅助MB86390完成编码过程。编码器的调试主要包括SAA7113的I~2C总线配置、MB86390初始化配置数据的串口下载、FPGA控制程序的模块化设计及时序仿真。
The technology of MPEG-2 (Moving Picture Experts Group) coding is mature and complicated Which realizes encoding for picture by taking advantage of statistical character of picture signal and human vision character in physiology and psychology. The rules of framework are provided for by MPEG-2 standard, but devisers can decide on the detailed schemes. Using the MPEG-2 encoding chip MB86390 made in Fujitsu, This coder can reduce the video signal with hardware and encode it into MPEG-2 bit stream. It has application in DVD and HTDV and DVB-C and video transmission in network, etc. Two parts the principle of video reduced on MPEG-2 standard and the designing of encoder and debugging on encoder are primarily expatiated on in this dissertation.
What the part of the principle of video reduced narrates mainly is that there is plentiful temporal redundancy between adjacent frames in a video sequence for their "Similarity" and there is a lot of spatial redundancy in each pixel within a frame for their "Similarity", the video is compressed by reducing spatial and temporal and statistical redundancy with the technology of DPCM and DCT and Huffman encoding.
On designing of the encoder, by using the decoding for video chip SAA7113 made in Philips, analog video signal inputted realizes A/D conversion in analog/power block. Digital video is compressed to bit stream in encoder block, Chip MB86390 is kernel in this block, FPGA is used to controlling and it assists MB86390 to encode. The part of debugging the encoder describes mainly SAA7113 being configured by I~2C bus and MB86390 being configured by downloading from serial interface and designing of FPGA blocking program and emulating the timing order.
引文
[1] 阮秋琦，数字图像处理学，电子工业出版社，2001；
[2] 钟玉琢 乔秉新 祁卫 等译，运动图像及其伴音通用编码国际标准－MPEG-2，清华大学出版社，1996；
[3] 文富忠 徐定杰等, MPEG的发展动态及其未来预测，电子技术应用，2002年09期；
[4] 姚丰 罗向阳 陈常娟，MPEG-2数字图像、声音编码与传输技术，广东通信技术，1996年第4期；
[5] 骆立俊 皱采荣 何振亚，一种用于MPEG2运动估计的八步搜索算法，信号处理，1998年第14卷第12期；
[6] 陶林，图像变换编码技术，电视技术，1998年第8期；
[7] 骆立俊 皱采荣 高西奇 何振亚，视频编码中的块运动估计算法，电视技术，1997年第6期；
[8] 张春田，视频信号压缩编码，广播与电视技术，1995年第2期；
[9] 袁云，MPEG-2视频压缩技术及其应用，中国数据通信，2002第5期；
[10] 孙玉霞，数字电视图像信号的正交变换编码，常州技术师范学院学报，2000第6卷第2期；
[11] 周凌华，一种视频信号压缩编码方法的研究，通讯技术，1998年第1期；
[12] 李军 叶玮 黄天 余松煜 ，mpeg-2传送层语法结构及传送复用器实现技术 ，电视技术，1998第3期；
[13] 陈维强 高文 ，mpeg-2视频编码的运动估计与实现，自动化学报，1998年05期；
[14] 王建松 俞斯乐 ，mpeg-2数字压缩视频的转换编码及其应用，通信技术，1998年第4期；
[15] 黎洪松，数字视频技术及其应用，清华大学出版社，1997；
[16] 毕厚杰，多媒体信息的传输与处理，人民邮电出版社，1999；
[17] 彭明全，有线电视技术教程，电子工业出版社，1999；
[18] 张锟生，彩色电视原理，东南大学出版社，1999；
[19] 何立民，I~2C总线应用系统设计，北京航空航天大学出版社，1995；
[20] 宋万杰 罗丰 吴顺君，CPLD技术及其应用，西安电子科技大学出版社，1999；
[21] 侯伯亨 顾新 VHDL硬件描述语言与数字逻辑电路设计，西安电子科技大学出版社，1997；
[22] ISO/IEC 13818-2(MPEG2DIS)，Coding of moving picture and associated audio，1995；
[23] T.Koya, K.Iinuma, AHirano, Y.Iiyima, and T.Ishi-guro, "Motion-compensated inter-frame coding for video conferencing".in Proc. NTC81,New Orleans, LA, pp. C9.6.1-9.6.5, Nov.1981；
[24] S.kappagantula and K.R.Rao, "Motion compensated inter-frame image prediction". IEEET rans.Commun.,vol.COM-33,pp.1011-1015,Sept,1985；
[25] J.R.Jain and A.K.Jain, "Displacement meaasurement and its application in inter-frame image cod-ing".IEEET rans.Commun.vol.COM-29,pp.1799-1808, Dec, 1981；
[26] Ghanbari,"The cross-search algorithm for motion estimattion," IEEET rans.Commun., vol.38, no.7, pp.950-953, July 1990；
[27] W.Lee, J.F.Wang, J.Y.Lee, and J.D.Shie. "Dynamic search-window adjustment and interlaced search for block-matching algorithm".IEEET rans.CASVT.vol.3,pp.85-87,Feb,1993；
[28] HEWLETT PACKARD, MPEG-2:The basics of how if works；
[29] PHILIPS Data sheet, SAA7113H 9-bit video input process 1999 JUL 01;[]
[30] FUJITSU Data Sheet, MPEG-2 1chip audio/video encoder MB86390A Product specification, Revision 1.4 06,September 2000;
[31] FUJITSU Data Sheet, MB86390A parameter specification, revision 2.2 12,December 2000;
[32] FUJITSU Data Sheet, MB86390 control protocol command specification, revision 1.7, 25 February, 1999;
[33] FUJITSU Data Sheet, MPEG-2 codec module (MB86390-RB-SA1) Hardware specification;
[34] FUJITSU Data Sheet, MB86390_RB_SA1_V010e.pdf;
[35] ALTERA Data Sheet, MAX+PLUSII Programmable logic development system & software, January 1998, ver.8;
[36] ALTERA Data Sheet, Configuration devices for APEX & FLEX devices, November 1999, ver.10.03
[37] IDT Data sheet, fast COMS buffer/driver IDT49FCT3805/A, October 1998;
[38] IDT Data sheet, 3.3V low skew pll-based CMOS clock driver (with 3 state) IDT74FCT388915T August 1998;
[39] FUJITSU semiconductor data sheet, memory CMOS 4×512 K ×32 bit synchronous dynamic ram MB81F643242B;
[40] FUJITSU semiconductor data sheet, flash memory CMOS 8M bit MBM29LV800BA;
[2] 钟玉琢 乔秉新 祁卫 等译，运动图像及其伴音通用编码国际标准－MPEG-2，清华大学出版社，1996；
[3] 文富忠 徐定杰等, MPEG的发展动态及其未来预测，电子技术应用，2002年09期；
[4] 姚丰 罗向阳 陈常娟，MPEG-2数字图像、声音编码与传输技术，广东通信技术，1996年第4期；
[5] 骆立俊 皱采荣 何振亚，一种用于MPEG2运动估计的八步搜索算法，信号处理，1998年第14卷第12期；
[6] 陶林，图像变换编码技术，电视技术，1998年第8期；
[7] 骆立俊 皱采荣 高西奇 何振亚，视频编码中的块运动估计算法，电视技术，1997年第6期；
[8] 张春田，视频信号压缩编码，广播与电视技术，1995年第2期；
[9] 袁云，MPEG-2视频压缩技术及其应用，中国数据通信，2002第5期；
[10] 孙玉霞，数字电视图像信号的正交变换编码，常州技术师范学院学报，2000第6卷第2期；
[11] 周凌华，一种视频信号压缩编码方法的研究，通讯技术，1998年第1期；
[12] 李军 叶玮 黄天 余松煜 ，mpeg-2传送层语法结构及传送复用器实现技术 ，电视技术，1998第3期；
[13] 陈维强 高文 ，mpeg-2视频编码的运动估计与实现，自动化学报，1998年05期；
[14] 王建松 俞斯乐 ，mpeg-2数字压缩视频的转换编码及其应用，通信技术，1998年第4期；
[15] 黎洪松，数字视频技术及其应用，清华大学出版社，1997；
[16] 毕厚杰，多媒体信息的传输与处理，人民邮电出版社，1999；
[17] 彭明全，有线电视技术教程，电子工业出版社，1999；
[18] 张锟生，彩色电视原理，东南大学出版社，1999；
[19] 何立民，I~2C总线应用系统设计，北京航空航天大学出版社，1995；
[20] 宋万杰 罗丰 吴顺君，CPLD技术及其应用，西安电子科技大学出版社，1999；
[21] 侯伯亨 顾新 VHDL硬件描述语言与数字逻辑电路设计，西安电子科技大学出版社，1997；
[22] ISO/IEC 13818-2(MPEG2DIS)，Coding of moving picture and associated audio，1995；
[23] T.Koya, K.Iinuma, AHirano, Y.Iiyima, and T.Ishi-guro, "Motion-compensated inter-frame coding for video conferencing".in Proc. NTC81,New Orleans, LA, pp. C9.6.1-9.6.5, Nov.1981；
[24] S.kappagantula and K.R.Rao, "Motion compensated inter-frame image prediction". IEEET rans.Commun.,vol.COM-33,pp.1011-1015,Sept,1985；
[25] J.R.Jain and A.K.Jain, "Displacement meaasurement and its application in inter-frame image cod-ing".IEEET rans.Commun.vol.COM-29,pp.1799-1808, Dec, 1981；
[26] Ghanbari,"The cross-search algorithm for motion estimattion," IEEET rans.Commun., vol.38, no.7, pp.950-953, July 1990；
[27] W.Lee, J.F.Wang, J.Y.Lee, and J.D.Shie. "Dynamic search-window adjustment and interlaced search for block-matching algorithm".IEEET rans.CASVT.vol.3,pp.85-87,Feb,1993；
[28] HEWLETT PACKARD, MPEG-2:The basics of how if works；
[29] PHILIPS Data sheet, SAA7113H 9-bit video input process 1999 JUL 01;[]
[30] FUJITSU Data Sheet, MPEG-2 1chip audio/video encoder MB86390A Product specification, Revision 1.4 06,September 2000;
[31] FUJITSU Data Sheet, MB86390A parameter specification, revision 2.2 12,December 2000;
[32] FUJITSU Data Sheet, MB86390 control protocol command specification, revision 1.7, 25 February, 1999;
[33] FUJITSU Data Sheet, MPEG-2 codec module (MB86390-RB-SA1) Hardware specification;
[34] FUJITSU Data Sheet, MB86390_RB_SA1_V010e.pdf;
[35] ALTERA Data Sheet, MAX+PLUSII Programmable logic development system & software, January 1998, ver.8;
[36] ALTERA Data Sheet, Configuration devices for APEX & FLEX devices, November 1999, ver.10.03
[37] IDT Data sheet, fast COMS buffer/driver IDT49FCT3805/A, October 1998;
[38] IDT Data sheet, 3.3V low skew pll-based CMOS clock driver (with 3 state) IDT74FCT388915T August 1998;
[39] FUJITSU semiconductor data sheet, memory CMOS 4×512 K ×32 bit synchronous dynamic ram MB81F643242B;
[40] FUJITSU semiconductor data sheet, flash memory CMOS 8M bit MBM29LV800BA;