高速宽带连续型Sigma Delta调制器的研究与设计
|
摘要
Sigma Delta调制器使用过采样技术与量化噪声整形相结合的方法,使高精度ADC的设计成为可能。而在对信号带宽要求较高的领域,如无线通讯等,离散型Sigma Delta调制器的设计变得更为困难。而连续时间架构降低了对各模块设计指标的需求,从而广泛地应用于兆赫信号带宽的低功耗ADC设计中。
本文首先介绍了Sigma Delta调制器的基本原理,着重分析了离散时间与连续时间Sigma Delta调制器之间的区别;针对兆赫信号带宽高速ADC设计,完成了系统级设计与分析以及电路级实现。在系统级设计方面,主要工作包括:在理论分析的基础上,选择三阶一位量化连续时间Sigma Delta调制器架构;在离散域进行调制器的建模,主要包括噪声传递函数的设计与优化、离散域Simulink建模与仿真,然后采用脉冲恒定变换原理将离散域环路方程变换至连续域,并重点分析了由变换所引入的DAC非理想因素;依据对环路滤波器非理想因素的分析,定义各模块的设计指标。在电路实现方面,调制器的放大器电路采用低压共源共栅偏置、增益提高技术与连续时间共模反馈相结合的结构以实现低功耗、高增益和宽带宽;比较器电路采用增加额外正反馈的方法,在降低比较器功耗的同时,提高了比较的速度;最后对调制器进行仿真分析,各项指标满足设计要求,并进行了版图设计与验证。
本文的设计采用SMIC 0.18μm CMOS工艺,在Cadence环境下,对各模块电路及调制器整体电路进行仿真分析。结果显示,在输入信号幅度为0.5 V,频率分别为500 KHz及1.5 MHz两种情况下,后端仿真SNR分别达到68.7 dB及68.6 dB,有效位分别达到11.13 bits及11.11 bits,功耗仅为1.8 mW。这表明,本文设计的调制器在兆赫信号带宽领域达到较高水平。
Sigma Delta modulators make the design of high resolution Analog-to-Digital Converter (ADC) feasible by employing the oversampling technology combined with quantization noise shaping methodology. The design of Discrete-Time (DT) Sigma Delta modulator becomes more and more difficult when regarding the fields that high requirements of signal bandwidth are needed, such as wireless communication. However, the Continuous-Time (CT) architectures decrease the demands of block specifications and are widely used in the realizations of low power Mega Hz signal bandwidth ADC.
The basic principles of Sigma Delta modulator are introduced in this design firstly, focusing on the analysis of the difference between DT and CT Sigma Delta filters; for the high speed ADC design in Mega Hz signal bandwidth, the system level design and analysis are completed, also the implementation of circuit level design. At the system level design, the main work includes: Based on the theoretical analysis, a three-order single-bit CT Sigma Delta architecture is adopted and modeled in discrete domain, including the design and optimization of the Noise-Transfer-Function (NTF), modeling and simulate in Simulink; then, the loop function is converted to continuous domain by using the theory of Impulse-Invariant-Transform (IIT), and the Digital-to-Analog Converter (DAC) nonidealities introduced by the transformation are illustrated; the specifications of each blocks are defined thanks to the discuss of the loop filter nonidealities. In the circuit implementation, the low-voltage cascade bias circuit, gain-boosting technology and CT common-mode feedback (CMFB) are presented in the amplifier design of the modulator to realize low power consumption and wide bandwidth; meanwhile, extra positive feedback is introduced in the comparator circuit, which increases the speed of comparison, decreases the power consumption at the same time; finally, the simulation results and analysis are put forward, which show that the requirements are met well, and then the layout design and verification are carried out.
The implementation is designed in SMIC 0.18μm CMOS process, the module circuits and the top modulator are simulated and analyzed under the Cadence environment. The simulation result of post-layout shows that 68.7 dB and 68.6 dB signal-to-noise ratio (SNR), 11.13 bits and 11.11 bits of effective number of bits (ENOB) are achieved respectively, with the input signal frequency of 500 KHz and 1.5 MHz, when the amplitude is 0.5 V. Consuming only 1.8 mW, the proposed Sigma Delta modulator reaches a high level in the field of Mega Hz signal bandwidth.
本文首先介绍了Sigma Delta调制器的基本原理,着重分析了离散时间与连续时间Sigma Delta调制器之间的区别;针对兆赫信号带宽高速ADC设计,完成了系统级设计与分析以及电路级实现。在系统级设计方面,主要工作包括:在理论分析的基础上,选择三阶一位量化连续时间Sigma Delta调制器架构;在离散域进行调制器的建模,主要包括噪声传递函数的设计与优化、离散域Simulink建模与仿真,然后采用脉冲恒定变换原理将离散域环路方程变换至连续域,并重点分析了由变换所引入的DAC非理想因素;依据对环路滤波器非理想因素的分析,定义各模块的设计指标。在电路实现方面,调制器的放大器电路采用低压共源共栅偏置、增益提高技术与连续时间共模反馈相结合的结构以实现低功耗、高增益和宽带宽;比较器电路采用增加额外正反馈的方法,在降低比较器功耗的同时,提高了比较的速度;最后对调制器进行仿真分析,各项指标满足设计要求,并进行了版图设计与验证。
本文的设计采用SMIC 0.18μm CMOS工艺,在Cadence环境下,对各模块电路及调制器整体电路进行仿真分析。结果显示,在输入信号幅度为0.5 V,频率分别为500 KHz及1.5 MHz两种情况下,后端仿真SNR分别达到68.7 dB及68.6 dB,有效位分别达到11.13 bits及11.11 bits,功耗仅为1.8 mW。这表明,本文设计的调制器在兆赫信号带宽领域达到较高水平。
Sigma Delta modulators make the design of high resolution Analog-to-Digital Converter (ADC) feasible by employing the oversampling technology combined with quantization noise shaping methodology. The design of Discrete-Time (DT) Sigma Delta modulator becomes more and more difficult when regarding the fields that high requirements of signal bandwidth are needed, such as wireless communication. However, the Continuous-Time (CT) architectures decrease the demands of block specifications and are widely used in the realizations of low power Mega Hz signal bandwidth ADC.
The basic principles of Sigma Delta modulator are introduced in this design firstly, focusing on the analysis of the difference between DT and CT Sigma Delta filters; for the high speed ADC design in Mega Hz signal bandwidth, the system level design and analysis are completed, also the implementation of circuit level design. At the system level design, the main work includes: Based on the theoretical analysis, a three-order single-bit CT Sigma Delta architecture is adopted and modeled in discrete domain, including the design and optimization of the Noise-Transfer-Function (NTF), modeling and simulate in Simulink; then, the loop function is converted to continuous domain by using the theory of Impulse-Invariant-Transform (IIT), and the Digital-to-Analog Converter (DAC) nonidealities introduced by the transformation are illustrated; the specifications of each blocks are defined thanks to the discuss of the loop filter nonidealities. In the circuit implementation, the low-voltage cascade bias circuit, gain-boosting technology and CT common-mode feedback (CMFB) are presented in the amplifier design of the modulator to realize low power consumption and wide bandwidth; meanwhile, extra positive feedback is introduced in the comparator circuit, which increases the speed of comparison, decreases the power consumption at the same time; finally, the simulation results and analysis are put forward, which show that the requirements are met well, and then the layout design and verification are carried out.
The implementation is designed in SMIC 0.18μm CMOS process, the module circuits and the top modulator are simulated and analyzed under the Cadence environment. The simulation result of post-layout shows that 68.7 dB and 68.6 dB signal-to-noise ratio (SNR), 11.13 bits and 11.11 bits of effective number of bits (ENOB) are achieved respectively, with the input signal frequency of 500 KHz and 1.5 MHz, when the amplitude is 0.5 V. Consuming only 1.8 mW, the proposed Sigma Delta modulator reaches a high level in the field of Mega Hz signal bandwidth.
引文
[1] Raf Schoofs, Michiel Steyaert, Willy Sansen. A 1GHz Continuous-Time Sigma-Delta A/D Converter in 90 nm Standard CMOS. in: Microwave Symposium Digest, IEEE MTT-S International. Long Beach, USA: IEEE MIT-S’05, 2005. 1287-1290
[2] M. Ortmanns F. Gerfers. Continuous-Time Sigma-Delta A/D Conversion: Fundamentals, Performance Limits and Robust Implementations. New York: Springer Press, 2005. 185-222
[3] Phillip E. Allen, Douglas R Holberg. CMOS模拟集成电路设计.第二版.冯军,李智群译.北京:电子工业出版社, 2005. 533-582
[4] H. Inose, Y. Yasuda, J. Murikami. A Telemetering System by Code Modulation–Σ? Modulation. IRE Trans. Space Electron. Telemetry. 1962, 8(9): 204-209
[5] J. C. Candy. A Use of Double Integration in Sigma-Delta Modulation. IEEE Trans. Commun. 1985, 33(7): 249-258
[6] H. Nosaka, M. Nakamura, M. Ida, et al. A 24-Gsps 3-bit Nyquist ADC using InP HBTs for Electronic Dispersion Compensation. IEEE MTT-S Digest, 2004, 1(6): 101-104
[7] Balasubramanian Sivakumar, Shankar Thirunakkarasu. Current Pumping and Voltage Pulling to Maximize Speed: An Application to A 2.5 Gsps Flash ADC in 350 nm Standard CMOS Process. in: IEEE International Conference on Advanced Computer Theory and Engineering. Phuket, Thailand: IEEE ICACTE, 2008. 1100-1103
[8] Khaled A. Shehata, Hanady Hussein, Hani F. Ragai. Design and Implementation of 2.5 Gbps Pipeline Digital Encoder for Flash A/D Converters. in: IEEE International Conference on Signals,Circuits and Systems. Nabeul, Tunisia: IEEE ICSCS, 2008. 1-5
[9] Adam Hart, Sorin Voinigescu. A 1 GHz Bandwidth Low-PassΔΣADC with 20-50 GHz Adjustable Sampling Rate. IEEE Journal of Solid-State Circuits, 2009, 44(5): 1401-1414
[10] G. Mitteregger, Christian Ebner. A 20-mW 640-MHz CMOS Continuous-Time ADC With 20-MHz Signal Bandwidth, 80-dB Dynamic Range and 12-bit ENOB. IEEE Journal of Solid-State Circuits, 2006, 41(12): 2642-2649
[11] L. Dorrer, F. Kuttner, P. Greco, et al. A 3-mW 74-dB SNR 2-MHz Continuous-Time Delta-Sigma ADC with a Tracking ADC Quantizer in 0.13-μm CMOS. IEEE Journal of Solid-State Circuits, 2005, 40(12): 2416-2427
[12] L. Dorrer, F. Kuttner, A. Wiesbauer, et al. A 10-Bit, 3 mW Continuous-Time Sigma-Delta ADC for UMTS in a 0.12μm CMOS Process. in: Proc. Eur. Solid-State Circuits Conf. Estoril, Portugal: ESSCIRC’03, 2003. 245-248
[13] K. Philips, P. Nuijten, R. Roovers, et al. A Continuous-TimeΣ? ADC with Increased Immunity to Interferers. IEEE Journal of Solid-State Circuits, 2004, 39(12): 2170-2178
[14] Tongyu Song, Shouli Yan. A Low Power 1.1 MHz CMOS Continuous-Time Delta- Sigma Modulator with Active-Passive Loop Filters. IEEE Journal of Solid-State Circuits, 2008, 43(2): 4423-4426
[15] Zhiming Li, Terri S. Fiez. A 14 Bit Continuous-Time Delta-Sigma A/D Modulator with 2.5 MHz Signal Bandwidth. IEEE Journal of Solid-State Circuits, 2007, 42(9): 1873-1883
[16] Shouli Yan, Edgar Sanchez-Sinencio. A Continuous-TimeΣ? Modulator with 88-dB Dynamic Range and 1.1-MHz Signal Bandwidth. IEEE Journal of Solid-State Circuits, 2004, 39(1): 75-86
[17] Maurits Ortmanns, Friedel Gerfers, Yiannos Manoli. A Case Study on a 2-1-1 Cascaded Continuous-Time Sigma-Delta Modulator. IEEE Transactions on Circuits and Systems-Ⅰ, 2005, 52(8): 1515-1525
[18] Richard Schreier, Gabor C. Temes. Understanding Delta-Sigma Data Converters. Wilmington: Wiley-IEEE Press, 2005. 410-415
[19] Richard Schreier. An Empirical Study of High-Order Single-Bit Delta-Sigma Modulators. IEEE Transactions on Circuits and Systems-Ⅱ: Analog and Digital Signal Processing, 1993, 40(8): 461-466
[20]冯晖.具有高性能的高阶Sigma Delta A/D转换器研究: [博士学位论文].上海:上海交通大学图书馆, 2006
[21] D.W. Cline. Noise, Speed and Power Trade-Offs in Pipelined Analog to Digital Converters: [PhD Thesis]. Berkeley: University of California at Berkeley, 1995
[22] Shahriar. Rabii, Bruce A. Wooley. The Design of Low-Voltage Low-Power Sigma-Delta Modulators. Dordrecht: Springer Publisher, 1999. 176-193
[23] W. Bennett. Spectra of Quantized Signals. Bell System Technical Journal, 1948. 27(3): 446-472
[24] S. Northworthy, R. Schreier, G. Temes. Delta-Sigma Data Converters. Piscataway: IEEE Press, 1997.141-192
[25] B. Widrow. A Study of Rough Amplitude Quantization by means of Nyquist Sampling Theory. IRE Trans. Circuit Theory, 1956, 3(2): 266-276
[26] T. L. Brooks, D. H. Robertson, D.F. Kelly, et al. A Cascaded Sigma-Delta Pipeline A/D Converter with 1.25MHz Signal Bandwidth and 89 dB SNR. IEEE Journal of Solid-State Circuits, 1997, 32(12): 1896-1906
[27] Cheongyuen William Tsang. Digitally Calibrated Analog-to-Digital Converters in Deep Sub-micron CMOS: [PhD Thesis]. Berkeley: University of California, 2008
[28] R. Adams. Design and Implementation of an Audio 18-bit Analog-to-Digital Converter using Oversampling Techniques. Journal of the Audio Engineering Society. 1986, 34(3): 153-166
[29] Y. Geerts, M. Steyaert, W. Sansen. Design of Multi-Bit Delta-Sigma A/D Converters. Dordrecht: Kluwer Academic Publisher, 2002. 104-139
[30] M.W. Hauser, R.W. Brodersen. Circuit and Technology Considerations for MOS Delta-Sigma A/D Converters. in: Proc. IEEE Int. Symp. Circuits Syst. San Jose, USA: IEEE ISCAS, 1986. 1310-1315
[31] F. Medeiro, B. Perez-Verdu, A. Rodriguez-Vazquez. Top-Down Design of High-Performance Sigma-Delta Modulators. Dordrecht: Kluwer Academic Publisher, 1999. 235-267
[32] P. Kiss, Un-Ku Moon, J. Steensgaard, et al. MultibitΣ? ADC with Mixed-Mode DAC Error Correction. in: Proc. IEEE Int. Symp. Circuits Syst. Sydney, Australia: IEEE ISCAS’01, 2001. 280-283
[33] R. T. Baird, T. S. Fiez. A Low Oversampling Ratio 14-Bit 500-KHzΣ? ADC with a Self-Calibrated Multibit DAC. IEEE Journal of Solid-State Circuits, 1996, 31(3): 312-320
[34] F. Gerfers, M. Ortmanns, Y. Manoli. A 12-Bit Power Efficient Continuous-TimeΣ? Modulator with 220μW Power Consumption. in: Proc. Eur. Solid-State Circuits Conf. Hague, Netherlands: ESSCIRC’01, 2001.536-539
[35] J. A. Cherry, W. M. Snelgrove. Continuous-Time Delta-Sigma Modulators for High-Speed A/D Conversion. Dordrecht: Kluwer Academic Publisher, 1999. 98-134
[36] E. J. Van der Zwan, E. C. Dijkmans. A 0.2-mW CMOSΣ? Modulator for Speech Coding with 80 dB Dynamic Range. IEEE Journal of Solid-State Circuits, 1996, 31(12): 1873-1880
[37] T. Burger, Q. Huang. A 13.5-mW 185-M Sample/sΣ? Modulator for UMTS/GSM Dual-Standard IF Reception. IEEE Journal of Solid-State Circuits, 2001, 36(12): 1868-1878
[38] V. Peluso, P. Vancorenland, A. Marques, et al. A 900-mV Low-PowerΣ? A/D Converter with 77- dB Dynamic Range. IEEE Journal of Solid-State Circuits, 1998, 33(12): 1887-1897
[39] Richard Schreier. An Empirical Study of High-Order Single-Bit Delta-SigmaModulators. IEEE Transactions on Circuits and Systems-Ⅱ: Analog and Digital Signal Processing, 1993, 40(8): 461-466
[40] O. Oliaei, H. Aboushady. Jitter Effects in Continuous TimeΣ? Modulators with Delayed Return-to-Zero Feedback. in: Proc. Int. Conf. Electron. Circuits Syst. Lisbon, Portugal: IEEE ICECS, 1998. 351-354
[41] M. Ortmanns, F. Gerfers, Y. Manoli. Jitter Insensitive Feedback DAC for Continuous-TimeΣ? Modulators. in: Proc. IEEE Int. Conf. Electron. Circuits Syst. Valletta, Malta: IEEE ICECS, 2001. 1049-1052
[42] J. A. Cherry, W. M. Snelgrove. Loop Delay and Jitter in Continuous-Time Delta Sigma Modulators. in: Proc. IEEE Int. Symp. Circuits Syst. Monterey, USA: IEEE ISCAS’98, 1998. 596-599
[43] L. Risbo.Σ? Modulators-Stability and Design Optimization: [PhD Thesis]. Copenhagen: Technical University of Denmark, 1994
[44] R. J. Van de Plassche. A Sigma-Delta Modulator as an A/D Converter. IEEE Trans. Circuits Syst, 1978, 25(7): 510-514
[45] J. A. Cherry, W. M. Snelgrove. Excess Loop Delay in Continuous-Time Delta-Sigma Modulators. IEEE Trans. Circuits Syst.-II, 1999, 46(4): 376-389
[46] B. E. Boser, B. A. Wooley. The Design of Sigma-Delta Modulation Analog-to-Digital Converters. IEEE Journal of Solid-State Circuits, 1988, 23(6): 1298-1308
[47] P. F. Ferguson, A. Ganesan, R. W. Adams. One Bit Higher Order Sigma Delta A/D Converters. in: Proc. IEEE Int. Symp. Circuits Syst. New Orleans, USA: IEEE ISCAS’90, 1990. 890-893
[48] M. Ortmanns, F. Gerfers, Y. Manoli. Compensation of Finite Gain Bandwidth Induced Errors in Continuous-Time Sigma-Delta Modulators. IEEE Trans. Circuits Syst.-II, 2004, 51(6): 1088-1100
[49] M. Rebeschini, N. van Bavel, P. Rakers, et al. A 16-B 160-KHz CMOS A/DConverter using Sigma-Delta Modulation. IEEE Journal of Solid-State Circuits, 1990, 25(2): 431-440
[50] J. Silva-Martinez, M. Steyaert, W. M. Sansen. High-Performance CMOS Continuous-Time Filters. Dordrecht: Kluwer Academic Publisher, 1993. 84-113
[51] K. Chao, S. Nadeem, W. L. Lee, et al. A Higher Order Topology for Interpolative Modulators for Oversampleed A/D Converters. IEEE Trans. Circuits Syst, 1990, 37(3): 309-318
[52] J. H. Tao, J. M. Khoury. A 400-Ms/s Frequency Translating Bandpass Sigma-Delta Modulator. IEEE Journal of Solid-State Circuits, 1999, 34(12): 1741-1752
[53] B. Xia, S. Yan, E. Sanchez-Sinencio. An RC Time Constant Auto-Tuning Structure for High Linearity Continuous-timeΣ? Modulators and Active Filters. IEEE Trans. Circuits Syst.-I, 2004, 51(11): 2179-2188
[54] M. Ortmanns, F. Gerfers, Y. Manoli. Successful Design of Cascaded Continuous-TimeΣ? Modulators. in: Proc. IEEE Int. Conf. Electron. Circuits Syst. Valletta, Malta: IEEE ICECS, 2001. 321-324
[55] R. Gregorian, G. C. Temes. Analog MOS Integrated Circuits for Signal Processing. New York : John Wiley & Sons Press, 1995. 346-428
[56] N. Wongkomet. A Comparison of Continuous-Time and Discrete-Time Sigma-Delta Modulators: [Master Thesis]. Berkeley: University of California at Berkeley, 1995
[57] A. Marques, V. Peluso, M. Steyaert, et al. Optimal Parameters forΣ? Modulator Topologies. IEEE Trans. Circuits Syst.- II, 1998, 45(9): 1232-1241
[58] Alan Hastings. The Art of ANALOG LAYOUT. New Jersey: Prentice-Hall, 2001. 156-395
[59] L. Dorre, F. Kunttner, P. Greco, et al. A 3-mW 74-dB SNR 2-MHz Continuous-Time Delta-Sigma ADC With a Tracking ADC Quantizer in 0.13-μm CMOS. IEEE Journal of Solid-State Circuits, 2005, 40(12): 2416-2427
[60] F. Gerfers, M. Ortmanns, Y. Manoli. A 1 V, 12-Bit Wideband Continuous-TimeΣ?Modulator for UMTS Applications. Proceedings-IEEE International Symposium on Circuits and Systems, 2003, 1(5): 921-924
[2] M. Ortmanns F. Gerfers. Continuous-Time Sigma-Delta A/D Conversion: Fundamentals, Performance Limits and Robust Implementations. New York: Springer Press, 2005. 185-222
[3] Phillip E. Allen, Douglas R Holberg. CMOS模拟集成电路设计.第二版.冯军,李智群译.北京:电子工业出版社, 2005. 533-582
[4] H. Inose, Y. Yasuda, J. Murikami. A Telemetering System by Code Modulation–Σ? Modulation. IRE Trans. Space Electron. Telemetry. 1962, 8(9): 204-209
[5] J. C. Candy. A Use of Double Integration in Sigma-Delta Modulation. IEEE Trans. Commun. 1985, 33(7): 249-258
[6] H. Nosaka, M. Nakamura, M. Ida, et al. A 24-Gsps 3-bit Nyquist ADC using InP HBTs for Electronic Dispersion Compensation. IEEE MTT-S Digest, 2004, 1(6): 101-104
[7] Balasubramanian Sivakumar, Shankar Thirunakkarasu. Current Pumping and Voltage Pulling to Maximize Speed: An Application to A 2.5 Gsps Flash ADC in 350 nm Standard CMOS Process. in: IEEE International Conference on Advanced Computer Theory and Engineering. Phuket, Thailand: IEEE ICACTE, 2008. 1100-1103
[8] Khaled A. Shehata, Hanady Hussein, Hani F. Ragai. Design and Implementation of 2.5 Gbps Pipeline Digital Encoder for Flash A/D Converters. in: IEEE International Conference on Signals,Circuits and Systems. Nabeul, Tunisia: IEEE ICSCS, 2008. 1-5
[9] Adam Hart, Sorin Voinigescu. A 1 GHz Bandwidth Low-PassΔΣADC with 20-50 GHz Adjustable Sampling Rate. IEEE Journal of Solid-State Circuits, 2009, 44(5): 1401-1414
[10] G. Mitteregger, Christian Ebner. A 20-mW 640-MHz CMOS Continuous-Time ADC With 20-MHz Signal Bandwidth, 80-dB Dynamic Range and 12-bit ENOB. IEEE Journal of Solid-State Circuits, 2006, 41(12): 2642-2649
[11] L. Dorrer, F. Kuttner, P. Greco, et al. A 3-mW 74-dB SNR 2-MHz Continuous-Time Delta-Sigma ADC with a Tracking ADC Quantizer in 0.13-μm CMOS. IEEE Journal of Solid-State Circuits, 2005, 40(12): 2416-2427
[12] L. Dorrer, F. Kuttner, A. Wiesbauer, et al. A 10-Bit, 3 mW Continuous-Time Sigma-Delta ADC for UMTS in a 0.12μm CMOS Process. in: Proc. Eur. Solid-State Circuits Conf. Estoril, Portugal: ESSCIRC’03, 2003. 245-248
[13] K. Philips, P. Nuijten, R. Roovers, et al. A Continuous-TimeΣ? ADC with Increased Immunity to Interferers. IEEE Journal of Solid-State Circuits, 2004, 39(12): 2170-2178
[14] Tongyu Song, Shouli Yan. A Low Power 1.1 MHz CMOS Continuous-Time Delta- Sigma Modulator with Active-Passive Loop Filters. IEEE Journal of Solid-State Circuits, 2008, 43(2): 4423-4426
[15] Zhiming Li, Terri S. Fiez. A 14 Bit Continuous-Time Delta-Sigma A/D Modulator with 2.5 MHz Signal Bandwidth. IEEE Journal of Solid-State Circuits, 2007, 42(9): 1873-1883
[16] Shouli Yan, Edgar Sanchez-Sinencio. A Continuous-TimeΣ? Modulator with 88-dB Dynamic Range and 1.1-MHz Signal Bandwidth. IEEE Journal of Solid-State Circuits, 2004, 39(1): 75-86
[17] Maurits Ortmanns, Friedel Gerfers, Yiannos Manoli. A Case Study on a 2-1-1 Cascaded Continuous-Time Sigma-Delta Modulator. IEEE Transactions on Circuits and Systems-Ⅰ, 2005, 52(8): 1515-1525
[18] Richard Schreier, Gabor C. Temes. Understanding Delta-Sigma Data Converters. Wilmington: Wiley-IEEE Press, 2005. 410-415
[19] Richard Schreier. An Empirical Study of High-Order Single-Bit Delta-Sigma Modulators. IEEE Transactions on Circuits and Systems-Ⅱ: Analog and Digital Signal Processing, 1993, 40(8): 461-466
[20]冯晖.具有高性能的高阶Sigma Delta A/D转换器研究: [博士学位论文].上海:上海交通大学图书馆, 2006
[21] D.W. Cline. Noise, Speed and Power Trade-Offs in Pipelined Analog to Digital Converters: [PhD Thesis]. Berkeley: University of California at Berkeley, 1995
[22] Shahriar. Rabii, Bruce A. Wooley. The Design of Low-Voltage Low-Power Sigma-Delta Modulators. Dordrecht: Springer Publisher, 1999. 176-193
[23] W. Bennett. Spectra of Quantized Signals. Bell System Technical Journal, 1948. 27(3): 446-472
[24] S. Northworthy, R. Schreier, G. Temes. Delta-Sigma Data Converters. Piscataway: IEEE Press, 1997.141-192
[25] B. Widrow. A Study of Rough Amplitude Quantization by means of Nyquist Sampling Theory. IRE Trans. Circuit Theory, 1956, 3(2): 266-276
[26] T. L. Brooks, D. H. Robertson, D.F. Kelly, et al. A Cascaded Sigma-Delta Pipeline A/D Converter with 1.25MHz Signal Bandwidth and 89 dB SNR. IEEE Journal of Solid-State Circuits, 1997, 32(12): 1896-1906
[27] Cheongyuen William Tsang. Digitally Calibrated Analog-to-Digital Converters in Deep Sub-micron CMOS: [PhD Thesis]. Berkeley: University of California, 2008
[28] R. Adams. Design and Implementation of an Audio 18-bit Analog-to-Digital Converter using Oversampling Techniques. Journal of the Audio Engineering Society. 1986, 34(3): 153-166
[29] Y. Geerts, M. Steyaert, W. Sansen. Design of Multi-Bit Delta-Sigma A/D Converters. Dordrecht: Kluwer Academic Publisher, 2002. 104-139
[30] M.W. Hauser, R.W. Brodersen. Circuit and Technology Considerations for MOS Delta-Sigma A/D Converters. in: Proc. IEEE Int. Symp. Circuits Syst. San Jose, USA: IEEE ISCAS, 1986. 1310-1315
[31] F. Medeiro, B. Perez-Verdu, A. Rodriguez-Vazquez. Top-Down Design of High-Performance Sigma-Delta Modulators. Dordrecht: Kluwer Academic Publisher, 1999. 235-267
[32] P. Kiss, Un-Ku Moon, J. Steensgaard, et al. MultibitΣ? ADC with Mixed-Mode DAC Error Correction. in: Proc. IEEE Int. Symp. Circuits Syst. Sydney, Australia: IEEE ISCAS’01, 2001. 280-283
[33] R. T. Baird, T. S. Fiez. A Low Oversampling Ratio 14-Bit 500-KHzΣ? ADC with a Self-Calibrated Multibit DAC. IEEE Journal of Solid-State Circuits, 1996, 31(3): 312-320
[34] F. Gerfers, M. Ortmanns, Y. Manoli. A 12-Bit Power Efficient Continuous-TimeΣ? Modulator with 220μW Power Consumption. in: Proc. Eur. Solid-State Circuits Conf. Hague, Netherlands: ESSCIRC’01, 2001.536-539
[35] J. A. Cherry, W. M. Snelgrove. Continuous-Time Delta-Sigma Modulators for High-Speed A/D Conversion. Dordrecht: Kluwer Academic Publisher, 1999. 98-134
[36] E. J. Van der Zwan, E. C. Dijkmans. A 0.2-mW CMOSΣ? Modulator for Speech Coding with 80 dB Dynamic Range. IEEE Journal of Solid-State Circuits, 1996, 31(12): 1873-1880
[37] T. Burger, Q. Huang. A 13.5-mW 185-M Sample/sΣ? Modulator for UMTS/GSM Dual-Standard IF Reception. IEEE Journal of Solid-State Circuits, 2001, 36(12): 1868-1878
[38] V. Peluso, P. Vancorenland, A. Marques, et al. A 900-mV Low-PowerΣ? A/D Converter with 77- dB Dynamic Range. IEEE Journal of Solid-State Circuits, 1998, 33(12): 1887-1897
[39] Richard Schreier. An Empirical Study of High-Order Single-Bit Delta-SigmaModulators. IEEE Transactions on Circuits and Systems-Ⅱ: Analog and Digital Signal Processing, 1993, 40(8): 461-466
[40] O. Oliaei, H. Aboushady. Jitter Effects in Continuous TimeΣ? Modulators with Delayed Return-to-Zero Feedback. in: Proc. Int. Conf. Electron. Circuits Syst. Lisbon, Portugal: IEEE ICECS, 1998. 351-354
[41] M. Ortmanns, F. Gerfers, Y. Manoli. Jitter Insensitive Feedback DAC for Continuous-TimeΣ? Modulators. in: Proc. IEEE Int. Conf. Electron. Circuits Syst. Valletta, Malta: IEEE ICECS, 2001. 1049-1052
[42] J. A. Cherry, W. M. Snelgrove. Loop Delay and Jitter in Continuous-Time Delta Sigma Modulators. in: Proc. IEEE Int. Symp. Circuits Syst. Monterey, USA: IEEE ISCAS’98, 1998. 596-599
[43] L. Risbo.Σ? Modulators-Stability and Design Optimization: [PhD Thesis]. Copenhagen: Technical University of Denmark, 1994
[44] R. J. Van de Plassche. A Sigma-Delta Modulator as an A/D Converter. IEEE Trans. Circuits Syst, 1978, 25(7): 510-514
[45] J. A. Cherry, W. M. Snelgrove. Excess Loop Delay in Continuous-Time Delta-Sigma Modulators. IEEE Trans. Circuits Syst.-II, 1999, 46(4): 376-389
[46] B. E. Boser, B. A. Wooley. The Design of Sigma-Delta Modulation Analog-to-Digital Converters. IEEE Journal of Solid-State Circuits, 1988, 23(6): 1298-1308
[47] P. F. Ferguson, A. Ganesan, R. W. Adams. One Bit Higher Order Sigma Delta A/D Converters. in: Proc. IEEE Int. Symp. Circuits Syst. New Orleans, USA: IEEE ISCAS’90, 1990. 890-893
[48] M. Ortmanns, F. Gerfers, Y. Manoli. Compensation of Finite Gain Bandwidth Induced Errors in Continuous-Time Sigma-Delta Modulators. IEEE Trans. Circuits Syst.-II, 2004, 51(6): 1088-1100
[49] M. Rebeschini, N. van Bavel, P. Rakers, et al. A 16-B 160-KHz CMOS A/DConverter using Sigma-Delta Modulation. IEEE Journal of Solid-State Circuits, 1990, 25(2): 431-440
[50] J. Silva-Martinez, M. Steyaert, W. M. Sansen. High-Performance CMOS Continuous-Time Filters. Dordrecht: Kluwer Academic Publisher, 1993. 84-113
[51] K. Chao, S. Nadeem, W. L. Lee, et al. A Higher Order Topology for Interpolative Modulators for Oversampleed A/D Converters. IEEE Trans. Circuits Syst, 1990, 37(3): 309-318
[52] J. H. Tao, J. M. Khoury. A 400-Ms/s Frequency Translating Bandpass Sigma-Delta Modulator. IEEE Journal of Solid-State Circuits, 1999, 34(12): 1741-1752
[53] B. Xia, S. Yan, E. Sanchez-Sinencio. An RC Time Constant Auto-Tuning Structure for High Linearity Continuous-timeΣ? Modulators and Active Filters. IEEE Trans. Circuits Syst.-I, 2004, 51(11): 2179-2188
[54] M. Ortmanns, F. Gerfers, Y. Manoli. Successful Design of Cascaded Continuous-TimeΣ? Modulators. in: Proc. IEEE Int. Conf. Electron. Circuits Syst. Valletta, Malta: IEEE ICECS, 2001. 321-324
[55] R. Gregorian, G. C. Temes. Analog MOS Integrated Circuits for Signal Processing. New York : John Wiley & Sons Press, 1995. 346-428
[56] N. Wongkomet. A Comparison of Continuous-Time and Discrete-Time Sigma-Delta Modulators: [Master Thesis]. Berkeley: University of California at Berkeley, 1995
[57] A. Marques, V. Peluso, M. Steyaert, et al. Optimal Parameters forΣ? Modulator Topologies. IEEE Trans. Circuits Syst.- II, 1998, 45(9): 1232-1241
[58] Alan Hastings. The Art of ANALOG LAYOUT. New Jersey: Prentice-Hall, 2001. 156-395
[59] L. Dorre, F. Kunttner, P. Greco, et al. A 3-mW 74-dB SNR 2-MHz Continuous-Time Delta-Sigma ADC With a Tracking ADC Quantizer in 0.13-μm CMOS. IEEE Journal of Solid-State Circuits, 2005, 40(12): 2416-2427
[60] F. Gerfers, M. Ortmanns, Y. Manoli. A 1 V, 12-Bit Wideband Continuous-TimeΣ?Modulator for UMTS Applications. Proceedings-IEEE International Symposium on Circuits and Systems, 2003, 1(5): 921-924