应用于无线通讯中的12位连续时间Sigma-Delta ADC设计
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摘要
随着无线通讯技术的发展,人们将更多的注意力转向连续时间Sigma-Delta模数转换器。连续时间结构的Sigma-Delta调制器相对于离散时间结构的Sigma-Delta调制器,具有结构精简,尺寸小,功耗低,速度高,带宽宽等特性,特别适合应用于通讯系统,是目前国内外模数转换器的研究热点之一。本文基于chart0.35μm CMOS工艺设计了一个应用于无线通讯系统中的12位低通连续时间Sigma-Delta ADC,带宽1.92MHz。
连续时间Sigma-Delta ADC共分为两部分,调制器和数字滤波器。本文中调制器采用了单环三阶连续时间结构,根据系统信噪比和功耗考虑,过采样率选为16,这样在达到系统信噪比前提下,功耗较低,同时过采样率选为2的指数幂,也可以降低数字滤波器设计难度。在调制器电路实现方面,本文设计了一种高增益低噪声两级运算放大器,有效减小了运算放大器非理想性对积分器的影响。为了减小反馈DAC对系统的影响,本文特别设计了一种采用模拟校正与数字加权平均混合优化方法的反馈DAC,有效地提高了系统信噪比。同时本文还设计了一种预放大锁存的比较器构成Flash ADC型量化器,在保持较大频率的同时,减小系统功耗。本文中的数字滤波器采用了三级级联的方式,减小数字滤波器硬件消耗。降频滤波器采用了积分梳状级联(CIC)滤波器、半带滤波器和补偿滤波器级联实现。最后对滤波器进行了行为级仿真,仿真表明,降频滤波器能达到78dB信噪比和1.92MHz带宽要求。
With the development of the wireless communication, people pay more and more attention to the continuous Sigma-Delta analog to digital conversion. Compared with the discrete time Sigma-Delta modulator, the continuous time Sigma-Delta modulator has the character of simple structure, small size, low power dissipation, wide bandwidth. It is very suit for the communication system and it is very popular in the research of analog to digital conversion. This paper presented a 12 bit continuous time Sigma-Delta analog to digital conversion for wireless communication bashed on chart 0.35μm CMOS process, and the ADC’s bandwidth is 1.92MHz.
The continuous time Sigma-Delta ADC is consist of modulator and decimation. The continuous time modulator in this paper was adopted single loop third order structure. The over sampling ratio (OSR) was choose 16 because of the signal and noise ratio (SNR) and power dissipation. And it choose the OSR 16 can ease the difficulty of design of the decimation. In the schematic of modulator, this paper gives a high gain and low noise two-stage Opamps. The high gain and low noise Opamps can alleviate the nonideal of integrator. This paper presented a feedback DAC which was adopted analog error cancellation and digital weigh average, specially. The feedback DAC improved SNR of the modulator. And this paper presented a Flash ADC composed of pre-amplify and latch comparator. The Flash ADC can work in high clock frequency with low power dissipation. The decimation in this paper was adopted the three order cascade structure for reducing the power dissipation of the decimation. Based the theory of decimation, the decimation was implemented by cascaded of CIC filter, half band filter and compensate filter. Lastly, simulation of decimation showed that it can achieve 78dB SNR and 1.92MHz bandwidth.
连续时间Sigma-Delta ADC共分为两部分,调制器和数字滤波器。本文中调制器采用了单环三阶连续时间结构,根据系统信噪比和功耗考虑,过采样率选为16,这样在达到系统信噪比前提下,功耗较低,同时过采样率选为2的指数幂,也可以降低数字滤波器设计难度。在调制器电路实现方面,本文设计了一种高增益低噪声两级运算放大器,有效减小了运算放大器非理想性对积分器的影响。为了减小反馈DAC对系统的影响,本文特别设计了一种采用模拟校正与数字加权平均混合优化方法的反馈DAC,有效地提高了系统信噪比。同时本文还设计了一种预放大锁存的比较器构成Flash ADC型量化器,在保持较大频率的同时,减小系统功耗。本文中的数字滤波器采用了三级级联的方式,减小数字滤波器硬件消耗。降频滤波器采用了积分梳状级联(CIC)滤波器、半带滤波器和补偿滤波器级联实现。最后对滤波器进行了行为级仿真,仿真表明,降频滤波器能达到78dB信噪比和1.92MHz带宽要求。
With the development of the wireless communication, people pay more and more attention to the continuous Sigma-Delta analog to digital conversion. Compared with the discrete time Sigma-Delta modulator, the continuous time Sigma-Delta modulator has the character of simple structure, small size, low power dissipation, wide bandwidth. It is very suit for the communication system and it is very popular in the research of analog to digital conversion. This paper presented a 12 bit continuous time Sigma-Delta analog to digital conversion for wireless communication bashed on chart 0.35μm CMOS process, and the ADC’s bandwidth is 1.92MHz.
The continuous time Sigma-Delta ADC is consist of modulator and decimation. The continuous time modulator in this paper was adopted single loop third order structure. The over sampling ratio (OSR) was choose 16 because of the signal and noise ratio (SNR) and power dissipation. And it choose the OSR 16 can ease the difficulty of design of the decimation. In the schematic of modulator, this paper gives a high gain and low noise two-stage Opamps. The high gain and low noise Opamps can alleviate the nonideal of integrator. This paper presented a feedback DAC which was adopted analog error cancellation and digital weigh average, specially. The feedback DAC improved SNR of the modulator. And this paper presented a Flash ADC composed of pre-amplify and latch comparator. The Flash ADC can work in high clock frequency with low power dissipation. The decimation in this paper was adopted the three order cascade structure for reducing the power dissipation of the decimation. Based the theory of decimation, the decimation was implemented by cascaded of CIC filter, half band filter and compensate filter. Lastly, simulation of decimation showed that it can achieve 78dB SNR and 1.92MHz bandwidth.
引文
1 J.C. Candy. A Use of Double Integration in Sigma-Delta Modulation. IEEE Trans Communication. 1985(33): 249-258
2 Asad A. Abidi. RF CMOS Comes of Age. IEEE J. of solid-state circuits. 2004, 39(4):549~561
3 Behzad Razavi. CMOS Technology Characterization for Analog and RF Design. IEEE J. of solid-state circuits. 1999,34(3):268~276
4 Thomas H. Lee. The Design of CMOS Radio-Frequency Integrated Circuits. Second Edition. Cambridge University Press. 2004: 41~85
5 EricJ.vanderZwan, E.CarelDijkmans. A 2mW CMOSΣ? Modulator for speech Coding with 80dB Dynamic Range. IEEE Jounal of solid-State Circuits,1996, 31(12):1~6
6 R. H. M. Vanldhoven, B. J. Minnis, H. Hegt. A 33mwΣ? Modulator for UMTS in 0.18μm CMOS With 70 dB Dynamic Range in 2 MHz Bandwidth,IEEE Jounal of solid-State Circuits,2002,37(12)
7 R. H. M. Vanveldhoven. A Triple-Mode Continuous-time Modulator with switched-Capacitor Feedback DAC for a GSM-EDGE/CDMA2000/UMTS Receiver, IEEE Journal of Solid-State Circuits,2003,38(12) Circuits
8 Cherry, J.A., Snelgrove, W.M., Gao, W.: On the Design of a Fourth-Order Continuous-Time LC delta-sigma Modulator for UHF A/D Conversion. IEEE J. Solid-State Circuits. 1998,33(5),: 723–732
9 Schreier, R., Lloyd, J. Singer, L., Paterson etc. A 50mW bandpassΣ? ADC with 333 kHz BW and 90 dB Dynamic Range. Proc. IEEE Int. Solid-State Circuits Conf. 2002:216–217
10 Gao, W., Snelgrove, W.M. A 950-MHz IF Second-Order Integrated LC bandpass delta-sigma modulator. IEEE J. Solid-State Circuits 1998,33(5): 128–132
11 K. Philips. A 4.4mW, 76dB Complex Sigma-Delta ADC for a Low-Cost Bluetooth receiver. ISSCC 2003 in press.
12 Susana Patón, etc. A 70-mW 300-MHz CMOS Continuous-Time ADC With
15-MHz Bandwidth and 11 Bits of Resolution. IEEE Journal of Solid-stateCircuits. 2004,39(7).1056-1062
13 Zhimin Li. Design of a 14-bit Continuous-Time Delta-Sigma A/D Modulator with 2.5MHz Signal Bandwidth. Oregon State University, Doctor of Philosophy.2006.
14 Tao Wang, Liping Liang. Analysis and Design of a Continuous-Time Sigma-Delta Modulator with 20MHz Signal Bandwidth, 53.6dB Dynamic Range and 51.4dB SNDR. 4th IEEE International Symposium on Electronic Design, Test & Applicqtion.2008:71~79
15 G.. Ushaw, S. McLaughlin. On The Configuration of Second Order Sigma- Delta Modulator. IEEE Trans. Signal Processing 1993. 41(7).
16 M. Ortmanns, F. Gerfers, E. Manoli. Clock Jitter Insensitive Continuous- Time Sigma-Delta Modulator. IEEE Trans on Circuits and Systems II. 2001:1049~1052
17 L. Hernandez, S. Pafon. Continuous Time Sigma-Delta modulators with transmission line resonators and improved jitter and excess loop delay performance. IEEE Trans. on Circuits and Systems II. 2003:989~992
18 L. Hernández, etc. Modeling and Optimization of Low Pass Continuous-Time Sigma-Delta Modulators for Clock Jitter Noise Reduction. IEEE ISCAS. 2004:1072~1075
19 L. Hernández,etc. A Jitter Insensitive Continuous-Time Sigma-Delta Modulator Using Transmission Lines. ISCAS 2003:109~112
20 Konsrantinos Doris, Arthur van Roermund. A General Analysis on the Timing Jitter in D/A Conversion. ISCAS 2002:117~120
21 Yong-In Park, etc. A 16-Bit, 5MHz Multi-Bit Sigma-Delta ADC Using Adaptively Randomized DWA. IEEE 2003 Custom Integrated Circuits Conference. 2003:115~118
22 M. Keller, Y. Manoli, F. Gerfers. A Calibration Method for Current Steering Digital to Analog Converters in Continuous Time Multi-bit Sigma-Delta Modulators. ISCAS 2004:289~292
23 M. Ortmanns, F. Gerfers, Y. Manoli. A Continuous-Time Sigma-Delta Modulator with Switched Capacitor Controlled Current Mode Feedback. IEEE Trans. on Circuit and System-II. 2003: 679~682
24 F. Colodro, etc. New Approach for Continuous Time Sigma Delta Modulators.IEEE Trans. on Circuit and System-II. 2003:929~932
25 L. Samid, Y. Manoli. A Multibit Continuous Time Sigma Delta Modulator with Successive-Approximation Quantizer ISCAS 2006: 2965~2968
26 V. A. Bharadwaj. Continuous Time Sigma Delta Modulator Employing a Novel Comparator Architecture. 20th international Conference on VLSI Design, 2007: 2798~2801
27高速模拟/数字转换器首次采用连续时间Sigma-Delta技术.电子设计技术. 2008
28邬蓉.一个适用于UMTS系统的五阶连续时间Sigma-Delta调制器设计.复旦大学硕士论文. 2006:8~12
29 Shouli Yan. Baseband Continuous Time Sigma-Delta analog to Digital Conversion for ADSL Applications, PhD thesis, Texas A&M University, 2002
30 M. Ortmanns. Continuous Time Delta Sigma AD Converter. Springer publishing company, June,2005:63~70,28~29
31 B.E. Boser, B.A.Wooley. The design of Sigma-Delta Modulator Analog to Digital Converter. IEEE J.solid-state Circuit. 1998,23(6): 1298-1308,
32 J. A. Cherry, W.M. Snelgrove. Continuous-time Delta-Sigma modulators for high-speed A/ D conversion. Kluwer Academic Publishers , 2000,pp30~35
33 S. Brigati, F. Francesconi, P. Malcovati, D. Tonietto, etc. Modeling Sigma-Delta Modulator non-idealities in SIMULINK. ISCAS 01. Proceedings of the 1999 International Symposium on Circuits and Systems. 1999(2):384-387
34 L. Risbo.Σ? Modulators Stability and Design Optimization. Ph.D thesis. Technical University of Denmark, 1994.
35 R. Schreier, G.. C. Temes. Understanding Delta-Sigma Data Converters. New York .John Wiley &Sons , 2005.
36 S. Lindfors, K. Halonen, M. Ismail. A 2.7 V Elliptical MOSFET only gmC OTA Filter. IEEE J. Solid-State Circuits. 1993, 28(12):1234-1245
37 J.A. Cherry, W. M. Snelgrove, W. Gao. On the Design of a Fourth-order Continuous-time LC Delta-sigma modulator for UHF A/D Conversion. IEEE J. Solid-State Circuits 1998,33(5): 723–732
38 R. Schreier, J. Lloyd, L.Singer, etc. A 50mW BandpassΣ? ADC with 333 kHz BW and 90 dB DR. Proc. IEEE Int. Solid-State Circuits Conference 2002:216–217
39 W. Gao, W.M. Snelgrove. A 950-MHz IF Second-Order Integrated LC Bandpass Delta-Sigma Modulator. IEEE J. Solid-State Circuits 1998,33(5): 723–732
40 S. Benabid, E.N. Aghdam, P. Benabes, etc. CMOS Design of a Multi-bit Bandpass Continuous-Time Sigma Delta Modulator Running at 1.2 GHz. Proc. IEEE Int. Caracas Conference. Devices,Circuits Syst.,2004: 51–55
41王金菊,Johan Haanstra等.测量系统中20位精度带通Σ-Δ调制器的设计.微电子学.2008,第38卷(1):1~5
42 Kenneth R. Laker et al. Design of Analog Integrated Circuits and Systems. McGraw-Hill, 1994.
43王珩,陈勇. Sigma-Delta ADC中数字滤波器设计.世界科技研究与发展.2007,29(1):44-47
44薛静,栾英姿. Sigma-Delta调制器的原理和降采样分析.信息技术. 2008,1(4):113-115
45郭书苞,仇玉林,叶青.一种宽带,低失真、高过载特性的Sigma-Delta模数转换器结构.电子器件. 2007,30(4):1258-1261
46李梁等.一种适合Sigma-Delta AD转换器的FIR数字滤波器.微电子学. 2006,26(3):340-343
47 S. R. Norsworthy, R. Schreier, G. C. Temes. Delta-Sigma Data Converters, Theory, Design, and Simulation. IEEE Press Marketing. 1997:476-477
48 Hogenauer E.B. An Economical Class of Digital Filters for Decimation and Interpolation. IEEE Trans. Acoust., Speech, Signal Processing. 1997, 25(3):121-126.
49易婷,方杰,洪志良. 14位1.5625MHz的Sigma-Delta AD中的降采样低通滤波器设计.固体电子学研究与进展. 2004,24(4):455-460
50冯晖,林争辉.改进的降采样速率Leslie-Singh Sigma-Delta A/D转换器.上海交通大学学报. 2003,37(10):1616-1619
2 Asad A. Abidi. RF CMOS Comes of Age. IEEE J. of solid-state circuits. 2004, 39(4):549~561
3 Behzad Razavi. CMOS Technology Characterization for Analog and RF Design. IEEE J. of solid-state circuits. 1999,34(3):268~276
4 Thomas H. Lee. The Design of CMOS Radio-Frequency Integrated Circuits. Second Edition. Cambridge University Press. 2004: 41~85
5 EricJ.vanderZwan, E.CarelDijkmans. A 2mW CMOSΣ? Modulator for speech Coding with 80dB Dynamic Range. IEEE Jounal of solid-State Circuits,1996, 31(12):1~6
6 R. H. M. Vanldhoven, B. J. Minnis, H. Hegt. A 33mwΣ? Modulator for UMTS in 0.18μm CMOS With 70 dB Dynamic Range in 2 MHz Bandwidth,IEEE Jounal of solid-State Circuits,2002,37(12)
7 R. H. M. Vanveldhoven. A Triple-Mode Continuous-time Modulator with switched-Capacitor Feedback DAC for a GSM-EDGE/CDMA2000/UMTS Receiver, IEEE Journal of Solid-State Circuits,2003,38(12) Circuits
8 Cherry, J.A., Snelgrove, W.M., Gao, W.: On the Design of a Fourth-Order Continuous-Time LC delta-sigma Modulator for UHF A/D Conversion. IEEE J. Solid-State Circuits. 1998,33(5),: 723–732
9 Schreier, R., Lloyd, J. Singer, L., Paterson etc. A 50mW bandpassΣ? ADC with 333 kHz BW and 90 dB Dynamic Range. Proc. IEEE Int. Solid-State Circuits Conf. 2002:216–217
10 Gao, W., Snelgrove, W.M. A 950-MHz IF Second-Order Integrated LC bandpass delta-sigma modulator. IEEE J. Solid-State Circuits 1998,33(5): 128–132
11 K. Philips. A 4.4mW, 76dB Complex Sigma-Delta ADC for a Low-Cost Bluetooth receiver. ISSCC 2003 in press.
12 Susana Patón, etc. A 70-mW 300-MHz CMOS Continuous-Time ADC With
15-MHz Bandwidth and 11 Bits of Resolution. IEEE Journal of Solid-stateCircuits. 2004,39(7).1056-1062
13 Zhimin Li. Design of a 14-bit Continuous-Time Delta-Sigma A/D Modulator with 2.5MHz Signal Bandwidth. Oregon State University, Doctor of Philosophy.2006.
14 Tao Wang, Liping Liang. Analysis and Design of a Continuous-Time Sigma-Delta Modulator with 20MHz Signal Bandwidth, 53.6dB Dynamic Range and 51.4dB SNDR. 4th IEEE International Symposium on Electronic Design, Test & Applicqtion.2008:71~79
15 G.. Ushaw, S. McLaughlin. On The Configuration of Second Order Sigma- Delta Modulator. IEEE Trans. Signal Processing 1993. 41(7).
16 M. Ortmanns, F. Gerfers, E. Manoli. Clock Jitter Insensitive Continuous- Time Sigma-Delta Modulator. IEEE Trans on Circuits and Systems II. 2001:1049~1052
17 L. Hernandez, S. Pafon. Continuous Time Sigma-Delta modulators with transmission line resonators and improved jitter and excess loop delay performance. IEEE Trans. on Circuits and Systems II. 2003:989~992
18 L. Hernández, etc. Modeling and Optimization of Low Pass Continuous-Time Sigma-Delta Modulators for Clock Jitter Noise Reduction. IEEE ISCAS. 2004:1072~1075
19 L. Hernández,etc. A Jitter Insensitive Continuous-Time Sigma-Delta Modulator Using Transmission Lines. ISCAS 2003:109~112
20 Konsrantinos Doris, Arthur van Roermund. A General Analysis on the Timing Jitter in D/A Conversion. ISCAS 2002:117~120
21 Yong-In Park, etc. A 16-Bit, 5MHz Multi-Bit Sigma-Delta ADC Using Adaptively Randomized DWA. IEEE 2003 Custom Integrated Circuits Conference. 2003:115~118
22 M. Keller, Y. Manoli, F. Gerfers. A Calibration Method for Current Steering Digital to Analog Converters in Continuous Time Multi-bit Sigma-Delta Modulators. ISCAS 2004:289~292
23 M. Ortmanns, F. Gerfers, Y. Manoli. A Continuous-Time Sigma-Delta Modulator with Switched Capacitor Controlled Current Mode Feedback. IEEE Trans. on Circuit and System-II. 2003: 679~682
24 F. Colodro, etc. New Approach for Continuous Time Sigma Delta Modulators.IEEE Trans. on Circuit and System-II. 2003:929~932
25 L. Samid, Y. Manoli. A Multibit Continuous Time Sigma Delta Modulator with Successive-Approximation Quantizer ISCAS 2006: 2965~2968
26 V. A. Bharadwaj. Continuous Time Sigma Delta Modulator Employing a Novel Comparator Architecture. 20th international Conference on VLSI Design, 2007: 2798~2801
27高速模拟/数字转换器首次采用连续时间Sigma-Delta技术.电子设计技术. 2008
28邬蓉.一个适用于UMTS系统的五阶连续时间Sigma-Delta调制器设计.复旦大学硕士论文. 2006:8~12
29 Shouli Yan. Baseband Continuous Time Sigma-Delta analog to Digital Conversion for ADSL Applications, PhD thesis, Texas A&M University, 2002
30 M. Ortmanns. Continuous Time Delta Sigma AD Converter. Springer publishing company, June,2005:63~70,28~29
31 B.E. Boser, B.A.Wooley. The design of Sigma-Delta Modulator Analog to Digital Converter. IEEE J.solid-state Circuit. 1998,23(6): 1298-1308,
32 J. A. Cherry, W.M. Snelgrove. Continuous-time Delta-Sigma modulators for high-speed A/ D conversion. Kluwer Academic Publishers , 2000,pp30~35
33 S. Brigati, F. Francesconi, P. Malcovati, D. Tonietto, etc. Modeling Sigma-Delta Modulator non-idealities in SIMULINK. ISCAS 01. Proceedings of the 1999 International Symposium on Circuits and Systems. 1999(2):384-387
34 L. Risbo.Σ? Modulators Stability and Design Optimization. Ph.D thesis. Technical University of Denmark, 1994.
35 R. Schreier, G.. C. Temes. Understanding Delta-Sigma Data Converters. New York .John Wiley &Sons , 2005.
36 S. Lindfors, K. Halonen, M. Ismail. A 2.7 V Elliptical MOSFET only gmC OTA Filter. IEEE J. Solid-State Circuits. 1993, 28(12):1234-1245
37 J.A. Cherry, W. M. Snelgrove, W. Gao. On the Design of a Fourth-order Continuous-time LC Delta-sigma modulator for UHF A/D Conversion. IEEE J. Solid-State Circuits 1998,33(5): 723–732
38 R. Schreier, J. Lloyd, L.Singer, etc. A 50mW BandpassΣ? ADC with 333 kHz BW and 90 dB DR. Proc. IEEE Int. Solid-State Circuits Conference 2002:216–217
39 W. Gao, W.M. Snelgrove. A 950-MHz IF Second-Order Integrated LC Bandpass Delta-Sigma Modulator. IEEE J. Solid-State Circuits 1998,33(5): 723–732
40 S. Benabid, E.N. Aghdam, P. Benabes, etc. CMOS Design of a Multi-bit Bandpass Continuous-Time Sigma Delta Modulator Running at 1.2 GHz. Proc. IEEE Int. Caracas Conference. Devices,Circuits Syst.,2004: 51–55
41王金菊,Johan Haanstra等.测量系统中20位精度带通Σ-Δ调制器的设计.微电子学.2008,第38卷(1):1~5
42 Kenneth R. Laker et al. Design of Analog Integrated Circuits and Systems. McGraw-Hill, 1994.
43王珩,陈勇. Sigma-Delta ADC中数字滤波器设计.世界科技研究与发展.2007,29(1):44-47
44薛静,栾英姿. Sigma-Delta调制器的原理和降采样分析.信息技术. 2008,1(4):113-115
45郭书苞,仇玉林,叶青.一种宽带,低失真、高过载特性的Sigma-Delta模数转换器结构.电子器件. 2007,30(4):1258-1261
46李梁等.一种适合Sigma-Delta AD转换器的FIR数字滤波器.微电子学. 2006,26(3):340-343
47 S. R. Norsworthy, R. Schreier, G. C. Temes. Delta-Sigma Data Converters, Theory, Design, and Simulation. IEEE Press Marketing. 1997:476-477
48 Hogenauer E.B. An Economical Class of Digital Filters for Decimation and Interpolation. IEEE Trans. Acoust., Speech, Signal Processing. 1997, 25(3):121-126.
49易婷,方杰,洪志良. 14位1.5625MHz的Sigma-Delta AD中的降采样低通滤波器设计.固体电子学研究与进展. 2004,24(4):455-460
50冯晖,林争辉.改进的降采样速率Leslie-Singh Sigma-Delta A/D转换器.上海交通大学学报. 2003,37(10):1616-1619