可重构电路系统设计与应用研究
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摘要
可重构技术能够使系统在运行过程中动态地重构软件和硬件系统,具有资源利用率高、功耗低、灵活性强和功能自适应等优点,在多种领域具有广泛的应用前景。目前,基于数字系统的可重构计算是可重构技术中研究的热点之一,而针对特定应用领域的可重构电路与系统设计和实现研究较少、可行性较差。
本文针对数字、模拟、生物芯片和射频通信系统等不同领域电路系统中的技术难点问题,将可重构技术应用于相关领域,提出了可重构电路与系统的设计实现方法。主要工作和创新点如下:
1.在PipeRench架构基础上,提出了一种新的流水线可重构体系结构,及基于该架构的流水线可重构系统设计方法,提高了流水线硬件的执行速度和效率;将可重构技术应用于进化硬件,提出了一种基于流水线可重构体系结构的硬件进化路由策略。该路由策略可提高硬件进化的适应和选择速度。
2.将可重构技术应用于数模混合电路设计领域,提出一种用于流水线型ADC中和输入信号相关的动态可重构Dither电路结构。该结构使得Dither的设计和加入更加灵活,不仅显著提高了ADC的动态性能,而且降低了Dither硬件资源和功耗。
3.将可重构技术应用于生物医学芯片电路设计,提出了一种低电压、超低功耗、带宽和增益可重构的生物电信号采集模拟前端电路,与适合生物电信号采集的量程可重构逐次逼近ADC。该生物电信号采集接口芯片采用1V低电压供电,功耗仅为36μW,可实现对不同生物和神经信号的自适应采集需要。
4.针对脉冲无线电超宽带通信领域,提出了一种在实际复杂的传输环境下不同天线系统传输性能的分析方法,以及在不同传输环境下天线系统的选择策略,为超宽带通信系统射频前端重构提供了一种天线系统传输性能的实时评估方法。提出了一种用于射频前端可重构的CMOS开关电路,该开关电路在超宽带工作频率高达35GHz情况下插入损耗低于1dB,隔离度高达40dB,与同类开关电路相比,具有高的性能指标。
Reconfigurable technology can realize dynamical reconfiguration of hardware and software while system works. It has such advantages as high resource utilization, low power consumption and function adaptive reconstruction, thus having an extensive application prospect in various areas. Currently, one of the hot studies on reconfigurable technology mainly focuses on the reconfigurable computation based on digital system platforms. Not many studies are found on reconfigurable circuit and system design and realization methods aiming at the special application area. Usually they are of low feasibility.
This research aims at the technological difficulties of such distinct areas as digital, analogue, biological chips and communication system. The design and implementation methods of reconfigurable circuit and system are proposed. Here are the innovative points of this research:
1. The structure of PipeRench pipelined reconfigurable system is improved, and its design method is proposed based on improved structure. It enhances the running efficiency of pipeline hardware. By applying the reconfigurable technology into evolving hardware, a routing evolving strategy of pipeline-based reconfigurable system has been proposed. It can enhance the adaption and selecting speed of hardware evolvement.
2. Apply reconfigurable technology into digital and analog mixed-circuit and propose a dynamic reconfigurable Dither circuit related to input signals. This circuit is employed in pipelined ADC and can produce Dither more flexibly. Meanwhile, it reduces Dither hardware resources and power consumption when raising SFDR of ADC significantly.
3. Apply reconfigurable technology into biomedical chip design. A front-end of low-voltage, superlow-power, bio- and neuro-signal interface whose bandwidth and gain are reconfigurable has been proposed in this research. Also, the ADC is designed for rail-to-rail operation and the input full-scale is also reconfigurable so that the resolution requirement can be relaxed. The whole interface IC consumes only 36μW from a single 1-V supply, making it suitable for a wide range of low-voltage and low-power bio- and neuro-chip platforms.
4. In the area of antenna and impulse radio UWB systems, an antenna selection strategy for different propagation environments has been proposed as well as the evaluation methods of systematic transmission performance in time domains. Moreover, an innovative CMOS switch circuit applied in configurable RF front-ends has been proposed. This switch circuit can exhibit lower than 1-dB insertion loss and higher than 40-dB isolation when working frequency reaches up to 35GHz.
本文针对数字、模拟、生物芯片和射频通信系统等不同领域电路系统中的技术难点问题,将可重构技术应用于相关领域,提出了可重构电路与系统的设计实现方法。主要工作和创新点如下:
1.在PipeRench架构基础上,提出了一种新的流水线可重构体系结构,及基于该架构的流水线可重构系统设计方法,提高了流水线硬件的执行速度和效率;将可重构技术应用于进化硬件,提出了一种基于流水线可重构体系结构的硬件进化路由策略。该路由策略可提高硬件进化的适应和选择速度。
2.将可重构技术应用于数模混合电路设计领域,提出一种用于流水线型ADC中和输入信号相关的动态可重构Dither电路结构。该结构使得Dither的设计和加入更加灵活,不仅显著提高了ADC的动态性能,而且降低了Dither硬件资源和功耗。
3.将可重构技术应用于生物医学芯片电路设计,提出了一种低电压、超低功耗、带宽和增益可重构的生物电信号采集模拟前端电路,与适合生物电信号采集的量程可重构逐次逼近ADC。该生物电信号采集接口芯片采用1V低电压供电,功耗仅为36μW,可实现对不同生物和神经信号的自适应采集需要。
4.针对脉冲无线电超宽带通信领域,提出了一种在实际复杂的传输环境下不同天线系统传输性能的分析方法,以及在不同传输环境下天线系统的选择策略,为超宽带通信系统射频前端重构提供了一种天线系统传输性能的实时评估方法。提出了一种用于射频前端可重构的CMOS开关电路,该开关电路在超宽带工作频率高达35GHz情况下插入损耗低于1dB,隔离度高达40dB,与同类开关电路相比,具有高的性能指标。
Reconfigurable technology can realize dynamical reconfiguration of hardware and software while system works. It has such advantages as high resource utilization, low power consumption and function adaptive reconstruction, thus having an extensive application prospect in various areas. Currently, one of the hot studies on reconfigurable technology mainly focuses on the reconfigurable computation based on digital system platforms. Not many studies are found on reconfigurable circuit and system design and realization methods aiming at the special application area. Usually they are of low feasibility.
This research aims at the technological difficulties of such distinct areas as digital, analogue, biological chips and communication system. The design and implementation methods of reconfigurable circuit and system are proposed. Here are the innovative points of this research:
1. The structure of PipeRench pipelined reconfigurable system is improved, and its design method is proposed based on improved structure. It enhances the running efficiency of pipeline hardware. By applying the reconfigurable technology into evolving hardware, a routing evolving strategy of pipeline-based reconfigurable system has been proposed. It can enhance the adaption and selecting speed of hardware evolvement.
2. Apply reconfigurable technology into digital and analog mixed-circuit and propose a dynamic reconfigurable Dither circuit related to input signals. This circuit is employed in pipelined ADC and can produce Dither more flexibly. Meanwhile, it reduces Dither hardware resources and power consumption when raising SFDR of ADC significantly.
3. Apply reconfigurable technology into biomedical chip design. A front-end of low-voltage, superlow-power, bio- and neuro-signal interface whose bandwidth and gain are reconfigurable has been proposed in this research. Also, the ADC is designed for rail-to-rail operation and the input full-scale is also reconfigurable so that the resolution requirement can be relaxed. The whole interface IC consumes only 36μW from a single 1-V supply, making it suitable for a wide range of low-voltage and low-power bio- and neuro-chip platforms.
4. In the area of antenna and impulse radio UWB systems, an antenna selection strategy for different propagation environments has been proposed as well as the evaluation methods of systematic transmission performance in time domains. Moreover, an innovative CMOS switch circuit applied in configurable RF front-ends has been proposed. This switch circuit can exhibit lower than 1-dB insertion loss and higher than 40-dB isolation when working frequency reaches up to 35GHz.
引文
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