一种高精度逐次逼近模数转换器的研究与设计
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摘要
数字信号具有抗干扰能力强、易于集成、功耗小、成本低的综合优势,因此越来越多的模拟信号处理逐渐被数字信号技术所取代。然而,自然界的光、热、声、电、磁等信号都是模拟量,为了使这些模拟信号能够被计算机处理,需要将这些在时间幅度上连续的模拟信号转换为离散的数字信号,模数转换器(ADC)就是实现这样功能的模块。逐次逼近(SAR)模数转换器具有中等转换速度、中等精度、低功耗和低成本的综合优势,它在便携式仪表、工业控制等领域得到了非常广泛的应用。
本论文以中速、高精度逐次逼近结构(SAR)模数转换器的分析和设计为研究方向,从逐次逼近ADC原理入手,分析比较SAR ADC的典型结构,最终确定采用分段电容阵列结构来实现该设计。由于实现高精度SAR ADC的难点在于电容、电阻之间匹配误差以及比较器固有的失调误差,所以本文重点讨论了高精度比较器的失调误差消除技术以及电容失配误差的自校准技术。
本论文基于华虹NEC 0.35 ?m工艺,设计了一个电源电压为5 V,转换精度为16位,采样率为294K SP/s的中速、高精度、全差分逐次逼近模数转换器。仿真结果表明,在输入缓慢变化的-10mV~10mV的斜坡电压信号时,输出数字码信号重建后没有遗漏码,并且DNL小于1/2LSB。在输入141kHz正弦信号时,测得整个系统的信噪失真比SNR为86dB,信噪失真比SNDR为83dB,有效位数ENOB为13.59位。
Digital signal processing has the multi advantage of strong noise tolerance ability, easy to integrate, low power consumption, low cost, so more and more signal processing uses digital signal instead of analog signal. But most of the signals in the nature are analog such as light, heat, electrical, magnetic. To process these signals in computer, we need to translate these continuous time analog signals into discrete time digital signals. Analog to digital converter (ADC) is the module to realize this function. Successive approximation register analog to digital converter is very popular in the portable instruments, industry controlling and medical instruments because it has the characteristics of medium speed, medium resolution, low power consumption and low cost.
This thesis is focus on the research and design of medium speed and high resolution successive approximation register analog to digital converter. After comparing several typical kinds of SAR ADC architecture, the segmented capacitor array architecture is used. The most challenge difficulties in high resolution SAR ADC are the capacitors and resistors mismatch and the inherent offset voltage of comparator. So the offset cancellation technique for comparator and self calibration technique for capacitor mismatch are discussed separately.
Based on the Huahong NEC 0.35 ?m technology, a 16bit, 294kSP/s fully differential successive approximation register ADC with 5V power supply is designed. The simulation results show that it has no missing code and DNL is small than 1/2LSB when -10mV to 10mV ramp signal is input. At the 141 kHz sin wave input, it achieves the signal to noise ratio (SNR) 86dB, signal to distortion and noise ratio (SNDR) 83dB and effective number of bits (ENOB) 13.59 bit.
本论文以中速、高精度逐次逼近结构(SAR)模数转换器的分析和设计为研究方向,从逐次逼近ADC原理入手,分析比较SAR ADC的典型结构,最终确定采用分段电容阵列结构来实现该设计。由于实现高精度SAR ADC的难点在于电容、电阻之间匹配误差以及比较器固有的失调误差,所以本文重点讨论了高精度比较器的失调误差消除技术以及电容失配误差的自校准技术。
本论文基于华虹NEC 0.35 ?m工艺,设计了一个电源电压为5 V,转换精度为16位,采样率为294K SP/s的中速、高精度、全差分逐次逼近模数转换器。仿真结果表明,在输入缓慢变化的-10mV~10mV的斜坡电压信号时,输出数字码信号重建后没有遗漏码,并且DNL小于1/2LSB。在输入141kHz正弦信号时,测得整个系统的信噪失真比SNR为86dB,信噪失真比SNDR为83dB,有效位数ENOB为13.59位。
Digital signal processing has the multi advantage of strong noise tolerance ability, easy to integrate, low power consumption, low cost, so more and more signal processing uses digital signal instead of analog signal. But most of the signals in the nature are analog such as light, heat, electrical, magnetic. To process these signals in computer, we need to translate these continuous time analog signals into discrete time digital signals. Analog to digital converter (ADC) is the module to realize this function. Successive approximation register analog to digital converter is very popular in the portable instruments, industry controlling and medical instruments because it has the characteristics of medium speed, medium resolution, low power consumption and low cost.
This thesis is focus on the research and design of medium speed and high resolution successive approximation register analog to digital converter. After comparing several typical kinds of SAR ADC architecture, the segmented capacitor array architecture is used. The most challenge difficulties in high resolution SAR ADC are the capacitors and resistors mismatch and the inherent offset voltage of comparator. So the offset cancellation technique for comparator and self calibration technique for capacitor mismatch are discussed separately.
Based on the Huahong NEC 0.35 ?m technology, a 16bit, 294kSP/s fully differential successive approximation register ADC with 5V power supply is designed. The simulation results show that it has no missing code and DNL is small than 1/2LSB when -10mV to 10mV ramp signal is input. At the 141 kHz sin wave input, it achieves the signal to noise ratio (SNR) 86dB, signal to distortion and noise ratio (SNDR) 83dB and effective number of bits (ENOB) 13.59 bit.
引文
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[20] TREICHLER J, HUANG Q T, BURGER T. A 10-bit ENOB 50-MS/s pipeline ADC in 130-nm CMOS at 1.2 V supply [J]. ESSCIRC 2006: Proceedings of the 32nd European Solid-State Circuits Conference, 2006, 552-555.
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[22] AGAH A, VLEUGELS K, GRIFFIN P B, et al. A high-resolution low-power oversampling ADC with extended-range for bio-sensor Arrays [J]. 2007 Symposium on VLSI Circuits, Digest of Technical Papers, 2007, 244-245.
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