超低功耗10 bit Delta-Sigma 调制器设计
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摘要
本文使用二阶单环单bit量化结构设计了一个10bit超低功耗的Delta-Sigma调制器,功耗在150uW以内。
论文首先从时域分析了Delta-Sigma调制器的基本原理,然后分析了Delta-Sigma调制器频域的传递函数,建立了频域的模型,并使用Simulink完成了建模仿真。
根据建模仿真结果和设计要求,选定了设计的总体结构,即二阶单环单bit量化结构。在此结构的基础上提出超低功耗的方案,依据此方案重点进行了差分电路、积分电路、电压比较器电路、基准源电路和锁存器电路的低功耗设计,并对各电路进行仿真和分析。
最后搭建了系统的整体电路,并完成了仿真。仿真结果显示这种低功耗组合的电路完全能够实现10bit的精度,信噪比达到80dB以上,无杂散动态范围能够达到90dB以上,而功耗仅有139uW。
This paper discusses ultra-low power consumption 10bit second order 1-bit quantization loop Delta-sigma AD (analog-to-digital) modulator. The power consumption is controlled in 150uW.
Firstly, the working principle of Delta-sigma AD modulator in time domain is illuminated in this paper, then the transfer function in frequency domain is analsized, the frequency domain mode is set up, the modeling simulation is carried out by using Simulink tool.
Secondly, the circuit structure, second order 1-bit quantization loop, is selected in this paper, the ultra-low power plan is presented, the components, operational amplifier, integrator, voltage comparator, reference and latch circuits, are designed and simulated.
Finally, the system-level circuit is proposed and simulated, the simulation results demonstrate that this low consumption can achieve 10bit accuracy, more than 80dB SNR, more than 90dB spurious free dynamic range performance. At the same time, the power consumption is only 139uW.
论文首先从时域分析了Delta-Sigma调制器的基本原理,然后分析了Delta-Sigma调制器频域的传递函数,建立了频域的模型,并使用Simulink完成了建模仿真。
根据建模仿真结果和设计要求,选定了设计的总体结构,即二阶单环单bit量化结构。在此结构的基础上提出超低功耗的方案,依据此方案重点进行了差分电路、积分电路、电压比较器电路、基准源电路和锁存器电路的低功耗设计,并对各电路进行仿真和分析。
最后搭建了系统的整体电路,并完成了仿真。仿真结果显示这种低功耗组合的电路完全能够实现10bit的精度,信噪比达到80dB以上,无杂散动态范围能够达到90dB以上,而功耗仅有139uW。
This paper discusses ultra-low power consumption 10bit second order 1-bit quantization loop Delta-sigma AD (analog-to-digital) modulator. The power consumption is controlled in 150uW.
Firstly, the working principle of Delta-sigma AD modulator in time domain is illuminated in this paper, then the transfer function in frequency domain is analsized, the frequency domain mode is set up, the modeling simulation is carried out by using Simulink tool.
Secondly, the circuit structure, second order 1-bit quantization loop, is selected in this paper, the ultra-low power plan is presented, the components, operational amplifier, integrator, voltage comparator, reference and latch circuits, are designed and simulated.
Finally, the system-level circuit is proposed and simulated, the simulation results demonstrate that this low consumption can achieve 10bit accuracy, more than 80dB SNR, more than 90dB spurious free dynamic range performance. At the same time, the power consumption is only 139uW.
引文
[1]Willy M.C. Sansen陈莹梅译.模拟集成电路设计精粹.北京.清华大学出版社.2008年3月.pp421-485
[2]贾英江,王长龙,张力.“一种1Gsps ADC电测与仪表”.2001年11期.pp50-52.
[3]方狄,林平分."10bit 60Msps 15mW流水线ADC的设计”.电子元器件应用.2009年09期.pp64-66.
[4]肖培磊,“一种10位逐次逼近ADC的设计”.[D]硕士论文,电子科技大学,2010
[5]H. Inose, Y Yasuda and J. Murakami, "A Telemetering System by Code Modulation-Delta-Sigma Modulation", IRE Traps. Space Electron.Telemetry, Sept.1962, SET-8, pp.204-209
[6]GR. Ritchie, "Higher Order Interpolation Analog to Digital Converters". [D]. Dissertation, University of Pennsylvania,1977
[7]Candy J C. "Ause of double integration in sigma——delta modulation". IEEE Trans. Common, vol. COM-33, Mar.1985. pp.249-258.
[8]T. Hayashi, Y Inabe, K Uchimura, et al, "A Multistage Delta-Sigma Modulator without Double Integration Loop". ISSCC Dig.Tech.Papers,1986, pp182-183
[9]L.E.Larson, T.Cataltepe and GC.Temes, "Multi-Bit Oversampled Sigma Delta A/D Converter with Digital Error Correction", Electron.Lett. Vol.24.1988, pp.1051-1052
[10]T.C.Leslie and B. Singh, "An Improved Sigma-Delta Modulator Architecture", Proceedings of the 1990 IEEE Int. Symp. Circuits Syst.,1990, pp372-375.
[11]R. Baird and TFiez, "Stability Analysis of High-Order Delta-Sigma Modulation for ADC's", IEEE Trans. Circuits and Systems, Vol.41, January,1994, pp59-62
[12]R. Schreier and W. M. Snelgrove, "Bandpass Sigma-Delta Modulation", Electron. Lett, vol.25. 1989, pp1560-1561.
[13]V. Peluso, M. Steyaert, W. Sansen, "Design of Low-Voltage Low-Power CMOS Delta-Sigma A/D Converters," [D]. Kluwer Academic Publishers, Boston, MA,1999
[14]E. Fogleman, I.Galton, W.Huff, H. Jensen, "A 3.3V Single Poly CMOS Audio ADC Delta-Sigma Modulator with 98dB Peak SINAD and 105dB Peak SFDR," IEEE J. Solid State Circuits, voL 35, March 2000. pp.297-307.
[15]Horrocks. D.H, "A second-Order Oversampled Sigma-Delta Modulator for Bandpass Signals", Proc. IEEE Int. Symp. Circuits Systems,1991, Vol 3, pp 1653-1656
[16]程剑平.带通∑-△调制器的研究和设计[D].博士论文.东南大学.2006.
[17]段营,戎蒙恬,刘文江.“二阶Sigma-Delta ADC自适应量化算法及电路实现”,.上海交通大学学报.2007年41卷08期.pp1374-1378
[18]陈雷.高精度∑△ADC的研究[D].博士论文.西北工业大学.2006.
[19]Simona Brigati, Fabrizio Francesconi, and Piero Malcovati. "A fourth-order single-bit switched-capacitor sigma delta modulator for distributed sensor applications ". IEEE Transactions on Instrumentation and Measurement, April,2004, Vol 53, pp266-270.
[20]吴训威.韦健CMOS电路的功耗分析及基于PSPICE模拟的功耗估计[J].浙江大学学报.2000年02期,pp212-218.
[21]Mikhail Itskovich. "Design of a Low Power Delta Sigma Modulator for Analog to Digital Conversion"[D]. Virginia Polytechnic Institute and State University.2003.
[22]Pease.Robert.”The Design of Band-Gap Reference Circuits:Trials and Tribulations" [C].IEEE 1990 Bipolar Circuits and Technology Meeting,1990. pp214-218.
[23]叶英,曾健平,马勋,朱军.“应用于∑△ADC的带隙基准源的设计”[J].半导体技术.2007年.10期,pp 882-885
[24]徐双武.基于过采样技术的∑-△音频ADC设计[D].西南交通大学,2008
[25]刘莹.∑△调制器仿真数据处理[D].北京交通大学,2008
[2]贾英江,王长龙,张力.“一种1Gsps ADC电测与仪表”.2001年11期.pp50-52.
[3]方狄,林平分."10bit 60Msps 15mW流水线ADC的设计”.电子元器件应用.2009年09期.pp64-66.
[4]肖培磊,“一种10位逐次逼近ADC的设计”.[D]硕士论文,电子科技大学,2010
[5]H. Inose, Y Yasuda and J. Murakami, "A Telemetering System by Code Modulation-Delta-Sigma Modulation", IRE Traps. Space Electron.Telemetry, Sept.1962, SET-8, pp.204-209
[6]GR. Ritchie, "Higher Order Interpolation Analog to Digital Converters". [D]. Dissertation, University of Pennsylvania,1977
[7]Candy J C. "Ause of double integration in sigma——delta modulation". IEEE Trans. Common, vol. COM-33, Mar.1985. pp.249-258.
[8]T. Hayashi, Y Inabe, K Uchimura, et al, "A Multistage Delta-Sigma Modulator without Double Integration Loop". ISSCC Dig.Tech.Papers,1986, pp182-183
[9]L.E.Larson, T.Cataltepe and GC.Temes, "Multi-Bit Oversampled Sigma Delta A/D Converter with Digital Error Correction", Electron.Lett. Vol.24.1988, pp.1051-1052
[10]T.C.Leslie and B. Singh, "An Improved Sigma-Delta Modulator Architecture", Proceedings of the 1990 IEEE Int. Symp. Circuits Syst.,1990, pp372-375.
[11]R. Baird and TFiez, "Stability Analysis of High-Order Delta-Sigma Modulation for ADC's", IEEE Trans. Circuits and Systems, Vol.41, January,1994, pp59-62
[12]R. Schreier and W. M. Snelgrove, "Bandpass Sigma-Delta Modulation", Electron. Lett, vol.25. 1989, pp1560-1561.
[13]V. Peluso, M. Steyaert, W. Sansen, "Design of Low-Voltage Low-Power CMOS Delta-Sigma A/D Converters," [D]. Kluwer Academic Publishers, Boston, MA,1999
[14]E. Fogleman, I.Galton, W.Huff, H. Jensen, "A 3.3V Single Poly CMOS Audio ADC Delta-Sigma Modulator with 98dB Peak SINAD and 105dB Peak SFDR," IEEE J. Solid State Circuits, voL 35, March 2000. pp.297-307.
[15]Horrocks. D.H, "A second-Order Oversampled Sigma-Delta Modulator for Bandpass Signals", Proc. IEEE Int. Symp. Circuits Systems,1991, Vol 3, pp 1653-1656
[16]程剑平.带通∑-△调制器的研究和设计[D].博士论文.东南大学.2006.
[17]段营,戎蒙恬,刘文江.“二阶Sigma-Delta ADC自适应量化算法及电路实现”,.上海交通大学学报.2007年41卷08期.pp1374-1378
[18]陈雷.高精度∑△ADC的研究[D].博士论文.西北工业大学.2006.
[19]Simona Brigati, Fabrizio Francesconi, and Piero Malcovati. "A fourth-order single-bit switched-capacitor sigma delta modulator for distributed sensor applications ". IEEE Transactions on Instrumentation and Measurement, April,2004, Vol 53, pp266-270.
[20]吴训威.韦健CMOS电路的功耗分析及基于PSPICE模拟的功耗估计[J].浙江大学学报.2000年02期,pp212-218.
[21]Mikhail Itskovich. "Design of a Low Power Delta Sigma Modulator for Analog to Digital Conversion"[D]. Virginia Polytechnic Institute and State University.2003.
[22]Pease.Robert.”The Design of Band-Gap Reference Circuits:Trials and Tribulations" [C].IEEE 1990 Bipolar Circuits and Technology Meeting,1990. pp214-218.
[23]叶英,曾健平,马勋,朱军.“应用于∑△ADC的带隙基准源的设计”[J].半导体技术.2007年.10期,pp 882-885
[24]徐双武.基于过采样技术的∑-△音频ADC设计[D].西南交通大学,2008
[25]刘莹.∑△调制器仿真数据处理[D].北京交通大学,2008