一种16位SAR ADC的设计
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摘要
电子系统设计已进入片上系统SOC阶段，即在单个硅片上集成各种电路功能模块，包括数字和模拟的模块，以实现完整的系统功能。模数转换器是对自然界中的物理信号进行数字化处理的入口部件，它的性能及制作方式直接影响到进行数字信号处理的物理信号的范围及其处理成本，因此ADC是一个非常重要的单元电路。在相当多的应用场合，ADC与数字部分电路常需共用同一个衬底，周围环境噪声很大，所以尽量避免转换器受到交叉干扰至关重要。此外，从成本及日益增多的可携带式设备考虑，也对模数转换器的芯片面积和功耗提出了严格的要求，同时也要求尽量不进行额外的物理修正，这些无疑都增加了ADC的设计难度。随着应用范围的拓展和对系统性能指标要求的不断提高，发展迅猛的SOC设计对高精度低功耗的ADC需求非常迫切。因而设计更高性能的ADC是一项应持续进行的重要课题。
随着半导体工艺技术的不断提高，ADC围绕着精度和速度两个方而迅速发展，出现了双积分型、闪速型、逐次逼近型、折迭插值型、二阶型、过采样型、流水线型、∑-Δ型、混合型等多种结构。不同结构的ADC的应用领域和优缺点也不完全相同，对于便携式或者电池供电的电子设备，要求比较低的供电电压和功耗，逐次逼近模数转换器具有中等转换速度和精度、小功耗、小面积特点，必然成为首选。本论文设计了一个16位的电荷重分布式逐次逼近模拟数字转换器，完成了以下工作：
1、完成ADC全部的电路设计，并采用Spectre进行电路仿真。该ADC达到的主要性能指标为：在典型的工艺条件下，可达200KSPS的吞吐率，转换精度达16bit，最大耗散功率85mW，输入范围达±10Y，片上集成时钟、2.5V基准和高速并行接口，完全达到了预期的目标。
2、基于德国某生产线的0.6um BiCMOS工艺，完成整个电路的LAYOUT，通过ERC、
With the development of circuit design coming into the SOC stage, analog and digital modules must be integrated to implement the function of system. But signals in real world generally are analog signals .Therefore, analog-to-digital converters (ADCs) become key blocks in the mixed signal system.
Different types of ADC have their own characteristics. Owning to the properties of low power consumption and a small area, the successive approximation register (SAR) ADCs are commonly used for medium-to-high resolution applications such as portable/battery powered instruments, pen digitizers and touch screen controllers. In this work, a 16 bit SAR ADC was designed.
To possess the features of fast 16 bit high resolution,- 10V～+10V input range, 100mW max power dissipation, high speed parallel interface etc, new structure of coupling capacitances was adopt to work as ADC's core module DAC,cause traditional algorithm and structure cannot get the high-precision. Some special designs were also made to realize both high-precision and low power consumption. Charge redistribution technique was employed and a 2.5V bandgap reference, accurate clock were integrated on chip. Compared with many types of reference, at last bandgap reference was used, considering to its best TC and PSRR. A buffer was arranged to follow the reference to increase the load capacity and insulate the noise from the digital circuits. To ensure the clock with the accurate frequency of 5 MHz and duty ratio of 1:1, self detector was added to the clock circuit. Through the state
随着半导体工艺技术的不断提高，ADC围绕着精度和速度两个方而迅速发展，出现了双积分型、闪速型、逐次逼近型、折迭插值型、二阶型、过采样型、流水线型、∑-Δ型、混合型等多种结构。不同结构的ADC的应用领域和优缺点也不完全相同，对于便携式或者电池供电的电子设备，要求比较低的供电电压和功耗，逐次逼近模数转换器具有中等转换速度和精度、小功耗、小面积特点，必然成为首选。本论文设计了一个16位的电荷重分布式逐次逼近模拟数字转换器，完成了以下工作：
1、完成ADC全部的电路设计，并采用Spectre进行电路仿真。该ADC达到的主要性能指标为：在典型的工艺条件下，可达200KSPS的吞吐率，转换精度达16bit，最大耗散功率85mW，输入范围达±10Y，片上集成时钟、2.5V基准和高速并行接口，完全达到了预期的目标。
2、基于德国某生产线的0.6um BiCMOS工艺，完成整个电路的LAYOUT，通过ERC、
With the development of circuit design coming into the SOC stage, analog and digital modules must be integrated to implement the function of system. But signals in real world generally are analog signals .Therefore, analog-to-digital converters (ADCs) become key blocks in the mixed signal system.
Different types of ADC have their own characteristics. Owning to the properties of low power consumption and a small area, the successive approximation register (SAR) ADCs are commonly used for medium-to-high resolution applications such as portable/battery powered instruments, pen digitizers and touch screen controllers. In this work, a 16 bit SAR ADC was designed.
To possess the features of fast 16 bit high resolution,- 10V～+10V input range, 100mW max power dissipation, high speed parallel interface etc, new structure of coupling capacitances was adopt to work as ADC's core module DAC,cause traditional algorithm and structure cannot get the high-precision. Some special designs were also made to realize both high-precision and low power consumption. Charge redistribution technique was employed and a 2.5V bandgap reference, accurate clock were integrated on chip. Compared with many types of reference, at last bandgap reference was used, considering to its best TC and PSRR. A buffer was arranged to follow the reference to increase the load capacity and insulate the noise from the digital circuits. To ensure the clock with the accurate frequency of 5 MHz and duty ratio of 1:1, self detector was added to the clock circuit. Through the state
引文
[1] Robert H. Walden, Member, IEEE, "Analog-to Digital Converter Survey and Analysis".IEEE Journal on Selected Areas in Communications,Vol.17,No.4,April 1999.pp539.
[2] 魏智．解析逐次逼近ADC．国外电子元器件．2003年第2期
[3] M. Steyaert, R.Roovers, and J.Craninckx, "A 100 MHz 8-bit CMOS Interpolating A/D Converter," IEEE Custom Integrated Circuits Conference, May 1993,pp.28.1.1-28.1.4
[4] J.van Valburg and R.J.van de Plassche,"An 8-b,650-MHz folding ADC," IEEE J.Solid-StateCircuits, Vol.27,pp. 1662-1666,Dec. 1992
[5] P. Vorenkamp and R.Roovers,"A 12b 50M sample/s cascaded folding and interpolating ADC," in IEEE ISSCC Dig.Tech.Papers,Feb. 1997,vol.40,pp.134-135.
[6] R.T.Baird and T.S.Fiez, "A Low Over sampling Radio 14-b 500-khz∑-Δ ADC with a Self-Calibrated Multibit DAC,"IEEE J.Solid-State Circuits, Vol.31, pp. 312-320, Mar.1996.
[7] Nagaraj K. A 250Mw, Sbit,52 M sample/s, Paralle pipeline A/D Converter with Reduced Number of Amplifiers. JSSC, 1997,32(3):312-320
[8] 成立，李彦旭，董素玲等．高速低压低功耗BiCMOS逻辑电路及工艺技术[J]．电子工艺技术，2002，23(1)：24—27．
[9] 高性能处理器的新动向．电子产品世界．IC与元器件．2005．5，pp108．
[10] R.H.Walden, "Analog-to-digital converter technology compadson," in IEEE GaAs IC Symp.Tech.Dig.,Oct. 1994,pp.217-219
[11] 模数转换器应用技术．高光天 主编．薛天宇，孟庆昌，华正权 编著．ADI产品应用技术从书
[12] Michiel de wit, Khen-Sang Tan, A low-power 12-b analog-to-digital converter with on-chip precision trimming. IEEE Journal of Solid-State Circuits, 1993:28 (4): 455-461.
[13] 王娜，王继安等．电荷再分配DAC级间耦合电容值的优化设计．微电子学(2006年6月发表)
[14] 隋海建．硕士毕业论文：全差分逐次逼近模拟数字转换器的设计．微电子学与固体电子学．20040401
[15] Richard K.Hester, Khen-Sang Tan, etc."Full diferential ADC with Rail-to-Rail Common Mode Range and Nonlinear Capacitor Compensation" IEEE JSSC, vol.SC-25, pp. 173-183, February 1990
[16] Behzad Razavi, Bruce A, "Design Techniques for High-Speed, High Resolution Comparators. IEEE, JSSC, vol.27.NO. 12, December 1992
[17] Gilbert Promitzer, "12-bit Low-Power Fully Diferential Switched CapacitorNoncalibrating Successiv Approximation ADC with 1 MS/s", IEEE JSSC,VOL.36,NO.7,JULY 2001
[18] Behzad Razavi. design of analog cmos integrated circuits, P 384-400.清华大学出版社 影印版
[19] I.S. Brugler. Silicon Transistor Biasing for Linear Collector Current Tempreature Dependence. IEEE J. Solid-State Circuits, Vol.SC-2,June 1967.pp.57-58
[20] Jan Verspecht. Compensation of timing jitter—induced distortion of Sampled waveforms. [J].IEEE Trans. on Instrumentation and Measurem0n, 1994, 43(10):726-732.
[21] Vostretsov A G. The effect of time jitter in sampling inside discrete systems with high-stable synchronizing clock. models and analysis [A]. Republic of Korea, 2000.106-111.
[22] 邱兆坤、王伟、黄小红、陈曾平．周边电路对模数转换器性能影响的分析．系统工程与电子技术．2005年8月，第27卷第8期
[23] Charge pump with perfect current matching characteristics in phase-locked loops, Jae-shin, Min-sun keel, Electronics Letters, 9th November 2000
[24] Programmable High Frequency RC Oscillator, Falguni Bala and Tapas Nandy, VLSID'05 IEEE
[25] Phillip E. Allen. Douglas R.Holberg.CMOS Analog Circuit Design. Publishing House of Electronics Industry.2002.6
[26] K.N.Sslama, A.M.Saliman.Novel oscillators using the operational trans-resistance amplifier, Microelectronics Journal 31(2000) 39-47
[27] Shuhuan Yu, Yiming Chen, etc.A Digital-Trim Controlled On Chip Oscillator. 0-7803-7105-X, 2001 IEEE
[28] Razavi Li, Wooley B A. Design techniques for high-speed, Higl- resolution comparators solid- state circuits [J].IEEE Journal of Solid-State Circuits, 1992, 27(12):1916-1926.
[29] James H, Atherton H, Thomas S. An offset reduction technique for use with CMOS integrated comparators and amplifiers [J]. IEEE Journal of Solid-State Circuits, 1992,27(8): 1168—1175.
[30] 李彦旭，徐立新，崔占忠，林蔚。高速ADC中CMOS比较器的改进。半导体技术第30卷第4期，2005年
[31] 带失调补偿的高性能比较器的设计 曲静然 导师：贾香鸾 20040501
[32] Siamak Mortozapour, Edward K. F. Lee, "A 1-V, 8-Bit Successive Approximation ADC in Standard CMOS Process", IEEE J. Solid-State Circuits, Vol 35, NO. 4, APRIL 2000
[33] B. Murmann and B.Boser, "A 12 bit 75MS/s pipelined ADC using open—loop residue amplification", IEEE JSSC, vol. 38, PP.2040—2050, Dec 2003
[34] Hae-Seung Lee, Davida Hodges, Paul. R.Gray. A self-calibrating 15 bit CMOS AD converter. IEEE Journal of solid-state circuit, Vol sc-19,No.6, December 1984
[35] Mahmoud Fawzy Wagdy. Correction of Capacitor Errors during the Conversion Cycle of self-calibrating A/D Converters. IEEE transaction on circuits and systems, Vol,37, No. 10, October 1990
[36] 庄弈琪主编．微电子器件应用可靠性技术．电子工业出版社 1996
[37] J.B.Shyu, G.C.Temes, and F.Krummenacher, "Random Error Effects in Mateched MOS Capacitors and Current Sources," IEEE J.Solid-State Circuits, Vol.SC-19, No.6, pp. 948-955,Dec.1984
[38] R.W.Brodersen, P.R.Gray, and D.A.Hodges, "MOS Switched-CapacitorFilter," Proc. IEEE, Vol.67,pp.61-75, Jan. 1979
[39] 吕江平．一种数模混合IC的版图设计．集成电路通讯．第22卷第2期．2004、6
[40] J.L.McCreary, P.R.Gray," All-MOS Charge Redistribution Analog-to-Digital Conbersion Techniques—Part," IEEE J.Solid-State Circuits, Vol.SC-10 No.6,pp.371-379, Dec. 1975
[41] Christopher Peter Hurrell. Analog to digital convener with a calibration circuit for compensating for coupling capacitor errors, and a method for calibrating the analog to digital convener. United States Patent US 6707403B1, Mar.16,2004.
[42] 杨之廉、申明．超大规模集成电路设计方法学导论．北京：清华大学出版社，1999．
[43] Alan Hastings, "The Art of Analog Layout", 2004 by Peason Education Asia Limited and Tsinghua University press.pp223-224
[44] A.Z.Wang, H.G.Feng.On-Chip ESD protection design for intergrated circuits:an overview for IC designers. Microelectronics Journal 32(2001).733-747.
[45] A.Z.Wang,C.Tsay, A compact square-cell ESD structure for BiCMOS IC,Proc.IEEE BCTM(1999). pp46-49.
[46] H.G.Feng,K.Gong, A.Wang, ESD Protection Design using copper interconnects: more robustness and less parasitics, SCR project report, December 1999.
[47] A.Wang, On-Chip ESD Protection for integrated Circuits—an IC Design Perspective, Kluwer Academic Publishers,Boston,2001.
[48] 王翠霞，范学峰，许维胜等．Cadence版图设计环境的建立及设计规则的验证．《现代电子技术》2004年第15期总第182期。
[49] 程未，冯勇建，杨涵．集成电路版图(1ayout)设计方法与实例[J]．现代电了技术，2003，26(3)：75-78．
[50] Cadence installation guide, Cadence company, product Version2.1 2001, Cadence design systems.Inc. Printed in the United States of America.
[2] 魏智．解析逐次逼近ADC．国外电子元器件．2003年第2期
[3] M. Steyaert, R.Roovers, and J.Craninckx, "A 100 MHz 8-bit CMOS Interpolating A/D Converter," IEEE Custom Integrated Circuits Conference, May 1993,pp.28.1.1-28.1.4
[4] J.van Valburg and R.J.van de Plassche,"An 8-b,650-MHz folding ADC," IEEE J.Solid-StateCircuits, Vol.27,pp. 1662-1666,Dec. 1992
[5] P. Vorenkamp and R.Roovers,"A 12b 50M sample/s cascaded folding and interpolating ADC," in IEEE ISSCC Dig.Tech.Papers,Feb. 1997,vol.40,pp.134-135.
[6] R.T.Baird and T.S.Fiez, "A Low Over sampling Radio 14-b 500-khz∑-Δ ADC with a Self-Calibrated Multibit DAC,"IEEE J.Solid-State Circuits, Vol.31, pp. 312-320, Mar.1996.
[7] Nagaraj K. A 250Mw, Sbit,52 M sample/s, Paralle pipeline A/D Converter with Reduced Number of Amplifiers. JSSC, 1997,32(3):312-320
[8] 成立，李彦旭，董素玲等．高速低压低功耗BiCMOS逻辑电路及工艺技术[J]．电子工艺技术，2002，23(1)：24—27．
[9] 高性能处理器的新动向．电子产品世界．IC与元器件．2005．5，pp108．
[10] R.H.Walden, "Analog-to-digital converter technology compadson," in IEEE GaAs IC Symp.Tech.Dig.,Oct. 1994,pp.217-219
[11] 模数转换器应用技术．高光天 主编．薛天宇，孟庆昌，华正权 编著．ADI产品应用技术从书
[12] Michiel de wit, Khen-Sang Tan, A low-power 12-b analog-to-digital converter with on-chip precision trimming. IEEE Journal of Solid-State Circuits, 1993:28 (4): 455-461.
[13] 王娜，王继安等．电荷再分配DAC级间耦合电容值的优化设计．微电子学(2006年6月发表)
[14] 隋海建．硕士毕业论文：全差分逐次逼近模拟数字转换器的设计．微电子学与固体电子学．20040401
[15] Richard K.Hester, Khen-Sang Tan, etc."Full diferential ADC with Rail-to-Rail Common Mode Range and Nonlinear Capacitor Compensation" IEEE JSSC, vol.SC-25, pp. 173-183, February 1990
[16] Behzad Razavi, Bruce A, "Design Techniques for High-Speed, High Resolution Comparators. IEEE, JSSC, vol.27.NO. 12, December 1992
[17] Gilbert Promitzer, "12-bit Low-Power Fully Diferential Switched CapacitorNoncalibrating Successiv Approximation ADC with 1 MS/s", IEEE JSSC,VOL.36,NO.7,JULY 2001
[18] Behzad Razavi. design of analog cmos integrated circuits, P 384-400.清华大学出版社 影印版
[19] I.S. Brugler. Silicon Transistor Biasing for Linear Collector Current Tempreature Dependence. IEEE J. Solid-State Circuits, Vol.SC-2,June 1967.pp.57-58
[20] Jan Verspecht. Compensation of timing jitter—induced distortion of Sampled waveforms. [J].IEEE Trans. on Instrumentation and Measurem0n, 1994, 43(10):726-732.
[21] Vostretsov A G. The effect of time jitter in sampling inside discrete systems with high-stable synchronizing clock. models and analysis [A]. Republic of Korea, 2000.106-111.
[22] 邱兆坤、王伟、黄小红、陈曾平．周边电路对模数转换器性能影响的分析．系统工程与电子技术．2005年8月，第27卷第8期
[23] Charge pump with perfect current matching characteristics in phase-locked loops, Jae-shin, Min-sun keel, Electronics Letters, 9th November 2000
[24] Programmable High Frequency RC Oscillator, Falguni Bala and Tapas Nandy, VLSID'05 IEEE
[25] Phillip E. Allen. Douglas R.Holberg.CMOS Analog Circuit Design. Publishing House of Electronics Industry.2002.6
[26] K.N.Sslama, A.M.Saliman.Novel oscillators using the operational trans-resistance amplifier, Microelectronics Journal 31(2000) 39-47
[27] Shuhuan Yu, Yiming Chen, etc.A Digital-Trim Controlled On Chip Oscillator. 0-7803-7105-X, 2001 IEEE
[28] Razavi Li, Wooley B A. Design techniques for high-speed, Higl- resolution comparators solid- state circuits [J].IEEE Journal of Solid-State Circuits, 1992, 27(12):1916-1926.
[29] James H, Atherton H, Thomas S. An offset reduction technique for use with CMOS integrated comparators and amplifiers [J]. IEEE Journal of Solid-State Circuits, 1992,27(8): 1168—1175.
[30] 李彦旭，徐立新，崔占忠，林蔚。高速ADC中CMOS比较器的改进。半导体技术第30卷第4期，2005年
[31] 带失调补偿的高性能比较器的设计 曲静然 导师：贾香鸾 20040501
[32] Siamak Mortozapour, Edward K. F. Lee, "A 1-V, 8-Bit Successive Approximation ADC in Standard CMOS Process", IEEE J. Solid-State Circuits, Vol 35, NO. 4, APRIL 2000
[33] B. Murmann and B.Boser, "A 12 bit 75MS/s pipelined ADC using open—loop residue amplification", IEEE JSSC, vol. 38, PP.2040—2050, Dec 2003
[34] Hae-Seung Lee, Davida Hodges, Paul. R.Gray. A self-calibrating 15 bit CMOS AD converter. IEEE Journal of solid-state circuit, Vol sc-19,No.6, December 1984
[35] Mahmoud Fawzy Wagdy. Correction of Capacitor Errors during the Conversion Cycle of self-calibrating A/D Converters. IEEE transaction on circuits and systems, Vol,37, No. 10, October 1990
[36] 庄弈琪主编．微电子器件应用可靠性技术．电子工业出版社 1996
[37] J.B.Shyu, G.C.Temes, and F.Krummenacher, "Random Error Effects in Mateched MOS Capacitors and Current Sources," IEEE J.Solid-State Circuits, Vol.SC-19, No.6, pp. 948-955,Dec.1984
[38] R.W.Brodersen, P.R.Gray, and D.A.Hodges, "MOS Switched-CapacitorFilter," Proc. IEEE, Vol.67,pp.61-75, Jan. 1979
[39] 吕江平．一种数模混合IC的版图设计．集成电路通讯．第22卷第2期．2004、6
[40] J.L.McCreary, P.R.Gray," All-MOS Charge Redistribution Analog-to-Digital Conbersion Techniques—Part," IEEE J.Solid-State Circuits, Vol.SC-10 No.6,pp.371-379, Dec. 1975
[41] Christopher Peter Hurrell. Analog to digital convener with a calibration circuit for compensating for coupling capacitor errors, and a method for calibrating the analog to digital convener. United States Patent US 6707403B1, Mar.16,2004.
[42] 杨之廉、申明．超大规模集成电路设计方法学导论．北京：清华大学出版社，1999．
[43] Alan Hastings, "The Art of Analog Layout", 2004 by Peason Education Asia Limited and Tsinghua University press.pp223-224
[44] A.Z.Wang, H.G.Feng.On-Chip ESD protection design for intergrated circuits:an overview for IC designers. Microelectronics Journal 32(2001).733-747.
[45] A.Z.Wang,C.Tsay, A compact square-cell ESD structure for BiCMOS IC,Proc.IEEE BCTM(1999). pp46-49.
[46] H.G.Feng,K.Gong, A.Wang, ESD Protection Design using copper interconnects: more robustness and less parasitics, SCR project report, December 1999.
[47] A.Wang, On-Chip ESD Protection for integrated Circuits—an IC Design Perspective, Kluwer Academic Publishers,Boston,2001.
[48] 王翠霞，范学峰，许维胜等．Cadence版图设计环境的建立及设计规则的验证．《现代电子技术》2004年第15期总第182期。
[49] 程未，冯勇建，杨涵．集成电路版图(1ayout)设计方法与实例[J]．现代电了技术，2003，26(3)：75-78．
[50] Cadence installation guide, Cadence company, product Version2.1 2001, Cadence design systems.Inc. Printed in the United States of America.