基于Verilog HDL的SPI可复用IP核的设计与实现
摘要
SPI(Serial Peripheral Interface,串行外围接口)是Motorola公司提出的外围接口协议,它采用一个串行、同步、全双工的通信方式,解决了微处理器(或者微控制器,嵌入式微处理器)和外设之间的串行通信问题,并且可以和多个外设进行直接通信,具有配置灵活,结构简单等优点。Wishbone总线是Silicore公司推出的片上总线协议,它的结构极其简单、灵活,又完全公开、完全免费,获得众多支持。随着SOC(System On Chip,片上系统)的发展,其设计中需要可复用的IP(Intellectual Property,知识产权)核,因此本文主要内容是用Verilog HDL语言对基于Wishbone片上总线的SPI接口电路进行RTL(Register Transfer Level,寄存器传输级)描述,并在EDA(Electronic Design Automatical,电子设计自动化)平台上对其进行功能的验证和仿真,以此来讨论可复用技术在现代集成电路设计中的应用,并设计面向SOC,便于SOC调用的具有可复用性和实用性的SPI IP核,从而实现SOC通过SPI接口与外围设备的通信。在设计中,本文将程序层次化,完成了spi_master和spi_slave的设计,并且编写了测试程序testbench,检测串并转换之后wishbone_master与spi_slave之间数据传输的正确性,通过软件仿真,来验证其功能的正确性。最终本设计达到预期目标和SPI通信要求,spi_master可以作为一个独立的可重复使用的IP核,被SOC调用。之后,本文还将从功能、速度、面积、成本等方面对本次设计进行分析,以此总结集成电路设计中获得的经验。
The SPI put forward by Motorola Company is a full-duplex, synchronous, serial data link that is standard across many microprocessors, microcontrollers, and peripherals. It enables communication between microprocessors and peripherals and/or inter-processor communication. The SPI system is flexible enough to interface directly with numerous commercially available peripherals, and it also has some excellences such as it can be configured flexibly and it has a simply structure, and so on. Wishbone bus is a On-Chip-Bus protocol released by the company of Silicore. Its structure is very simple, flexible, and it's completely public, completely free, so it acquires numerous supports. Along with the development of System-On-Chip, its design needs reusable IP Core. So this article mainly introduces particularly how to describe the SPI with Verilog HDL in RTL's level, then simulate and verify it with EDA softwares. After then, we probe into the Reusing Methodology's application in modern circuit system. At last we finish a reusable SPI IP core based on Wishbone bus for SOC, to accomplish the correspondence between SOC and peripherals through the SPI. In the design, programme is hiberarchy, and the spi_master's design and the spi_slave's design are finished in this paper, and also have a testbench programme to check SPI function. Finally, the design achieves the expectant target and the SPI protocol's requirements, and the spi_master module is a independent, reusable IP Core for SOC. Then, this text will carry on the analysis to this design from the aspects, such as function, speed, area and cost and so on, and sum up experiences that acquired in the integrated circuit design.
The SPI put forward by Motorola Company is a full-duplex, synchronous, serial data link that is standard across many microprocessors, microcontrollers, and peripherals. It enables communication between microprocessors and peripherals and/or inter-processor communication. The SPI system is flexible enough to interface directly with numerous commercially available peripherals, and it also has some excellences such as it can be configured flexibly and it has a simply structure, and so on. Wishbone bus is a On-Chip-Bus protocol released by the company of Silicore. Its structure is very simple, flexible, and it's completely public, completely free, so it acquires numerous supports. Along with the development of System-On-Chip, its design needs reusable IP Core. So this article mainly introduces particularly how to describe the SPI with Verilog HDL in RTL's level, then simulate and verify it with EDA softwares. After then, we probe into the Reusing Methodology's application in modern circuit system. At last we finish a reusable SPI IP core based on Wishbone bus for SOC, to accomplish the correspondence between SOC and peripherals through the SPI. In the design, programme is hiberarchy, and the spi_master's design and the spi_slave's design are finished in this paper, and also have a testbench programme to check SPI function. Finally, the design achieves the expectant target and the SPI protocol's requirements, and the spi_master module is a independent, reusable IP Core for SOC. Then, this text will carry on the analysis to this design from the aspects, such as function, speed, area and cost and so on, and sum up experiences that acquired in the integrated circuit design.
引文
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[2]沈戈.基于IP核的SOC设计方法及其应用的研究.西北工业大学硕士学位论文.2002:2.
[3]焦慧芳.贾新章.SOC系统设计发展与挑战.电子产品可靠性与环境试验.2004,第4期:55-59.
[4]Chris Rowen.Engineering the Complex SOC.机械工业出版社,2005
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[8]Jozwiak L Quality-driven system-on-chip design.IEEE 2000 First International Symposium on Quality Electronic Design.2000:93-102.
[9]陆思安.可复用IP核以及系统芯片SOC的测试结构研究.浙江大学博士学位论文,2003:8-10.
[10]高谷刚.罗春.可复用SPI模块IP核的设计与验证.单片机与嵌入式系统应用,2004(11):5-8.
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[13]刘韬.楼兴华.FPGA数字电子系统设计开发与实例人民邮电出版社,2005.
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[15]J.Bhasker.Verilog HDL硬件描述语言.第二版.机械工业出版社,2004.
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[18]程铮.几种硬件描述语言HDL的现状与发展.重庆工业高等专科学校学报.2004,vol.19 No.5:36-38.
[19]李乙成.周祖成.陈尚松.SoC片上总线技术的研究半导体技术2003:第28卷第2期.
[20]ARM Ltd.:AMBA~(TM)Specification(Rev2.0),1999.5
[21]郭书军.王玉花.葛纫秋.嵌入式处理器原理及应用.清华大学出版社,2004.
[22]彭澄廉.挑战SOC——于NIOS的SOPC设计与实践.清华大学出版社,2004.
[23]王建校.危建国.SOPC设计基础与实践.西安电子科技大学出版,2006.
[24]徐光辉.程东旭.黄如.基于FGPA的嵌入式开发与应用.电子工业出版社,2006.
[25]http://www.opencores.org/wishbone/specs/wbspec_b3.pdf
[26]Simon Srot.SPI Master Core Specification.OpENCORES,2004
[27]易志明.林凌.郝丽宏.李树靖.SPI串行总线接口及其实现.自动化与仪器仪表,2002(6):45-48.
[28]李宽余.戴瑜兴.张义兵.基于可编程逻辑器件的串行外设接口设计及实现.低压器件,2004(11):28-30.
[29]Xilinx Corporation.CoolRunner Serial Peripheral Interface Master.2002
[30]Motorola Corporation.SPI Block Guide V04.01.2004
[31]牛风举.刘元成.朱明程.基于IP复用的数字IC设计技术.电子工业出版社,2003
[32]牛风举.朱明程.芯片设计中的IP技术.Semiconductor Technology.2001,vol 26.n010:21-25
[33]Jan M..Rabaey.数字集成电路—设计透视(影印版).清华大学出版社,1998.
[34]Bob Zidaman.基于FGPA&CPLD的数字IC设计方法.赵宏图.北京航空航天大学出版社,2004.
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[36]Cadence Design Systems Inc.Verilog-XL Reference[C].Cadence,2003
[37]陈献文.HDL Debugging with Debussy[M].2004
[38]方承志.李元.李明栋.用于嵌入式系统多路SPI Master接口设计.电子测量,2004(2):17-19.
[39]Bob.Gelinas.Vstyle:A Coding Style Analyzer for Synthesizalbe Verilog.Verilog HDL Conference.IEEE,1996:50-57.
[40]L.Bacciarelli.G.Lucia.Design,testing and prototyping of a software programmable I2C/SPI IP on AMBA bus.Research in Microelectronis and Electronic.2006:373-376.
[41]Behrooz Parhami.Computer Arithmetic Algorithms and Hardware Designs [M].Oxford University Publishers,2000
[42]杜慧敏.赵全量.基于Verilog的FPGA设计基础.西安电子科技大学出版设,2005.
[43]Michael.D.Ciletti.Verilog HDL高级数字设计.张雅绮.李锵.电子工业出版社,2005.
[44]夏宇闻.复杂数字逻辑系统的VerilogHDL设计技术和方法[M].北京:高等教育出版社,2001.
[45]尼尔H.E.维斯特.大卫.哈里斯等.“CMOS大规模集成电路设计”[M].机械工业出版社,2005.
[46]简弘伦.精通Verilog HDL:IC设计核心技术实例详解.电子工业出版社,2005.
[2]沈戈.基于IP核的SOC设计方法及其应用的研究.西北工业大学硕士学位论文.2002:2.
[3]焦慧芳.贾新章.SOC系统设计发展与挑战.电子产品可靠性与环境试验.2004,第4期:55-59.
[4]Chris Rowen.Engineering the Complex SOC.机械工业出版社,2005
[5]Michael Keating.Pierre Bricaud.Reuse Methodology Manual for System-on-a-Chips.KluwerAcademic Publishers,1999.
[6]李加元.系统芯片设计中的可复用IP技术.半导体技术.2004,31(1):15-17.
[7]Bricaud P J.IP reuse creation for system-on-a-chip design.Proceedings of the IEEE Custom Integrated Circuit.1999:395-401.
[8]Jozwiak L Quality-driven system-on-chip design.IEEE 2000 First International Symposium on Quality Electronic Design.2000:93-102.
[9]陆思安.可复用IP核以及系统芯片SOC的测试结构研究.浙江大学博士学位论文,2003:8-10.
[10]高谷刚.罗春.可复用SPI模块IP核的设计与验证.单片机与嵌入式系统应用,2004(11):5-8.
[11]罗杰.康华光.两种硬件描述语言VHDL/Nerilog的发展及其应用电气电子教学学报2002,Vol.24 No.4:1-5.
[12]Xudong Shi.Phillip E.Allen.Use of VHDL to Model and Simulate Analog-Digital ICs.Circuits and Systems.Proceedings of the 35th Midwest Symposium:IEEE,1992 vol.2:908-911.
[13]刘韬.楼兴华.FPGA数字电子系统设计开发与实例人民邮电出版社,2005.
[14]Design Automation Standards Committee of the IEEE Computer Society.IEEE Standard Hardware Description Language Based on the Verilog Hardware Description Language.1995.
[15]J.Bhasker.Verilog HDL硬件描述语言.第二版.机械工业出版社,2004.
[16]王金明.VerilogHDL程序设计教程人民邮电出版社,2004.
[17]Douglas J.Smith VHDL & Verilog Compared & Contrasted- Plus Modeled Example Written in VI-IDL,Verilog and C.IEEE.Design Automation Conference Proceedings,1996:771-776.
[18]程铮.几种硬件描述语言HDL的现状与发展.重庆工业高等专科学校学报.2004,vol.19 No.5:36-38.
[19]李乙成.周祖成.陈尚松.SoC片上总线技术的研究半导体技术2003:第28卷第2期.
[20]ARM Ltd.:AMBA~(TM)Specification(Rev2.0),1999.5
[21]郭书军.王玉花.葛纫秋.嵌入式处理器原理及应用.清华大学出版社,2004.
[22]彭澄廉.挑战SOC——于NIOS的SOPC设计与实践.清华大学出版社,2004.
[23]王建校.危建国.SOPC设计基础与实践.西安电子科技大学出版,2006.
[24]徐光辉.程东旭.黄如.基于FGPA的嵌入式开发与应用.电子工业出版社,2006.
[25]http://www.opencores.org/wishbone/specs/wbspec_b3.pdf
[26]Simon Srot.SPI Master Core Specification.OpENCORES,2004
[27]易志明.林凌.郝丽宏.李树靖.SPI串行总线接口及其实现.自动化与仪器仪表,2002(6):45-48.
[28]李宽余.戴瑜兴.张义兵.基于可编程逻辑器件的串行外设接口设计及实现.低压器件,2004(11):28-30.
[29]Xilinx Corporation.CoolRunner Serial Peripheral Interface Master.2002
[30]Motorola Corporation.SPI Block Guide V04.01.2004
[31]牛风举.刘元成.朱明程.基于IP复用的数字IC设计技术.电子工业出版社,2003
[32]牛风举.朱明程.芯片设计中的IP技术.Semiconductor Technology.2001,vol 26.n010:21-25
[33]Jan M..Rabaey.数字集成电路—设计透视(影印版).清华大学出版社,1998.
[34]Bob Zidaman.基于FGPA&CPLD的数字IC设计方法.赵宏图.北京航空航天大学出版社,2004.
[35]Charles Dawson.Sathyam K.Pattanam.David Roberts.The Verilog Procedrual Interface for the Verilog Hardware Description.Verilog HDL Conference,1996,IEEE
[36]Cadence Design Systems Inc.Verilog-XL Reference[C].Cadence,2003
[37]陈献文.HDL Debugging with Debussy[M].2004
[38]方承志.李元.李明栋.用于嵌入式系统多路SPI Master接口设计.电子测量,2004(2):17-19.
[39]Bob.Gelinas.Vstyle:A Coding Style Analyzer for Synthesizalbe Verilog.Verilog HDL Conference.IEEE,1996:50-57.
[40]L.Bacciarelli.G.Lucia.Design,testing and prototyping of a software programmable I2C/SPI IP on AMBA bus.Research in Microelectronis and Electronic.2006:373-376.
[41]Behrooz Parhami.Computer Arithmetic Algorithms and Hardware Designs [M].Oxford University Publishers,2000
[42]杜慧敏.赵全量.基于Verilog的FPGA设计基础.西安电子科技大学出版设,2005.
[43]Michael.D.Ciletti.Verilog HDL高级数字设计.张雅绮.李锵.电子工业出版社,2005.
[44]夏宇闻.复杂数字逻辑系统的VerilogHDL设计技术和方法[M].北京:高等教育出版社,2001.
[45]尼尔H.E.维斯特.大卫.哈里斯等.“CMOS大规模集成电路设计”[M].机械工业出版社,2005.
[46]简弘伦.精通Verilog HDL:IC设计核心技术实例详解.电子工业出版社,2005.