基于分块编码的SoC测试数据压缩方法研究
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摘要
SoC技术的出现,给超大规模集成电路VLSI的设计带来了一场革命,它通过复用大量具有自主知识产权(IP)的芯核,极大地缩短了开发周期,加快了产品上市速度,提高了芯片的产量。随着SoC技术的发展,芯片的集成度迅速提高,芯片测试的复杂性和测试数据量随之激增,而传统的ATE的存储空间、工作频率以及带宽却非常有限,这使得SoC测试面临着测试时间过长、测试难度和测试成本急剧增加等诸多方面问题。
目前解决这类问题的一种行之有效的方法是运用测试数据压缩技术,该技术的运用能够达到简化测试实施过程、减少测试实施时间以及降低测试成本的目的。
为了充分发挥测试集中无关位多且各测试向量所包含的无关位数量差异大的特点,本文提出了一种新颖的基于变长数据块相关性统计方法,以测试向量为单位,运用统计和数据块相关性的思想,先确定向量的参考数据块,再利用它与该向量中数据块的相关性进行压缩。各向量的参考数据块长度相互独立,且同时具有和该向量中数据块相关性频率最高以及用其对向量进行编码得到的位数最少的特点。该方案运用对不同测试向量分而治之的策略,突破了在整个测试集范围内操作所受的限制。同大部分现有方法相比,该方法更有效地压缩了测试集,且硬件解压结构也较简单,具有较好的适用性。
本文随后提出了一种基于连续及非连续长度块编码方法,该方法从提高码字利用率出发,是一种新的固定长度编码方法。将测试集看成若干个连续‘0'序列和‘1'序列,将长度超过被选择的长度k的序列看成连续块,利用一个定长的k位二进制编码表示该块的长度信息;同时,创新性的对短序列进行了处理,即连续长度不足k位的序列,按一定的策略被划为非连续块,并且不对其进行编码。该策略有效地减小了编码中序列长度变化大带来的影响,避免了用长码字替换短序列的情况。同时本方案减小了使用前、后缀形式编码的复杂性,所以其编码及解码过程简单,具有简单的通讯协议。文中对ISCAS-89标准电路原测试集以及差分预处理后的测试集进行了实验,结果表明本方案能获得较高的压缩率,并通过设计的硬件解压结构能顺利还原成原始数据,是一种具有较强适用性的方法。
The emergence of SoC technology brings a revolution to the design of the VLSI, through reuse a lot of independent intellectual property (IP) cores, chip design cycle is greatly shortted, the speed to market is accelerated, and the output increases correspondingly. Due to the development of SoC, the integration of the chip increase rapidly, the complexity of chip testing and test data volume also increase, while the storage capacity, frequency and the band of the traditional ATE are very limited, these make SoC test facing some problems, such as the time of test is too long, the difficulty and the costs of test increases rapidly and so on.
Presently, test data compression technology is an effective solution to these problems. It can be used to simplify the implementation of the test, reduce the test implementation time and lower the test costs.
In order to give full play to the features that the don't-care bits in the test set are plentiful and the number of them in each test vectors are by large difference, this dissertation presents a new method based on statistic relativity of variable length data blocks, for each test vector, use the thought of statistics and relativity of data blocks, determine the referenced data block of it, then compress the vector by the relativity between its data blocks and the referenced data block. Besides, the length of referenced data block is independent from each other, at the same time, the referenced data block of each vector has the characteristics that it has the highest frequency of relativity and the least code. The proposed method uses the divide and rule tactic with different vectors to break the constraints in the entire test set. Compare with most of the existing method, it can compress the test set more efficiently, and the decompression architecture is relatively simple, so the applicability of this method is better than others.
After that, a new fixed length test data compression method based on encoding the data blocks which are sequential or non-continuous is proposed, with intent to improve the efficiency of the code, view the test set as a number of '0' sequences and the ' 1' sequences, the sequences length over the selected block length k will be seen as sequential blocks, a binary code with fixed length is used to express the length information of the sequential block. On the other hand, the sequences which has lack of it-length is made to be non-continuous data blocks by some strategy, and not be encoded, so it can avoid the situation that short sequences replaced by long code. The rule proposed by the method reduces the complexity of encoding which makes use of prefix and tail code separately, so the process of it's encoding and decoding is simple, and the protocol of communication is also simple. Experiments have been done in the original and precomputed difference test set of ISCAS-89 benchmark circuits, the result shows that this method can receive a higher compression ratio, the decompression architecture designed can decode the compressed test set to original test set accurately, so the method proposed has much more applicability.
目前解决这类问题的一种行之有效的方法是运用测试数据压缩技术,该技术的运用能够达到简化测试实施过程、减少测试实施时间以及降低测试成本的目的。
为了充分发挥测试集中无关位多且各测试向量所包含的无关位数量差异大的特点,本文提出了一种新颖的基于变长数据块相关性统计方法,以测试向量为单位,运用统计和数据块相关性的思想,先确定向量的参考数据块,再利用它与该向量中数据块的相关性进行压缩。各向量的参考数据块长度相互独立,且同时具有和该向量中数据块相关性频率最高以及用其对向量进行编码得到的位数最少的特点。该方案运用对不同测试向量分而治之的策略,突破了在整个测试集范围内操作所受的限制。同大部分现有方法相比,该方法更有效地压缩了测试集,且硬件解压结构也较简单,具有较好的适用性。
本文随后提出了一种基于连续及非连续长度块编码方法,该方法从提高码字利用率出发,是一种新的固定长度编码方法。将测试集看成若干个连续‘0'序列和‘1'序列,将长度超过被选择的长度k的序列看成连续块,利用一个定长的k位二进制编码表示该块的长度信息;同时,创新性的对短序列进行了处理,即连续长度不足k位的序列,按一定的策略被划为非连续块,并且不对其进行编码。该策略有效地减小了编码中序列长度变化大带来的影响,避免了用长码字替换短序列的情况。同时本方案减小了使用前、后缀形式编码的复杂性,所以其编码及解码过程简单,具有简单的通讯协议。文中对ISCAS-89标准电路原测试集以及差分预处理后的测试集进行了实验,结果表明本方案能获得较高的压缩率,并通过设计的硬件解压结构能顺利还原成原始数据,是一种具有较强适用性的方法。
The emergence of SoC technology brings a revolution to the design of the VLSI, through reuse a lot of independent intellectual property (IP) cores, chip design cycle is greatly shortted, the speed to market is accelerated, and the output increases correspondingly. Due to the development of SoC, the integration of the chip increase rapidly, the complexity of chip testing and test data volume also increase, while the storage capacity, frequency and the band of the traditional ATE are very limited, these make SoC test facing some problems, such as the time of test is too long, the difficulty and the costs of test increases rapidly and so on.
Presently, test data compression technology is an effective solution to these problems. It can be used to simplify the implementation of the test, reduce the test implementation time and lower the test costs.
In order to give full play to the features that the don't-care bits in the test set are plentiful and the number of them in each test vectors are by large difference, this dissertation presents a new method based on statistic relativity of variable length data blocks, for each test vector, use the thought of statistics and relativity of data blocks, determine the referenced data block of it, then compress the vector by the relativity between its data blocks and the referenced data block. Besides, the length of referenced data block is independent from each other, at the same time, the referenced data block of each vector has the characteristics that it has the highest frequency of relativity and the least code. The proposed method uses the divide and rule tactic with different vectors to break the constraints in the entire test set. Compare with most of the existing method, it can compress the test set more efficiently, and the decompression architecture is relatively simple, so the applicability of this method is better than others.
After that, a new fixed length test data compression method based on encoding the data blocks which are sequential or non-continuous is proposed, with intent to improve the efficiency of the code, view the test set as a number of '0' sequences and the ' 1' sequences, the sequences length over the selected block length k will be seen as sequential blocks, a binary code with fixed length is used to express the length information of the sequential block. On the other hand, the sequences which has lack of it-length is made to be non-continuous data blocks by some strategy, and not be encoded, so it can avoid the situation that short sequences replaced by long code. The rule proposed by the method reduces the complexity of encoding which makes use of prefix and tail code separately, so the process of it's encoding and decoding is simple, and the protocol of communication is also simple. Experiments have been done in the original and precomputed difference test set of ISCAS-89 benchmark circuits, the result shows that this method can receive a higher compression ratio, the decompression architecture designed can decode the compressed test set to original test set accurately, so the method proposed has much more applicability.
引文
[1]The National Technology Roadmap for Semiconductors(ITRS),1997 Edition Semiconductor Industry Association.
[2]李桂宏、谢世健,集成电路设计宝典.电子工业出版社,2006年4月出版,7月第2次印刷.
[3]HAN Yin-He,LI Xiao-Wei,XU Yong-Jun,et al.System-on-a-Chip Test-Data Coding Compression Technology[J].Microelectronics & Computer,2003,20(2):44-47(in Chinese)[韩银和、李晓维、徐勇军等,SoC测试数据的编码压缩技术[J].微电子学和计算机,2003,20(2):44-47].
[4]A.Chandra,K.Chakrabarty.Frequency-directed run-length(FDR)codes with application to system-on-a-chip test data compression[C].VLSI Test Symposium,19th IEEE Proceedings on.VTS 2001,29 April-3 May 2001:42-47.
[5]Z.Barzilai,D.Coppersmith,A.L.Rosenberg.Exhaustive generation of bit pattern with application to VLSI self-testing.IEEE Transactions on Computer,Volume C-32,Issue 2,Feb 1983,pp.190-194.
[6]L.T.Wang and E.J.McCluskey.Cireuits for pseudo-exhaustive pattern generation,Proceeding of IEEE Int.Test Conf.,1986,pp.25-37.
[7]H.J.Wundelich,S.Hellebrand.The pseudo-exhaustive test of sequential circuits,IEEE Trans.of Computer-Aided Design Integrated Circuits Syst.,Vol.11,No.1,pp.26-33,1992.
[8]P.Bardell,W.H.McAnney,J.Savir.Biult-in Test for VLSI.New York,WileyInterscienee,1987.
[9]N.Touba,E.J.McCluskey.Altering a pseudo-random bit sequence for scan based BIST.Proceedings of International Test Conference,1996,pp.167-175.
[10]B.Koenemann.LFSR-Coded Test Pattern for Scan Design.Proc.of European Test Conference,Munich,Germany,April 1991,pp.273-242.
[11]S.Hellebrand,S.Tarnick,J.Rajski,et.al.Generation of Vector Parrern Through Reseeding of Multiple-polynomial Linear Feedback Shift Registers,in proc.IEEE Int.Test Conf.,Baltimore,MD,1992,pp.120-129.
[12]S.Venkataraman,J.Rajski,S.Hellebrand,et.al.An Efficient BIST Scheme Based on Reseeding of Multiple-polynomial Linear Feedback Shift Registers,Proceeding of IEEE/ACM Int.Conf.Computer-Aided Design,Santa Clara,CA,1993,pp.572-577.
[13]梁华国,聚贝勒.海伦布昂特,汉斯-耶西姆.冯特利希.一种基于折叠计数器重新播种的确定自测试方案.计算机研究与发展,2001,Vol.38,No.8, pp.931-938.
[14]梁华国,方祥圣,蒋翠云,欧阳一鸣,易茂祥.一种选择折叠计数器状态转移的BIST方案.计算机研究与发展,2006,Vol.43,No.2,pp.343-349.
[15]S.Hellerbrand,Hua-Guo Liang,Hans-Joachim Wunderlich.A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters,Proceedings IEEE International Test Conference,Atlantic City,NJ,Oct 2000,pp.778-784.
[16]S.Swaminathan and K.Chakrabatarty.On Using Twisted-ring Counters for Test Set Embedding in BIST.Journal of Electronic Testing,Theory and Application,Dec 2001,Vol.17,pp.530-542.
[17]K.Chakrabarty,V.Iyengar and A.Chandra.Test Recourse Partitioning for System-on-a-chip,Kluwer Aeademic Publishers,Norwell,MA,2002.
[18]A.Chandra and K.Chakrabarty.Test resource partitioning for System-on-achip,based on test data compression and on-chip decompression",IEEE Design and Test of Computers,September/October,2001,vol.18,pp.80-91.
[19]A.Chandra and K.Chakrabarty,Test data compression and test resource partitioning for system-on-a-chip using frequency-directed run-length(FDR)codes.Computers,IEEE Transactions on Volume 52,Issue 8,Aug.2003Page(s):1076-1088.
[20]A.Chandra and K.Chakrabarty,System-on-a-chip test data compression and decompression architectures based on Golomb codes,IEEE Trans.ComputerAided Design,Vol.20,March 2001,pp.355-368.
[21]A Jas,J G Dastidar,N A Touba.Scan vector compression/decompression using statistical coding.Proceeding of 17th IEEE VLSI Test Symposium.Dana Point,California,1999,114-121.
[22]A Jas,J G.Dastidar,N A Touba.An efficient test vector compression scheme using selective huffman coding.IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2003,22(6):797-806.
[23]梁华国,蒋翠云.基于交替与连续长度码的有效测试数据压缩和解压.计算机学报,2004,27(4):549-554.
[24]Xiaoyu Ruan,Rajendra Katti.An efficient data-independent technique for compressing test vectors in Systems-on-a-Chip.IEEE Proceedings of the 2006Emerging VLSI Technologies and Architectures,2006,pp.153-158.
[25]Mohammad Tehranipoor,Mehrdad Nourani,K Chakrabarty.Nine-coded compression technique for testing embedded cores in SoCs.IEEE Transactions on VLSI systems,Vol.13,No.6,Jun,2006,pp.719-731.
[26]Mohammad Tehranipoor,Mehrdad Nourani,K Chakrabarty.Nine-coded compression technique with Application to Reduced Pin-Count Testing and Flexible-on-chip Decompression. Proceedings of IEEE /ACM Design, Automation and Test in Europe (DATE) Conference, 2004, pp. 1284-1289.
[27] A. Jas, and N. A.Touba, Test vector decompression via cyclical scan chains and its application to testing core-based design, Proc. ITC, 1998, pp.458-464.
[28] E.J. McClusky. Verification Testing - A Pseudo-Exhaustive Test Technique. IEEE Trans. on Computers, June 1984, vol. C-33, No. 6, pp.541-546.
[29] E.J. McClusky and S. Bozorgui-Nesbat. Design for Autonomous Test. IEEE Trans. on Circuits and Systems, vol. CAS-28, Nov. 1981, No.11, pp. 1070-1079.
[30] A.K.Chandra, L.T.Kou, GMarkowsky, and S.Zaks. On Sets of Boolean n-Vectors with All k-Projections Surjective. Acta Information, Oct. 1983, vol. 20, No.1.pp. 103-111.
[31] C. L. Chen. Exhaustive Test Pattern Generation Using Cyclic Codes. IEEE Trans on Computers, Feb. 1988, vol. C-37, No. 2, pp.225-228.
[32] J. G. Udell Jr. Test Set Generation for Pseudo-Exhaustive BIST. in proc. of the International Conf. on Computer-Aided Design, Nov. 1986, pp.52-55.
[33] Michael L.Bushnell, Vishwani D. Agrawal 著 蒋安平等译. 超大规模集成电路测试. 电子工业出版社, 2005年8月第1次印刷.
[34] Chih-Ang Chen and Sandeep K.Gupta.Efficient BIST TGP Design and Test Set Compaction Via Input Reduction.IEEE Transactions on Computer-Aided Design of Intergrated Circuit and Systems, Vol.17, No.8, August 1998, pp. 692-705.
[35] K Chakrabarty and B T Murray.Design of Built-in Test Generator Circuits Using Width Compression, IEEE Transactions on CAD/ICAS, Vol. 17, Oct 1998, pp. 1044-1051.
[36] A.Raghunathan and S.T.Chakradhar.Acceleration Techniques for Dynamic Vector Compaction. 1995 IEEE/ACM International Conference on Computer-Aided Design, Nov. 1995, pp. 310-317.
[37] L.Hamzaoglu and J.H.Patel.Test Set Compaction Algorithms for Combinational Circuits. IEEE Transactions on Computer-Aided of Integrated Circuits and Systems, 2000, 19(8), pp 957-963.
[38] I.Pomeranz and S.M.Reddy.Static Compaction for Two-Pattern Test Sets. Proceedings of the Fourth Asian Test Symposium, Nov. 1995, pp. 222-228.
[39] I.Pomeranz and S.M.Reddy. Static Test Compaction for Scan-Based Designs to Application Time. Proceedings of the Seventh Asian Test Symposium, Dec. 1998,pp 198-203.
[40]A.H.El-Maleh and R.H.Al-abaji,Extended frequency-directed run-length code with improved application to system-on-a-chip test data compression,International Conference on Electronics,Circuits and Systems,vol.2,September 2002,pp.449-452.
[41]P.Gonciari,B.Al-Hashimi and N.Nicolici,Improving compression ratio,area overhead,and test application time for system-on-a-chip test data compression/decompression,Proc.DATE,2002,pp.604-611.
[42]Lei Li,Chakrabarty.K.Test data compression using dictionaries with fixed-length indices[SOC testing].VLSI Test Symposium,2003.Proceedings.21st,27 April-1 May 2003 Page(s):219-224.
[43]L.Li,K.Chakrabarty and N.A.Touba,Test data compression using dictionaries with selective entries and fixed-length indices,ACM Trans.On Design Automation of Electronic Systems,2003,pp.470-490.
[44]E.J.McCluskey,D.Burek,et al.Test Data Compression.IEEE Design&Test of Computers,20(2),March-April 2003,pp.76-87.
[45]S.W.Golomb.Run-Length Encoding.IEEE transactions on Information Theory,1966,IT-12:399-401.
[46]Chandra.A.,Chakrabarty.K.System-on-a-chip test-data compression and decompression architectures based on internal scan chains and Golomb codes.IEEE Transactions on computer-aided design of integrated circuit &systems,vol.21,2002,pp.715-722.
[47]韩银和,李晓维,徐勇军,李华伟.应用Variable-Tail编码压缩的测试资源划分方法[J].电子学报,2004,32(8):1346-1350.Han Yin-he,Li Xiao-wei,Xu Yong-jun,Li Hua-wei.Test resource partitioning using variable-tail code[J].Acta Eelectronica Sinica,2004,32(8):1346-1350.(in Chinese).
[48]R.David.Signature Analysis of Multi-Output Circuit.Proceding of International Fault-tolerant Computing Symp.July 1981,pp.32-34.
[49]El-Maleh.A.H.;Al-Abaji.R.H,Extended frequency-directed run-length code with improved application to system-on-a-chip test data compression.Electronics,Circuits and Systems,2002.9th International Conference on Volume 2,15-18 Sept.2002,vol.2,pp:449-452.
[50]W.Armin,S.T.Christofer,H.Sybille,A Hybrid Coding Strategy for Optimized Test Data Compression,Proceedings IEEE Internatioanal Test Conference,Charlotte,NC,USA,September 30-October 2,2003.
[2]李桂宏、谢世健,集成电路设计宝典.电子工业出版社,2006年4月出版,7月第2次印刷.
[3]HAN Yin-He,LI Xiao-Wei,XU Yong-Jun,et al.System-on-a-Chip Test-Data Coding Compression Technology[J].Microelectronics & Computer,2003,20(2):44-47(in Chinese)[韩银和、李晓维、徐勇军等,SoC测试数据的编码压缩技术[J].微电子学和计算机,2003,20(2):44-47].
[4]A.Chandra,K.Chakrabarty.Frequency-directed run-length(FDR)codes with application to system-on-a-chip test data compression[C].VLSI Test Symposium,19th IEEE Proceedings on.VTS 2001,29 April-3 May 2001:42-47.
[5]Z.Barzilai,D.Coppersmith,A.L.Rosenberg.Exhaustive generation of bit pattern with application to VLSI self-testing.IEEE Transactions on Computer,Volume C-32,Issue 2,Feb 1983,pp.190-194.
[6]L.T.Wang and E.J.McCluskey.Cireuits for pseudo-exhaustive pattern generation,Proceeding of IEEE Int.Test Conf.,1986,pp.25-37.
[7]H.J.Wundelich,S.Hellebrand.The pseudo-exhaustive test of sequential circuits,IEEE Trans.of Computer-Aided Design Integrated Circuits Syst.,Vol.11,No.1,pp.26-33,1992.
[8]P.Bardell,W.H.McAnney,J.Savir.Biult-in Test for VLSI.New York,WileyInterscienee,1987.
[9]N.Touba,E.J.McCluskey.Altering a pseudo-random bit sequence for scan based BIST.Proceedings of International Test Conference,1996,pp.167-175.
[10]B.Koenemann.LFSR-Coded Test Pattern for Scan Design.Proc.of European Test Conference,Munich,Germany,April 1991,pp.273-242.
[11]S.Hellebrand,S.Tarnick,J.Rajski,et.al.Generation of Vector Parrern Through Reseeding of Multiple-polynomial Linear Feedback Shift Registers,in proc.IEEE Int.Test Conf.,Baltimore,MD,1992,pp.120-129.
[12]S.Venkataraman,J.Rajski,S.Hellebrand,et.al.An Efficient BIST Scheme Based on Reseeding of Multiple-polynomial Linear Feedback Shift Registers,Proceeding of IEEE/ACM Int.Conf.Computer-Aided Design,Santa Clara,CA,1993,pp.572-577.
[13]梁华国,聚贝勒.海伦布昂特,汉斯-耶西姆.冯特利希.一种基于折叠计数器重新播种的确定自测试方案.计算机研究与发展,2001,Vol.38,No.8, pp.931-938.
[14]梁华国,方祥圣,蒋翠云,欧阳一鸣,易茂祥.一种选择折叠计数器状态转移的BIST方案.计算机研究与发展,2006,Vol.43,No.2,pp.343-349.
[15]S.Hellerbrand,Hua-Guo Liang,Hans-Joachim Wunderlich.A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters,Proceedings IEEE International Test Conference,Atlantic City,NJ,Oct 2000,pp.778-784.
[16]S.Swaminathan and K.Chakrabatarty.On Using Twisted-ring Counters for Test Set Embedding in BIST.Journal of Electronic Testing,Theory and Application,Dec 2001,Vol.17,pp.530-542.
[17]K.Chakrabarty,V.Iyengar and A.Chandra.Test Recourse Partitioning for System-on-a-chip,Kluwer Aeademic Publishers,Norwell,MA,2002.
[18]A.Chandra and K.Chakrabarty.Test resource partitioning for System-on-achip,based on test data compression and on-chip decompression",IEEE Design and Test of Computers,September/October,2001,vol.18,pp.80-91.
[19]A.Chandra and K.Chakrabarty,Test data compression and test resource partitioning for system-on-a-chip using frequency-directed run-length(FDR)codes.Computers,IEEE Transactions on Volume 52,Issue 8,Aug.2003Page(s):1076-1088.
[20]A.Chandra and K.Chakrabarty,System-on-a-chip test data compression and decompression architectures based on Golomb codes,IEEE Trans.ComputerAided Design,Vol.20,March 2001,pp.355-368.
[21]A Jas,J G Dastidar,N A Touba.Scan vector compression/decompression using statistical coding.Proceeding of 17th IEEE VLSI Test Symposium.Dana Point,California,1999,114-121.
[22]A Jas,J G.Dastidar,N A Touba.An efficient test vector compression scheme using selective huffman coding.IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2003,22(6):797-806.
[23]梁华国,蒋翠云.基于交替与连续长度码的有效测试数据压缩和解压.计算机学报,2004,27(4):549-554.
[24]Xiaoyu Ruan,Rajendra Katti.An efficient data-independent technique for compressing test vectors in Systems-on-a-Chip.IEEE Proceedings of the 2006Emerging VLSI Technologies and Architectures,2006,pp.153-158.
[25]Mohammad Tehranipoor,Mehrdad Nourani,K Chakrabarty.Nine-coded compression technique for testing embedded cores in SoCs.IEEE Transactions on VLSI systems,Vol.13,No.6,Jun,2006,pp.719-731.
[26]Mohammad Tehranipoor,Mehrdad Nourani,K Chakrabarty.Nine-coded compression technique with Application to Reduced Pin-Count Testing and Flexible-on-chip Decompression. Proceedings of IEEE /ACM Design, Automation and Test in Europe (DATE) Conference, 2004, pp. 1284-1289.
[27] A. Jas, and N. A.Touba, Test vector decompression via cyclical scan chains and its application to testing core-based design, Proc. ITC, 1998, pp.458-464.
[28] E.J. McClusky. Verification Testing - A Pseudo-Exhaustive Test Technique. IEEE Trans. on Computers, June 1984, vol. C-33, No. 6, pp.541-546.
[29] E.J. McClusky and S. Bozorgui-Nesbat. Design for Autonomous Test. IEEE Trans. on Circuits and Systems, vol. CAS-28, Nov. 1981, No.11, pp. 1070-1079.
[30] A.K.Chandra, L.T.Kou, GMarkowsky, and S.Zaks. On Sets of Boolean n-Vectors with All k-Projections Surjective. Acta Information, Oct. 1983, vol. 20, No.1.pp. 103-111.
[31] C. L. Chen. Exhaustive Test Pattern Generation Using Cyclic Codes. IEEE Trans on Computers, Feb. 1988, vol. C-37, No. 2, pp.225-228.
[32] J. G. Udell Jr. Test Set Generation for Pseudo-Exhaustive BIST. in proc. of the International Conf. on Computer-Aided Design, Nov. 1986, pp.52-55.
[33] Michael L.Bushnell, Vishwani D. Agrawal 著 蒋安平等译. 超大规模集成电路测试. 电子工业出版社, 2005年8月第1次印刷.
[34] Chih-Ang Chen and Sandeep K.Gupta.Efficient BIST TGP Design and Test Set Compaction Via Input Reduction.IEEE Transactions on Computer-Aided Design of Intergrated Circuit and Systems, Vol.17, No.8, August 1998, pp. 692-705.
[35] K Chakrabarty and B T Murray.Design of Built-in Test Generator Circuits Using Width Compression, IEEE Transactions on CAD/ICAS, Vol. 17, Oct 1998, pp. 1044-1051.
[36] A.Raghunathan and S.T.Chakradhar.Acceleration Techniques for Dynamic Vector Compaction. 1995 IEEE/ACM International Conference on Computer-Aided Design, Nov. 1995, pp. 310-317.
[37] L.Hamzaoglu and J.H.Patel.Test Set Compaction Algorithms for Combinational Circuits. IEEE Transactions on Computer-Aided of Integrated Circuits and Systems, 2000, 19(8), pp 957-963.
[38] I.Pomeranz and S.M.Reddy.Static Compaction for Two-Pattern Test Sets. Proceedings of the Fourth Asian Test Symposium, Nov. 1995, pp. 222-228.
[39] I.Pomeranz and S.M.Reddy. Static Test Compaction for Scan-Based Designs to Application Time. Proceedings of the Seventh Asian Test Symposium, Dec. 1998,pp 198-203.
[40]A.H.El-Maleh and R.H.Al-abaji,Extended frequency-directed run-length code with improved application to system-on-a-chip test data compression,International Conference on Electronics,Circuits and Systems,vol.2,September 2002,pp.449-452.
[41]P.Gonciari,B.Al-Hashimi and N.Nicolici,Improving compression ratio,area overhead,and test application time for system-on-a-chip test data compression/decompression,Proc.DATE,2002,pp.604-611.
[42]Lei Li,Chakrabarty.K.Test data compression using dictionaries with fixed-length indices[SOC testing].VLSI Test Symposium,2003.Proceedings.21st,27 April-1 May 2003 Page(s):219-224.
[43]L.Li,K.Chakrabarty and N.A.Touba,Test data compression using dictionaries with selective entries and fixed-length indices,ACM Trans.On Design Automation of Electronic Systems,2003,pp.470-490.
[44]E.J.McCluskey,D.Burek,et al.Test Data Compression.IEEE Design&Test of Computers,20(2),March-April 2003,pp.76-87.
[45]S.W.Golomb.Run-Length Encoding.IEEE transactions on Information Theory,1966,IT-12:399-401.
[46]Chandra.A.,Chakrabarty.K.System-on-a-chip test-data compression and decompression architectures based on internal scan chains and Golomb codes.IEEE Transactions on computer-aided design of integrated circuit &systems,vol.21,2002,pp.715-722.
[47]韩银和,李晓维,徐勇军,李华伟.应用Variable-Tail编码压缩的测试资源划分方法[J].电子学报,2004,32(8):1346-1350.Han Yin-he,Li Xiao-wei,Xu Yong-jun,Li Hua-wei.Test resource partitioning using variable-tail code[J].Acta Eelectronica Sinica,2004,32(8):1346-1350.(in Chinese).
[48]R.David.Signature Analysis of Multi-Output Circuit.Proceding of International Fault-tolerant Computing Symp.July 1981,pp.32-34.
[49]El-Maleh.A.H.;Al-Abaji.R.H,Extended frequency-directed run-length code with improved application to system-on-a-chip test data compression.Electronics,Circuits and Systems,2002.9th International Conference on Volume 2,15-18 Sept.2002,vol.2,pp:449-452.
[50]W.Armin,S.T.Christofer,H.Sybille,A Hybrid Coding Strategy for Optimized Test Data Compression,Proceedings IEEE Internatioanal Test Conference,Charlotte,NC,USA,September 30-October 2,2003.