一种由被测电路自己施加测试矢量的BIST方法研究
摘要
集成电路(Integrated Circuit,IC)测试开销很高的原因,一方面是因为大多数IC本身就非常复杂;另一方面是由于IC设计人员往往只对IC的功能需求感兴趣,没有对IC的可测性给予足够的重视。因此,IC生产出来以后常常很难被测试,需要使用十分昂贵的测试仪和很长的测试时间。解决测试问题的一个好办法是使用可测性设计(Design for Testability, DFT),即在对IC进行设计的同时就考虑对它的测试问题,使得IC生产出来以后比较容易地被测试。内建自测试(Build-In Self-Test,BIST)就是一种重要和常用的可测性设计技术。
BIST方案的关键在于测试矢量生成器(Test-Pattern Generator,TPG)的设计。两种典型的TPG分别是基于线性反馈移位寄存器(Linear Feedback Shift Register,LFSR)的伪随机TPG和基于只读存储器(Read Only Memory,ROM)的储存式TPG。这两种方式各有优缺点,因此经常被结合起来使用。
本文在阐述了数字电路测试基本理论以及可测性设计的常见策略的基础上,针对当前BIST方案中存在的问题,提出了一种由被测电路自己施加测试矢量(简称TPAC)的BIST方法。该方法适用于组合电路以及全扫描结构下的时序电路。在TPAC中,被测电路不仅仅被看作测试的对象,同时也是一种可利用的资源。通过将被测电路中的一些内部节点“反馈”连接到被测电路的原始输入端,该方法可以实现由被测电路自己生成并施加测试矢量,从而提高BIST的性能。这种利用反馈进行测试生成的策略也是TPAC方法与其他BIST方法主要的不同之处。
本文详细说明了TPAC方法的基本思想并介绍了在测试矢量生成,测试施加以及测试响应分析各个测试阶段与传统BIST方法的异同。针对不同的测试矢量集,本文提出了三种不同的TPAC实施策略:完全反馈,分组完全反馈以及一般反馈。此外,为了便于算法实现,本文还给出了TPAC方法的数学描述。用ISCAS85电路和MinTest给出的测试集进行的模拟实验结果表明TPAC与Golomb编码压缩方案相比平均可节约95%的存储空间,与LFSR重播种和LFSR结合硬件映射的方法相比可节约54%的测试矢量长度,同时还具有较高的故障覆盖率。
关于TPAC方法的研究本文仅仅算是一个开头。相信这种面积开销小,生成的测试矢量长度短,即测试时间短的BIST方法一定会有比较好的研究前景。
The cost for testing the modern Integrated Circuit (IC) is usually very high. This is because of the complexity of ICs themselves and less attention paid by the designers who are usually interested in IC’s functions. So, the test of IC is, generally speaking, very difficult and needs very expensive testers and long test application time. A good method to address this problem is Design-for-Testability (DFT). The fundamental idea of DFT is to consider the test issue while designing, in order to make the ICs to be tested easily. Build-In Self-Test (BIST) is a kind of most important and widely used DFT technologies.
A proper Test Patten Generator (TPG) is the essential part in any BIST scheme. There are two typical TPGs. One is the pseudo-random TPG based on the Linear Feedback Shift Register (LFSR) and the other is memory TPG based on the Read Only Memory (ROM). These two methods have their own advantages and disadvantages; therefore, they are often combined to meet a balance between the performance and the cost.
On the basis of introducing the principle of digital circuit testing and the common strategy of DFT, we propose a BIST scheme using test patterns applied by Circuit-under-Test (referred to as TPAC) itself for combination circuits or full-scanned sequential circuits. In this approach, CUTs are no longer only regarded as test objects, but also a sort of available resources. By feedback connecting some of the interior nodes to the primary inputs, TPAC can generate and apply the next input vector by CUT itself, so as to improve the performance of the BIST. The test generation method using“feedback strategy”is the main difference between TPAC and the other BIST approaches.
In this paper, we expound the basic idea of TPAC, and the similarities and differences between traditional BISTs and TPAC in the various stages of test procedure including test pattern generation, test application and response analysis. In additional, we propose three TPAC strategies: Entire-Feedback, Group-Entire-Feedback and General- Feedback for various CUTs and their test set. Furthermore, a mathematical description for TPAC is presented. The experimental results on the ISCAS85 circuits and MinTest test set demonstrate that the proposed scheme not only can achieve almost 100% single stuck-at fault coverage, but also has an average 54% decrease in test data volume compared with LFSR reseeding approaches.
Our current works are very infantile and it is just a beginning of TPAC researching. We believed that this method will have a wide research foreground because of its low area overhead and short test length (that is less test application time).
BIST方案的关键在于测试矢量生成器(Test-Pattern Generator,TPG)的设计。两种典型的TPG分别是基于线性反馈移位寄存器(Linear Feedback Shift Register,LFSR)的伪随机TPG和基于只读存储器(Read Only Memory,ROM)的储存式TPG。这两种方式各有优缺点,因此经常被结合起来使用。
本文在阐述了数字电路测试基本理论以及可测性设计的常见策略的基础上,针对当前BIST方案中存在的问题,提出了一种由被测电路自己施加测试矢量(简称TPAC)的BIST方法。该方法适用于组合电路以及全扫描结构下的时序电路。在TPAC中,被测电路不仅仅被看作测试的对象,同时也是一种可利用的资源。通过将被测电路中的一些内部节点“反馈”连接到被测电路的原始输入端,该方法可以实现由被测电路自己生成并施加测试矢量,从而提高BIST的性能。这种利用反馈进行测试生成的策略也是TPAC方法与其他BIST方法主要的不同之处。
本文详细说明了TPAC方法的基本思想并介绍了在测试矢量生成,测试施加以及测试响应分析各个测试阶段与传统BIST方法的异同。针对不同的测试矢量集,本文提出了三种不同的TPAC实施策略:完全反馈,分组完全反馈以及一般反馈。此外,为了便于算法实现,本文还给出了TPAC方法的数学描述。用ISCAS85电路和MinTest给出的测试集进行的模拟实验结果表明TPAC与Golomb编码压缩方案相比平均可节约95%的存储空间,与LFSR重播种和LFSR结合硬件映射的方法相比可节约54%的测试矢量长度,同时还具有较高的故障覆盖率。
关于TPAC方法的研究本文仅仅算是一个开头。相信这种面积开销小,生成的测试矢量长度短,即测试时间短的BIST方法一定会有比较好的研究前景。
The cost for testing the modern Integrated Circuit (IC) is usually very high. This is because of the complexity of ICs themselves and less attention paid by the designers who are usually interested in IC’s functions. So, the test of IC is, generally speaking, very difficult and needs very expensive testers and long test application time. A good method to address this problem is Design-for-Testability (DFT). The fundamental idea of DFT is to consider the test issue while designing, in order to make the ICs to be tested easily. Build-In Self-Test (BIST) is a kind of most important and widely used DFT technologies.
A proper Test Patten Generator (TPG) is the essential part in any BIST scheme. There are two typical TPGs. One is the pseudo-random TPG based on the Linear Feedback Shift Register (LFSR) and the other is memory TPG based on the Read Only Memory (ROM). These two methods have their own advantages and disadvantages; therefore, they are often combined to meet a balance between the performance and the cost.
On the basis of introducing the principle of digital circuit testing and the common strategy of DFT, we propose a BIST scheme using test patterns applied by Circuit-under-Test (referred to as TPAC) itself for combination circuits or full-scanned sequential circuits. In this approach, CUTs are no longer only regarded as test objects, but also a sort of available resources. By feedback connecting some of the interior nodes to the primary inputs, TPAC can generate and apply the next input vector by CUT itself, so as to improve the performance of the BIST. The test generation method using“feedback strategy”is the main difference between TPAC and the other BIST approaches.
In this paper, we expound the basic idea of TPAC, and the similarities and differences between traditional BISTs and TPAC in the various stages of test procedure including test pattern generation, test application and response analysis. In additional, we propose three TPAC strategies: Entire-Feedback, Group-Entire-Feedback and General- Feedback for various CUTs and their test set. Furthermore, a mathematical description for TPAC is presented. The experimental results on the ISCAS85 circuits and MinTest test set demonstrate that the proposed scheme not only can achieve almost 100% single stuck-at fault coverage, but also has an average 54% decrease in test data volume compared with LFSR reseeding approaches.
Our current works are very infantile and it is just a beginning of TPAC researching. We believed that this method will have a wide research foreground because of its low area overhead and short test length (that is less test application time).
引文
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[2] Chris Castillo.45nm 节点缺陷检测面临的挑战.半导体制造,2007,4:11-13
[3] Bushnell M L, Agrawal V D 著,蒋安平,冯建华,王新安译.超大规模集成电路测试-数字、存储器和混合信号系统.电子工业出版社,2005:7-11
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[5] 詹友刚,王峰.DFMA 面向制造与装配的设计—并行工程的核心技术.计算机辅助设计与制造,2001,6:70-73
[6] 杨士元.数字系统的故障诊断与可靠性设计.清华大学出版社,2000:7-9
[7] Pomeranz I, Reddy S M.On Generating Tests that Avoid the Detection of Redundant Faults in Synchronous Sequential Circuits with Full Scan.IEEE Trans. on Computers, 2006, 55(4): 491-495
[8] Touba N A.Survey of Test Vector Compression Techniques.IEEE Design & Test of Computers, 2006, July-August: 294-303
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[15] 李杰,李锐,杨军.基于部分扫描的低功耗内建自测试.固体电子学研究与进展,2005,25(1):72-76
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[22] Chen Ming-Jing, Dong Xiang.Pseudorandom scan BIST using improved test point insertion techniques.In: 7th International Conference on Solid-State and Integrated Circuits Technology, 2004. Proceedings, 2004: 2043-2046
[23] Kapur R, Patil S, Snethen T J, et al.Design of an efficient weighted random pattern generation system.In: Proc. Int. Test Conf., 1994: 491-500
[24] Lai L, Patel J H, Rinderknecht T, et al.Hardware efficient LBIST with complementary weights.In: Proc. Int. Conf. on Computer Design, 2005: 479-481
[25] Krishna C V, Touba N A.Reducing Test Data Volume Using LFSR Resseding with Seed Compression.In: International Test Conference, 2002, 11(3): 321-330
[26] Venkataraman S, Rajski J, Hellebrand S, et al.An Efficient BIST scheme Based on Reseeding of Multiple Polynomial Linear Feedback Shift Registers.In: Proc. IEEE/ACM Int.Conf. On Computer-Aided Design, Santa Clara 1993: 572-577
[27] 张建胜,黄维康,唐璞山.变长重复播种测试码生成方法.复旦学报(自然科学版),2006,45(4):517-522
[28] Krishna C V, Jas A, Touba N A.Test vector encoding using partial LFSR reseeding.In: Proc. IEEE Int. Test Conf., 2001: 885-893
[29] Fu Yu-Hsuan, Wang Sying-Jyan . Test Data Compression with Partial LFSR- Reseeding.In: Proc. 14th Asian Test Symposium, 2005: 343-347
[30] Touba N A, McCluskey E J.Transformed pseudo-random patterns for BIST.In: Proc. VLSI Test Symp., 1995: 410–416
[31] Mitrajit Chatterjee, Dhiraj K Pradhan.A BIST Pattern Generator Design for Near-Perfect Fault Coverage.IEEE Transactions on Computers, 2003, 52(12): 1543-1557
[32] Touba N A, McCluskey E J.Bit-fixing in pseudorandom sequences for scan BIST.IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2001, 20(4): 545-555
[33] Lijian Li, Yinghua Min.An efficient BIST design using LFSR-ROM architecture.TestSymposium, 2000 (ATS 2000), Proceedings of the Ninth Asian, 2000: 386-390
[34] Youhua Shi, Zhe Zhang.Multiple test set generation method for LFSR-based BIST.In: ASPDAC: Proceedings of the 2003 conference on Asia South Pacific design automation, 2003, 863-868
[35] Chandra A, Chakrabarty K.System-on-a-chip Test-Data Compression and Decomp- ression Architectures Based on Golomb Codes.IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, 2001, 20(3): 355-268
[36] Chandra A, Chakrabarty K.Test data compression and test resource partitioning for system-on-a-chip using frequency-directed run length (FDR) Codes.IEEE. Trans. on Computer, 2003, 52(8): 1076-1088
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[2] Chris Castillo.45nm 节点缺陷检测面临的挑战.半导体制造,2007,4:11-13
[3] Bushnell M L, Agrawal V D 著,蒋安平,冯建华,王新安译.超大规模集成电路测试-数字、存储器和混合信号系统.电子工业出版社,2005:7-11
[4] Ishida M, Ha D S, Yamaguchi T. CMPACT:A hybrid method for compressing test data.In: Proc. VTS, 1998: 62-69
[5] 詹友刚,王峰.DFMA 面向制造与装配的设计—并行工程的核心技术.计算机辅助设计与制造,2001,6:70-73
[6] 杨士元.数字系统的故障诊断与可靠性设计.清华大学出版社,2000:7-9
[7] Pomeranz I, Reddy S M.On Generating Tests that Avoid the Detection of Redundant Faults in Synchronous Sequential Circuits with Full Scan.IEEE Trans. on Computers, 2006, 55(4): 491-495
[8] Touba N A.Survey of Test Vector Compression Techniques.IEEE Design & Test of Computers, 2006, July-August: 294-303
[9] Roth J P.Diagnosis of Automata Failures: A Calculus and a Method.IBM Journal of Research and Development, 1966, 10(4): 278-291
[10] Goel P.An Implicit Enumeration Algorithm to Generate Tests for Combinatinal Logic Ciruits.IEEE Trans. on Computers, 1981, C-30(3): 215-222
[11] Fujiwara H, Shimono T.On the Acceleration of Test Generation Algorithm.IEEE Trans. on Computer, 1983, C-32(12): 1137- 1144
[12] Ibarra P H, Sahni S K.Polynomially complete fault detection problems.IEEE Trans. on Computer, 1975, 24(3): 242-249
[13] Cheng K-T, Agrawal V D.A partial scan method for sequential circuits with feed- back.IEEE Trans. on Computers, 1990, 39(4): 544-548
[14] Dong Xiang, Patel J H.Partial scan design based on circuit state information and functional analysis. IEEE Trans. on Computers, 2004, 53 (3): 276–287
[15] 李杰,李锐,杨军.基于部分扫描的低功耗内建自测试.固体电子学研究与进展,2005,25(1):72-76
[16] IEEE Stand Test Access Port and Boundary Scan Architecture: IEEE Std 1149.1-2001.IEEE computer Society, 2001
[17] Agrawal V D, Kime C R, Saluja K K.A Tutorial on Built-In-Self-Test, Part1:Principles.IEEE Design&Test of Computers, 1993, 10(1): 73-82
[18] Agrawal V D, Kime C R, Saluja K K.A Tutorial on Built-In-Self-Test, Part12: Application.IEEE Design&Test of Computers, 1993, 10(2): 69-77
[19] Koenemann B, Mucha J, Zwiehoff G.Built-In Test for Complex Digital Integrated Circuits.IEEE Journal of Solid-State Circuits, 1980, SC-15(3): 315-319
[20] Bardell P H, McAnney W H.STUMPS: Self-Testing of Multichip Logic Modules.In: Proc. of the International Test Conf.(ITC), 1982: 200-204
[21] Dufaza C, Cambon G.LFSR-Based Deterministic and Pseudo-random Test Pattern Generator Strctures.In: Proc. of the European Test Conf., 1991: 27-34
[22] Chen Ming-Jing, Dong Xiang.Pseudorandom scan BIST using improved test point insertion techniques.In: 7th International Conference on Solid-State and Integrated Circuits Technology, 2004. Proceedings, 2004: 2043-2046
[23] Kapur R, Patil S, Snethen T J, et al.Design of an efficient weighted random pattern generation system.In: Proc. Int. Test Conf., 1994: 491-500
[24] Lai L, Patel J H, Rinderknecht T, et al.Hardware efficient LBIST with complementary weights.In: Proc. Int. Conf. on Computer Design, 2005: 479-481
[25] Krishna C V, Touba N A.Reducing Test Data Volume Using LFSR Resseding with Seed Compression.In: International Test Conference, 2002, 11(3): 321-330
[26] Venkataraman S, Rajski J, Hellebrand S, et al.An Efficient BIST scheme Based on Reseeding of Multiple Polynomial Linear Feedback Shift Registers.In: Proc. IEEE/ACM Int.Conf. On Computer-Aided Design, Santa Clara 1993: 572-577
[27] 张建胜,黄维康,唐璞山.变长重复播种测试码生成方法.复旦学报(自然科学版),2006,45(4):517-522
[28] Krishna C V, Jas A, Touba N A.Test vector encoding using partial LFSR reseeding.In: Proc. IEEE Int. Test Conf., 2001: 885-893
[29] Fu Yu-Hsuan, Wang Sying-Jyan . Test Data Compression with Partial LFSR- Reseeding.In: Proc. 14th Asian Test Symposium, 2005: 343-347
[30] Touba N A, McCluskey E J.Transformed pseudo-random patterns for BIST.In: Proc. VLSI Test Symp., 1995: 410–416
[31] Mitrajit Chatterjee, Dhiraj K Pradhan.A BIST Pattern Generator Design for Near-Perfect Fault Coverage.IEEE Transactions on Computers, 2003, 52(12): 1543-1557
[32] Touba N A, McCluskey E J.Bit-fixing in pseudorandom sequences for scan BIST.IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2001, 20(4): 545-555
[33] Lijian Li, Yinghua Min.An efficient BIST design using LFSR-ROM architecture.TestSymposium, 2000 (ATS 2000), Proceedings of the Ninth Asian, 2000: 386-390
[34] Youhua Shi, Zhe Zhang.Multiple test set generation method for LFSR-based BIST.In: ASPDAC: Proceedings of the 2003 conference on Asia South Pacific design automation, 2003, 863-868
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