基于FPGA的数字图像处理与SOPC系统的实现
摘要
数字图像处理在国防、安防、监控等关系国家和社会安全的领域应用越来越广泛,早期的数字图像处理主要通过PC机或FPGA+DSP来完成,由于PC机的体积、功耗过大,而用FPGA+DSP处理又相对成本较高、系统实现也较复杂,限制了其在道路监控、小区安防方面的广泛应用。基于FPGA的嵌入式SOPC系统能更好的解决这方面问题,推动了数字图像处理硬件实现的发展。数字图像的旋转、放大、追踪因其在国防、安防、监控中的重要性,受到研发人员的重视,但用纯硬件语言去实现又有很大的复杂性,有些算法写成硬件语言非常困难。在嵌入式SOPC系统中,可以用软件语言实现算法、硬件实现架构,有效的解决了这个问题。
论文的研究内容是在已有的FPGA开发平台上,设计出视频解码模块,把模拟视频解码成数字视频流,并对此数字视频流进行图像处理,从而实现对视频图像的旋转、放大功能,最后通过VGA接口输出所要求的视频图像。
论文讨论了双线性插值算法、最近邻点法,算法的软硬件编程实现;用硬件描述语言进行了系统逻辑架构设计;整个硬件系统和各逻辑模块都用Modelsim进行了仿真验证;完成了整个系统下板调试,并用ChipScope Pro进行了实时信号追踪验证。
Digital image processing is more and more widely used in many fields,such as military,safeguard,monitoring and so on.Early,digital image processing is accomplished by PC or FPGA&DSP.The volume,power dissipation of PC is too big.The cost of FPGA &DSP is high and its system realization is also complicated. Because of these disadvantageous,PC and FPGA&DSP's extensive use in road monitoring and housing estate safety are restricted.The embedded SOPC system based on FPGA resolved these problems,and promote the digital image processing's development.The digital image's revolution,enlarges and tracks is significance in military,safeguard,monitoring.But it is complex to realize them by pure hardware language.And some algorithms translate into hardware language is extraordinary difficulty.In the embedded SOPC system,we can effectively use the advanced language,such as C++,to realize algorithm and the hardware realization frame to resolved the above problem.
This thesis is based on the existing FPGA development platform.The main goal for the thesis was to build a video decoder module to decode the analog video into digital video stream,and processing this digital video stream to implement rotation and scale-up of the video image.Finally,output the required digital video images through VGA interface.
Issues discussed in this report are bilinear interpolation algorithm and nearest adjacent points method,and the implement in software and hardware;constructing the structure of the whole system with hardware description language;the entire system and logic modules are simulation and verification by the Modelsim;the whole system has been downloading to the board,and using ChipScope Pro to debug and real-time track verification.
论文的研究内容是在已有的FPGA开发平台上,设计出视频解码模块,把模拟视频解码成数字视频流,并对此数字视频流进行图像处理,从而实现对视频图像的旋转、放大功能,最后通过VGA接口输出所要求的视频图像。
论文讨论了双线性插值算法、最近邻点法,算法的软硬件编程实现;用硬件描述语言进行了系统逻辑架构设计;整个硬件系统和各逻辑模块都用Modelsim进行了仿真验证;完成了整个系统下板调试,并用ChipScope Pro进行了实时信号追踪验证。
Digital image processing is more and more widely used in many fields,such as military,safeguard,monitoring and so on.Early,digital image processing is accomplished by PC or FPGA&DSP.The volume,power dissipation of PC is too big.The cost of FPGA &DSP is high and its system realization is also complicated. Because of these disadvantageous,PC and FPGA&DSP's extensive use in road monitoring and housing estate safety are restricted.The embedded SOPC system based on FPGA resolved these problems,and promote the digital image processing's development.The digital image's revolution,enlarges and tracks is significance in military,safeguard,monitoring.But it is complex to realize them by pure hardware language.And some algorithms translate into hardware language is extraordinary difficulty.In the embedded SOPC system,we can effectively use the advanced language,such as C++,to realize algorithm and the hardware realization frame to resolved the above problem.
This thesis is based on the existing FPGA development platform.The main goal for the thesis was to build a video decoder module to decode the analog video into digital video stream,and processing this digital video stream to implement rotation and scale-up of the video image.Finally,output the required digital video images through VGA interface.
Issues discussed in this report are bilinear interpolation algorithm and nearest adjacent points method,and the implement in software and hardware;constructing the structure of the whole system with hardware description language;the entire system and logic modules are simulation and verification by the Modelsim;the whole system has been downloading to the board,and using ChipScope Pro to debug and real-time track verification.
引文
[1]王城,薛小刚,钟信潮.FPGA/CPLD设计工具ISE5.x使用详解.北京:人民邮电出版,2003.6
[2]徐欣,于红旗,易凡等.基于FPGA的嵌入式系统设计.北京:机械工业出版社,2004.9
[3]任晓东,文博.CPLD/FPGA高级应用开发指南.北京:电子工业出版社,2003.6
[4]吴继华,王诚.Altera FPGA/CPLD设计(高级篇).北京:人民邮电出版社,2005.7
[5]http://www.eetchina.com/ART_8800319890_865371_eb652a66.HTM.德州仪器公司Robert Oshana
[6]http://www.FPGA.com.cn/advance/structures/lut.htm
[7][美]Michael D.Ciletti.Verilog HDL高级数字设计.北京:电子工业出版社,2005.1
[8]http://www.eetchina.com/ART_8800314844_617703_9c1f4bbl.HTM作者:Geoff Hoekstra National Instruments
[9]http://www.eetchina.com/ART_8800360714_617685_5692ee8b.HTM
[10]Uwe Meyer-Baese.数字信号处理的FPGA实现.北京:清华大学出版社,2003.1
[11]http://www.eetchina.com/ART_8800360714_617685_5692ee8b.HTM;作者:Rodger Hosking和Richard Kuenzler Pentek公司
[12]发Yao Wang,Jorn Ostemann,Ya-Qin Zhang.视频处理与通信.北京:电子工业出版社,2003.6
[13][美]Keith Jack.Video Demystified Third Edition--A Hand Book for Digital Engineer.LLH Technology Publishing,2001
[14]Rec.ITU-R BT.656-3
[15]http://www-inst.eecs.berkeley.edu/-cs150/sp05
[16]Sophocles J.Orfanidis.Introduction to Signal Processing.北京:清华大学出版社,Prentice Hall出版公司,1998.12
[17]Philips Semiconductors I~2C Handbook 2000
[18]John L.Hennessy,David A.Patterson.Computer Architecture:A Quantitatire Approach(Third Edition.北京:中国机械出版社,2004
[19]Jan M.Rabacy,Anantha Chandrakasan,Borivoje Nikolic.Digital Integrated Circuits A Design Perspective(second edition).北京:清华大学出版社,2004
[20]THE I 2C-BUS SPECIFICATION VERSION 2.1 JANUARY 2000
[21]http://www.FPGA.com.cn/application/a175.htm.Xilinx公司Arthur Yang
[22]Xilinx rogrammable Logic Data Book,1999.
[23]Spartan-3 FPGA Family:Complete Data Sheet Product Specification.Philips Semiconductors.2005 Auf 19
[24]Spartan-Ⅱ 2.5V FPGA Family:Complete Data Sheet ProductSpecification.Philips Semiconductors.2004 Auf 2
[25]Device Documentation.http://www.altera.com/literature/lit-ip.jsp
[26]ITU-RBT.656-4standard.Available:http://www/itu.int/itudoc/itur/rec/bt
[27]Brown S,and Rose J,'Architecture of FPGAs and CPLDs:ATutorial',IEEE Design and Test of Computers,Vol.13,No.2,pp.42-57,1996.
[28]Xilinx Ltd.,'Virtex 2.5 V Field Programmable Gate Arrays -Product Specification',1999.http://www.xilinx.com/products/virtex
[29]Real Time Image Processing based on FPGA Hardware Acceleration.Steffen Klupsch,Markus Ernst research center Caesar center of advanced European studies and research Friedensplatz 16,53111 Bonn
[30]Designing Digital Signal Processing with FPGAs.MentorGraphics.Feb 2003
[31]Digital Video Decoder/Encoder Module Systenm:ENCMOD03+I~2C Interfacing Application Note.Philips Electronics N.V.1997
[32]Anil K.Jain,"Fundamentals of digital image processing," New Jersey:Prentice-Hall,1989,pp.253-255.
[33]Maheshwari R.,Rao S.S.S.P.,and Poonacha P.G.,"FPGA implementation of median filter," Tenth International Conference on VLSI Design,June,1997,pp.523-524.
[34]H.T.Kung and R.L.Picard,"Hardware Pipelines for Multi-Dimensional Convolution and Resampling," IEEE Computer Society Workshop on Computer Architecture for Pattern Analysis and Image Database Management,IEEE Computer Society Press,November,1981,pp.273- 278.
[35]Crookes D,Benkrid K,Bouridane A,Alotaib K.,and BenkridA,"Design and implementation of a high level programming environment for FPGA-based image processing," Vision,Image and Signal Processing,IEE Proceedings,vol.147,Issue:4,Aug,2000,pp.377 -384.
[36]XilinxProductSelectionGuides.http://www.xilinx.com/literature/index.h
[37]Benkrid K.,Crookes D.,and Benkrid A.,"Towards ageneral framework for FPGA based image processing using hardware skeleton," Parallel Computing vol.28,Issue:7-8,Aug,2002,pp.1141-1154.
[38]L.Shang,A.Kaviani,and K.Bathala,"Dynamic power consumption in Virtex-ⅡFPGA family," in Proc.ACM Int.Symp.Field-Programmable Gate Arrays,Monterey,CA,Feb.2002,pp.157-164
[39]E.Kusse and J.Rabaey,"Low-energy embedded FPGA structures," inProc.Int.Symp.Low Power Electronics and Design,Monterey,CA,Aug.1998,pp.155-160.
[40]A.Singh and M.Marek-Sadowska,"Efficient circuit clustering for area and power reduction," in Proc.ACM Int.Symp.Field-Programmable Gate Arrays,Monterey,CA,Feb.2002,pp.59-66.
[41]J.H.Anderson and F.N.Najm,"Low-power programmable routing circuitry for FPGAs," in Proc.Int.Conf.Computer-Aided Design,San Jose,CA,Nov.2004,pp.602-607.
[42]王城,薛小刚,钟信潮.FPGA/CPLD设计工具ISE6.0使用详解.北京:人民邮电出版,2005.1
[43]K.Poon,A.Yan,and S.Wilton,"A flexible power model for FPGAs," in Proc.12th Int.Conf.Field-Programmable Logic and Applications,Montpellier,France,Sep.2002,pp.312-321.
[44][美]Samir Palnitkar.Verilog HDL数字设计与综合(第二版).北京:电子工业出版社.2004.11
[45]T.Tuan and B.Lai,"Leakage power analysis of a 90 nm FPGA," in Proc.IEEE Custom Integrated Circuits Conf.,San Jose,CA,2003,pp.57-60.
[46]E.Ahmed and J.Rose,"The effect of LUT and cluster size on deep-submicron FPGA performance and density," in Proc.ACM Int.Symp.Field-Programmable Gate Arrays,Monterey,CA,Feb.2000,pp.3-12.
[47][美]Michael Keating,Pierre Bricaud.片上系统:可重用设计方法学(第三版).北京:电子工业出版社,2004.05
[48]Bailey D H,Barszcz E,Dagum L,and Simon H D,'NAS Parallel Benchmark Results',The IEEE Parallel and Distributed TechnologyJournal,pp 43-51,Feb 1993.
[49]Akiyama T,Aono H,Aoki K,et al,'MPEG2 video codec using Image compression DSP',IEEE Transactions on Consumer Electronics,Vol 40,No 3,pp 466-472,1994.
[50]Driscoll Tand Walker C,Evolution of Image-Processing algorithms from software to hardware',Proceedings of the society of photo-optical instrumentation engineers,Vol.271,pp.43-50,1981.
[2]徐欣,于红旗,易凡等.基于FPGA的嵌入式系统设计
[3]任晓东,文博.CPLD/FPGA高级应用开发指南.北京:电子工业出版社,2003.6
[4]吴继华,王诚.Altera FPGA/CPLD设计(高级篇).北京:人民邮电出版社,2005.7
[5]http://www.eetchina.com/ART_8800319890_865371_eb652a66.HTM.德州仪器公司Robert Oshana
[6]http://www.FPGA.com.cn/advance/structures/lut.htm
[7][美]Michael D.Ciletti.Verilog HDL高级数字设计.北京:电子工业出版社,2005.1
[8]http://www.eetchina.com/ART_8800314844_617703_9c1f4bbl.HTM作者:Geoff Hoekstra National Instruments
[9]http://www.eetchina.com/ART_8800360714_617685_5692ee8b.HTM
[10]Uwe Meyer-Baese.数字信号处理的FPGA实现.北京:清华大学出版社,2003.1
[11]http://www.eetchina.com/ART_8800360714_617685_5692ee8b.HTM;作者:Rodger Hosking和Richard Kuenzler Pentek公司
[12]发Yao Wang,Jorn Ostemann,Ya-Qin Zhang.视频处理与通信.北京:电子工业出版社,2003.6
[13][美]Keith Jack.Video Demystified Third Edition--A Hand Book for Digital Engineer.LLH Technology Publishing,2001
[14]Rec.ITU-R BT.656-3
[15]http://www-inst.eecs.berkeley.edu/-cs150/sp05
[16]Sophocles J.Orfanidis.Introduction to Signal Processing.北京:清华大学出版社,Prentice Hall出版公司,1998.12
[17]Philips Semiconductors I~2C Handbook 2000
[18]John L.Hennessy,David A.Patterson.Computer Architecture:A Quantitatire Approach(Third Edition.北京:中国机械出版社,2004
[19]Jan M.Rabacy,Anantha Chandrakasan,Borivoje Nikolic.Digital Integrated Circuits A Design Perspective(second edition).北京:清华大学出版社,2004
[20]THE I 2C-BUS SPECIFICATION VERSION 2.1 JANUARY 2000
[21]http://www.FPGA.com.cn/application/a175.htm.Xilinx公司Arthur Yang
[22]Xilinx rogrammable Logic Data Book,1999.
[23]Spartan-3 FPGA Family:Complete Data Sheet Product Specification.Philips Semiconductors.2005 Auf 19
[24]Spartan-Ⅱ 2.5V FPGA Family:Complete Data Sheet ProductSpecification.Philips Semiconductors.2004 Auf 2
[25]Device Documentation.http://www.altera.com/literature/lit-ip.jsp
[26]ITU-RBT.656-4standard.Available:http://www/itu.int/itudoc/itur/rec/bt
[27]Brown S,and Rose J,'Architecture of FPGAs and CPLDs:ATutorial',IEEE Design and Test of Computers,Vol.13,No.2,pp.42-57,1996.
[28]Xilinx Ltd.,'Virtex 2.5 V Field Programmable Gate Arrays -Product Specification',1999.http://www.xilinx.com/products/virtex
[29]Real Time Image Processing based on FPGA Hardware Acceleration.Steffen Klupsch,Markus Ernst research center Caesar center of advanced European studies and research Friedensplatz 16,53111 Bonn
[30]Designing Digital Signal Processing with FPGAs.MentorGraphics.Feb 2003
[31]Digital Video Decoder/Encoder Module Systenm:ENCMOD03+I~2C Interfacing Application Note.Philips Electronics N.V.1997
[32]Anil K.Jain,"Fundamentals of digital image processing," New Jersey:Prentice-Hall,1989,pp.253-255.
[33]Maheshwari R.,Rao S.S.S.P.,and Poonacha P.G.,"FPGA implementation of median filter," Tenth International Conference on VLSI Design,June,1997,pp.523-524.
[34]H.T.Kung and R.L.Picard,"Hardware Pipelines for Multi-Dimensional Convolution and Resampling," IEEE Computer Society Workshop on Computer Architecture for Pattern Analysis and Image Database Management,IEEE Computer Society Press,November,1981,pp.273- 278.
[35]Crookes D,Benkrid K,Bouridane A,Alotaib K.,and BenkridA,"Design and implementation of a high level programming environment for FPGA-based image processing," Vision,Image and Signal Processing,IEE Proceedings,vol.147,Issue:4,Aug,2000,pp.377 -384.
[36]XilinxProductSelectionGuides.http://www.xilinx.com/literature/index.h
[37]Benkrid K.,Crookes D.,and Benkrid A.,"Towards ageneral framework for FPGA based image processing using hardware skeleton," Parallel Computing vol.28,Issue:7-8,Aug,2002,pp.1141-1154.
[38]L.Shang,A.Kaviani,and K.Bathala,"Dynamic power consumption in Virtex-ⅡFPGA family," in Proc.ACM Int.Symp.Field-Programmable Gate Arrays,Monterey,CA,Feb.2002,pp.157-164
[39]E.Kusse and J.Rabaey,"Low-energy embedded FPGA structures," inProc.Int.Symp.Low Power Electronics and Design,Monterey,CA,Aug.1998,pp.155-160.
[40]A.Singh and M.Marek-Sadowska,"Efficient circuit clustering for area and power reduction," in Proc.ACM Int.Symp.Field-Programmable Gate Arrays,Monterey,CA,Feb.2002,pp.59-66.
[41]J.H.Anderson and F.N.Najm,"Low-power programmable routing circuitry for FPGAs," in Proc.Int.Conf.Computer-Aided Design,San Jose,CA,Nov.2004,pp.602-607.
[42]王城,薛小刚,钟信潮.FPGA/CPLD设计工具ISE6.0使用详解.北京:人民邮电出版,2005.1
[43]K.Poon,A.Yan,and S.Wilton,"A flexible power model for FPGAs," in Proc.12th Int.Conf.Field-Programmable Logic and Applications,Montpellier,France,Sep.2002,pp.312-321.
[44][美]Samir Palnitkar.Verilog HDL数字设计与综合(第二版).北京:电子工业出版社.2004.11
[45]T.Tuan and B.Lai,"Leakage power analysis of a 90 nm FPGA," in Proc.IEEE Custom Integrated Circuits Conf.,San Jose,CA,2003,pp.57-60.
[46]E.Ahmed and J.Rose,"The effect of LUT and cluster size on deep-submicron FPGA performance and density," in Proc.ACM Int.Symp.Field-Programmable Gate Arrays,Monterey,CA,Feb.2000,pp.3-12.
[47][美]Michael Keating,Pierre Bricaud.片上系统:可重用设计方法学(第三版).北京:电子工业出版社,2004.05
[48]Bailey D H,Barszcz E,Dagum L,and Simon H D,'NAS Parallel Benchmark Results',The IEEE Parallel and Distributed TechnologyJournal,pp 43-51,Feb 1993.
[49]Akiyama T,Aono H,Aoki K,et al,'MPEG2 video codec using Image compression DSP',IEEE Transactions on Consumer Electronics,Vol 40,No 3,pp 466-472,1994.
[50]Driscoll Tand Walker C,Evolution of Image-Processing algorithms from software to hardware',Proceedings of the society of photo-optical instrumentation engineers,Vol.271,pp.43-50,1981.