基于8086单芯片计算机外设IP软核设计技术的研究
|
摘要
ITRS预计到2010年时半导体工艺技术将进入45纳米阶段,单个芯片可以集成数十亿计的晶体管。基于这种技术发展的趋势,单台PC机的全部电路(显示器和键盘除外)都可以集成到一块芯片实现单芯片计算机。本论文工作围绕基于8086的单芯片计算机最小集项目开展研究,采用IP/SoC的设计方法,设计了最小集中两个重要的外设IP电路—可编程外围接口IP与可编程外围定时/计数器IP,并实现了这两个IP分别与8255和8254芯片指令集兼容,最后实现了两个IP在单芯片计算机平台中的集成验证。
为了增加整个芯片平台的可测性与可调试性,本论文讨论了目前流行的边界扫描测试技术,设计了边界扫描测试电路—JTAG调试模块,增强了芯片的可测试性与可调试性。
实验结果显示,两个外围IP与JTAG调试模块都能很好的满足设计的要求。
主要工作和取得的成果如下:
1)探讨了一种基于8086 CPU核的单芯片计算机平台的架构,设计两款外围接口IP软核a8255和a8254,并对其进行IP独立验证,实现基于8086单芯片计算机平台的最小集搭建;
2)设计基于IEEE 1149.1标准的JTAG调试模块,为单芯片计算机提供测试与调试端口。
ITRS expected that semiconductor technology scale would enter 45-nanometer era in the year of 2010 and more than one billion transistors would be integrated into a Single chip.According to this trend,all circuit modules(except monitor and keyboard)of single PC can be integrated in a chip,which is the single-chip computer.The research in this thesis is based on the project of the minimum set of 8086-based Single-Chip PC.In this paper the author adopted the IP/SoC design methodology and designed two important peripheral IPs-programmable peripheral interface a8255 IP and programmable peripheral interval timer a8254 IP.These two IPs are fully instruction-level compatible with 8255 chip and 8254 chip.Then the integration verification of them into a single-chip computer platform is realized.
In order to increase testability and debuggability of the platform,this paper also discussed boundary-scan technique and designed the boundary-scan circuit-JTAG debugging module.
The experimental results show that both the two peripheral IPs and JTAG debug module can well meet the design requirements.
The main work and achievements are as follows:
1)A kind of 8086 CPU-based single-PC platform architecture is discussed and design of two peripheral IP cores a8255 and a8254 are implemented.Independent functional verification of them and it integration into the minimum set of Single-Chip PC platform is also discussed;
2)Design of JTAG debug module based on IEEE 1149.1 standard is presented to afford test and debug interface for Single-Chip PC.
为了增加整个芯片平台的可测性与可调试性,本论文讨论了目前流行的边界扫描测试技术,设计了边界扫描测试电路—JTAG调试模块,增强了芯片的可测试性与可调试性。
实验结果显示,两个外围IP与JTAG调试模块都能很好的满足设计的要求。
主要工作和取得的成果如下:
1)探讨了一种基于8086 CPU核的单芯片计算机平台的架构,设计两款外围接口IP软核a8255和a8254,并对其进行IP独立验证,实现基于8086单芯片计算机平台的最小集搭建;
2)设计基于IEEE 1149.1标准的JTAG调试模块,为单芯片计算机提供测试与调试端口。
ITRS expected that semiconductor technology scale would enter 45-nanometer era in the year of 2010 and more than one billion transistors would be integrated into a Single chip.According to this trend,all circuit modules(except monitor and keyboard)of single PC can be integrated in a chip,which is the single-chip computer.The research in this thesis is based on the project of the minimum set of 8086-based Single-Chip PC.In this paper the author adopted the IP/SoC design methodology and designed two important peripheral IPs-programmable peripheral interface a8255 IP and programmable peripheral interval timer a8254 IP.These two IPs are fully instruction-level compatible with 8255 chip and 8254 chip.Then the integration verification of them into a single-chip computer platform is realized.
In order to increase testability and debuggability of the platform,this paper also discussed boundary-scan technique and designed the boundary-scan circuit-JTAG debugging module.
The experimental results show that both the two peripheral IPs and JTAG debug module can well meet the design requirements.
The main work and achievements are as follows:
1)A kind of 8086 CPU-based single-PC platform architecture is discussed and design of two peripheral IP cores a8255 and a8254 are implemented.Independent functional verification of them and it integration into the minimum set of Single-Chip PC platform is also discussed;
2)Design of JTAG debug module based on IEEE 1149.1 standard is presented to afford test and debug interface for Single-Chip PC.
引文
[1]http://www.rz.gov.cn/kjjy/kxts/20040513082430.htm
[2]杨之廉、申明,超大规模集成电路设计方法学导论(第二版).北京:清华大学出版社,1999.
[3]Gordon Moore,Electronic Materials Symposium Santa Clara,CA.March 1998.
[4]李丽,集成电路设计方法及IP设计技术的研究.合肥工业大学博士论文,2002年11月.
[5]Altizer B,Platform-based design:the next reuse frontier[A].Embedded Systems Conference[C].San Francisco:ESC Press,2002.
[6]Sangiovanni-Vincentelli.A,Carloni.L,De Bernardinis.F,benefits and challenges for platform-based design,Design Automation Conference,2004 proceedings.
[7]http://www2.ccw.com.cn/1998/47/172806.shtml
[8][美]基延(Keating.M.)、Bricaud.P著;沈戈、罗曼、张欣等译.片上系统.可重用设计方法学(第3版)[M].北京:电子工业出版社,2004.
[9]范学峰、杨燕琴著;微型计算机原理与应用-Intel 8086/8088[M].上海:同济大学出版社,1996.
[10]喻宗泉著;80X86微机原理与接口技术[M].西安:西安电子科技大学出版社,2005年1月
[11][美]Barry B.Brey著;The Intel Microprocessors Ar-chitecture,Programming,and Interfacing(Sixth Edition).2004.
[12]吴秀清、周荷琴著;微型计算机原理与接口技术(第2版)[M].合肥:中国科学技术大学出版社,2001.
[13]蒋本珊、欧阳春生著;常用可编程外围接口芯片使用指南[M].北京:北京理工大学出版社,1994年5月.
[14]陆鑫等编著;微机原理与接口技术[M].北京:机械工业出版社,2005年8月.
[15]Mentor,Graphics,Corporation;m8255_pd.pdf,m8255_ps.pdf,m8255_pu.pdf.02/98MW UG-40062.004-FC,Copyright 1996-1998.
[16]Intel,programmable peripheral interface 8255A[Z],1982.
[17]Lech Znamirowski etc,Programmable Analog/Digital Arrays in Control and Simulation[J].Analog Integrated Circuits and Signal Processing,2004.
[18]Mentor,Graphics,Corporation;m8254_pd.pdf,m8254_ps.pdf,m8254_pu.pdf.0298MWUG-40062.004-FC,Copyright 1996-1998.
[19]IL-Gu LEE,Seung-Beom LEE and Sin-Chong PARK,"Effective co-verification of IEEE 802.11 a MAC/PHY combining emulation and simulation technology,"ANSS'05.
[20]Paterson P R P、Singh L;系统芯片(SoC)验证方法与技术[M].孙海平、丁健译.北京:电子工业出版社,2005.
[21]Bob Altizer,Platform-based design,the next reuse frontier,Embedded Systems Conference,San Francisco,2002.
[22]Keutzer,K.Newton,A.R.Rabaey,J.M.Sangiovanni-Vincentelli,A.,System-level-design:ort hogonalizatin of concerns and platform-based deisn,IEEE Transactions on Computer-Aided Design,December 2000.
[23]孟庆、何乐年等,基于事务的SoC验证策略,半导体技术,第27卷第6期,2002年.
[24]Michael Keating、Pierre Bricaud,Reuse Methodology Manual for System-on-a-Chip Designs,Third Edition,2002.
[25]李亚民著,计算机组成与系统结构.北京:清华大学出版社,2000年4月.
[26]William Stallings著,Computer Organization & Architecture:Design for Performance.Prentice Hall,1999年9月.
[27]夏宇闻著,复杂系统数字电路与系统的Verilog HDL设计技术.北京:北京航空航天大学出版社,1998.
[28]Bob Zeidman著,Verilog Designer's Library.Prentice Hall PTR,1999.
[29]Victor P.Nelson,H.Troy Nagle著,Digital Logic Circuit Analysis&Design,Prentice Hall,1997年12月.
[30]Xiong Zhihui,Research on techniques of platform-based SoC hardware/software co-design[D].Changsha:National University of Defense Technology,2004.
[31]章立生,韩承德;SoC芯片设计方法及标准化[J].计算机研究与发展,2002.
[32]Amold S.Applying hardware/software co-design to system-on-a-chip[M].IEEE,1998.
[33][美]Rochit Rajsuman著,于敦山、盛世敏、田泽译;System-on-a-Chip:Design and Test[M].北京:北京航空航天大学出版社,2003.
[34]王田苗,嵌入式系统设计与实例开发(第2版)[M].北京:清华大学出版社,2003.
[35][美]基延(Keating.M.)、Bricaud.P著;沈戈、罗曼、张欣等译.片上系统—可重用设计方法学(第3版)[M].北京:电子工业出版社,2004.
[36]陈光禹、潘中良可测性设计技术[M].北京:电子工业出版社,1997.
[37]IEEE Standard 1149.1-2001.Standard Test Access Port and Boundary-scan Architecture [S].IEEE Standards Board,2001.
[38][美]Ciletti.M.D著;张雅绮、李锵译.Verilog HDL高级数字设计[M].北京:电子工业出版社,2005.
[39]雷绍充、邵志标、梁峰.VLSI测试方法学和可测性设计[M].北京:电子工业出社,2005.
[40]Application Note 28:The ARM7TDMI Debug Architecture.2004.
[41]Turbo86 and Turbo186 Synthesizable HDL Cores Reference.REV2.5,2005.
[42]ARC Turbo186 Prototyping System Reference.2005.
[2]杨之廉、申明,超大规模集成电路设计方法学导论(第二版).北京:清华大学出版社,1999.
[3]Gordon Moore,Electronic Materials Symposium Santa Clara,CA.March 1998.
[4]李丽,集成电路设计方法及IP设计技术的研究.合肥工业大学博士论文,2002年11月.
[5]Altizer B,Platform-based design:the next reuse frontier[A].Embedded Systems Conference[C].San Francisco:ESC Press,2002.
[6]Sangiovanni-Vincentelli.A,Carloni.L,De Bernardinis.F,benefits and challenges for platform-based design,Design Automation Conference,2004 proceedings.
[7]http://www2.ccw.com.cn/1998/47/172806.shtml
[8][美]基延(Keating.M.)、Bricaud.P著;沈戈、罗曼、张欣等译.片上系统.可重用设计方法学(第3版)[M].北京:电子工业出版社,2004.
[9]范学峰、杨燕琴著;微型计算机原理与应用-Intel 8086/8088[M].上海:同济大学出版社,1996.
[10]喻宗泉著;80X86微机原理与接口技术[M].西安:西安电子科技大学出版社,2005年1月
[11][美]Barry B.Brey著;The Intel Microprocessors Ar-chitecture,Programming,and Interfacing(Sixth Edition).2004.
[12]吴秀清、周荷琴著;微型计算机原理与接口技术(第2版)[M].合肥:中国科学技术大学出版社,2001.
[13]蒋本珊、欧阳春生著;常用可编程外围接口芯片使用指南[M].北京:北京理工大学出版社,1994年5月.
[14]陆鑫等编著;微机原理与接口技术[M].北京:机械工业出版社,2005年8月.
[15]Mentor,Graphics,Corporation;m8255_pd.pdf,m8255_ps.pdf,m8255_pu.pdf.02/98MW UG-40062.004-FC,Copyright 1996-1998.
[16]Intel,programmable peripheral interface 8255A[Z],1982.
[17]Lech Znamirowski etc,Programmable Analog/Digital Arrays in Control and Simulation[J].Analog Integrated Circuits and Signal Processing,2004.
[18]Mentor,Graphics,Corporation;m8254_pd.pdf,m8254_ps.pdf,m8254_pu.pdf.0298MWUG-40062.004-FC,Copyright 1996-1998.
[19]IL-Gu LEE,Seung-Beom LEE and Sin-Chong PARK,"Effective co-verification of IEEE 802.11 a MAC/PHY combining emulation and simulation technology,"ANSS'05.
[20]Paterson P R P、Singh L;系统芯片(SoC)验证方法与技术[M].孙海平、丁健译.北京:电子工业出版社,2005.
[21]Bob Altizer,Platform-based design,the next reuse frontier,Embedded Systems Conference,San Francisco,2002.
[22]Keutzer,K.Newton,A.R.Rabaey,J.M.Sangiovanni-Vincentelli,A.,System-level-design:ort hogonalizatin of concerns and platform-based deisn,IEEE Transactions on Computer-Aided Design,December 2000.
[23]孟庆、何乐年等,基于事务的SoC验证策略,半导体技术,第27卷第6期,2002年.
[24]Michael Keating、Pierre Bricaud,Reuse Methodology Manual for System-on-a-Chip Designs,Third Edition,2002.
[25]李亚民著,计算机组成与系统结构.北京:清华大学出版社,2000年4月.
[26]William Stallings著,Computer Organization & Architecture:Design for Performance.Prentice Hall,1999年9月.
[27]夏宇闻著,复杂系统数字电路与系统的Verilog HDL设计技术.北京:北京航空航天大学出版社,1998.
[28]Bob Zeidman著,Verilog Designer's Library.Prentice Hall PTR,1999.
[29]Victor P.Nelson,H.Troy Nagle著,Digital Logic Circuit Analysis&Design,Prentice Hall,1997年12月.
[30]Xiong Zhihui,Research on techniques of platform-based SoC hardware/software co-design[D].Changsha:National University of Defense Technology,2004.
[31]章立生,韩承德;SoC芯片设计方法及标准化[J].计算机研究与发展,2002.
[32]Amold S.Applying hardware/software co-design to system-on-a-chip[M].IEEE,1998.
[33][美]Rochit Rajsuman著,于敦山、盛世敏、田泽译;System-on-a-Chip:Design and Test[M].北京:北京航空航天大学出版社,2003.
[34]王田苗,嵌入式系统设计与实例开发(第2版)[M].北京:清华大学出版社,2003.
[35][美]基延(Keating.M.)、Bricaud.P著;沈戈、罗曼、张欣等译.片上系统—可重用设计方法学(第3版)[M].北京:电子工业出版社,2004.
[36]陈光禹、潘中良可测性设计技术[M].北京:电子工业出版社,1997.
[37]IEEE Standard 1149.1-2001.Standard Test Access Port and Boundary-scan Architecture [S].IEEE Standards Board,2001.
[38][美]Ciletti.M.D著;张雅绮、李锵译.Verilog HDL高级数字设计[M].北京:电子工业出版社,2005.
[39]雷绍充、邵志标、梁峰.VLSI测试方法学和可测性设计[M].北京:电子工业出社,2005.
[40]Application Note 28:The ARM7TDMI Debug Architecture.2004.
[41]Turbo86 and Turbo186 Synthesizable HDL Cores Reference.REV2.5,2005.
[42]ARC Turbo186 Prototyping System Reference.2005.