射频集成低噪声放大器的分析与设计
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摘要
过去十年间,全球移动通信产业经历了前所未有的发展。CMOS工艺虽然直到最近才开始被考虑,但是如今正成为产业界的主流工艺。例如,在90nm工艺条件下,晶体管的截止频率已经高于100 GHz。这就给射频工程师提供了很多的选择余地。CMOS工艺在高频时主要的问题在于较低的跨导值以及信号通过导电率较低的硅衬底的损耗。
射频集成电路的一个主要应用在于无线局域网(WLAN)。现今最流行的三个WLAN标准是IEEE 802.11a,802.11b和802.11g。802.11a标准制定于1999年,它工作于5 GHz无须申请的美国国家信息基础设施(UNII)频段。UNII频段包括两个子频段:5.15到5.35 GHz,以及5.725到5.825 GHz,两个子频段总共提供300 MHz带宽以及12个每个20 MHz的信道。
本论文主要针对5.2 GHz 802.11a WLAN标准设计射频前端低噪声放大器。低噪声放大器的设计包括很多不同指标间的折衷,例如增益,噪声系数,功耗,以及输入输出阻抗匹配。关于低噪声放大器噪声以及线性度的分析将分别在第四章和第五章给出。区别于常见的幂级数分析法分析低噪声放大器线性度,这里将采用Volterra级数分析法,考虑了高频时电容以及电感的记忆性对低噪声放大器线性度的影响。最终设计的低噪声放大器噪声系数为1.35dB,输入三阶交调遮断点IIP3为7.392 dBm,增益为13.8 dB,功耗为14 mW。该低噪声放大器使用Agilent EEsof的Advanced Design System 2006A软件仿真。
During the last decade, mobile communication has experienced an enormous growth. CMOS technology, which has not been considered for commercial RF applications until recently, is becoming a commercially viable manufacturing option. For example, with the 90-nm CMOS technology, transit frequencies well over 100 GHz are achieved. This offers a comfortable frequency margin for RF designers. The major problems of CMOS technology at high frequencies are the low transconductance and signal loss through the conducting silicon substrate.
One of the main applications of Radio frequency Integrated Circuits is for the wireless local area network (WLAN). The three popular WLAN standards in use today are based on the IEEE 802.11a, 802.11b and 802.11g specifications. The 802.11a standard, which was ratified in 1999, operates in the 5-GHz unlicensed national information infrastructure (UNII) band. The UNII band consists of two subbands: 5.15 to 5.35 GHz, and 5.725 to 5.825 GHz, which together provide a total bandwidth of 300 MHz and offer 12 nonoverlapping data channels of 20 MHz each.
This thesis focuses on designing low-noise-amplifier (LNA) for the use of 5.2 GHz WLAN. The LNA design involves trade-offs between many figures of merits, such as gain, noise, power, impedance matching, stability, and linearity. The analysis of the noise and linearity performance of basic LNA topology will be detailed separated in Chapter four and five and the design procedure will be given in Chapter six. Besides, Volterra series approach was given for the analysis of the linearity of LNA considering the memory effects of the capacitors and the inductors. The LNA achieve low NF of 1.35 dB, the input-referred third order intercept point (IIP3) of 7.392 dBm, 13.8 dB gain with 14 mW power consumption. The simulation was done with Agilent EEsof Advanced Design System 2006A.
射频集成电路的一个主要应用在于无线局域网(WLAN)。现今最流行的三个WLAN标准是IEEE 802.11a,802.11b和802.11g。802.11a标准制定于1999年,它工作于5 GHz无须申请的美国国家信息基础设施(UNII)频段。UNII频段包括两个子频段:5.15到5.35 GHz,以及5.725到5.825 GHz,两个子频段总共提供300 MHz带宽以及12个每个20 MHz的信道。
本论文主要针对5.2 GHz 802.11a WLAN标准设计射频前端低噪声放大器。低噪声放大器的设计包括很多不同指标间的折衷,例如增益,噪声系数,功耗,以及输入输出阻抗匹配。关于低噪声放大器噪声以及线性度的分析将分别在第四章和第五章给出。区别于常见的幂级数分析法分析低噪声放大器线性度,这里将采用Volterra级数分析法,考虑了高频时电容以及电感的记忆性对低噪声放大器线性度的影响。最终设计的低噪声放大器噪声系数为1.35dB,输入三阶交调遮断点IIP3为7.392 dBm,增益为13.8 dB,功耗为14 mW。该低噪声放大器使用Agilent EEsof的Advanced Design System 2006A软件仿真。
During the last decade, mobile communication has experienced an enormous growth. CMOS technology, which has not been considered for commercial RF applications until recently, is becoming a commercially viable manufacturing option. For example, with the 90-nm CMOS technology, transit frequencies well over 100 GHz are achieved. This offers a comfortable frequency margin for RF designers. The major problems of CMOS technology at high frequencies are the low transconductance and signal loss through the conducting silicon substrate.
One of the main applications of Radio frequency Integrated Circuits is for the wireless local area network (WLAN). The three popular WLAN standards in use today are based on the IEEE 802.11a, 802.11b and 802.11g specifications. The 802.11a standard, which was ratified in 1999, operates in the 5-GHz unlicensed national information infrastructure (UNII) band. The UNII band consists of two subbands: 5.15 to 5.35 GHz, and 5.725 to 5.825 GHz, which together provide a total bandwidth of 300 MHz and offer 12 nonoverlapping data channels of 20 MHz each.
This thesis focuses on designing low-noise-amplifier (LNA) for the use of 5.2 GHz WLAN. The LNA design involves trade-offs between many figures of merits, such as gain, noise, power, impedance matching, stability, and linearity. The analysis of the noise and linearity performance of basic LNA topology will be detailed separated in Chapter four and five and the design procedure will be given in Chapter six. Besides, Volterra series approach was given for the analysis of the linearity of LNA considering the memory effects of the capacitors and the inductors. The LNA achieve low NF of 1.35 dB, the input-referred third order intercept point (IIP3) of 7.392 dBm, 13.8 dB gain with 14 mW power consumption. The simulation was done with Agilent EEsof Advanced Design System 2006A.
引文
[1]Ryuichi Fujimoto,Kenji Kojima,Shoji Otaka.A 7-GHz 1.8-dB NF CMOS Low-Noise Amplifier.IEEE Journal of Solid-State Circuits,2002,37(7):852-856.
[2]Vladimir Aparin,Lawrence E.Larson.Modified Derivative Superposition Method for Linearzing FET Low-Noise Amplifiers.IEEE Transactions on Microwave Theory and Techniques,2005,53(2):571-581.
[3]Namsoo Kim,Vladimir Aparin,Kenneth Barnett.A cellular-Band CDMA 0.25-um CMOS LNA Linearized Using Active Post-Distortion.IEEE Journal of Solid-State Circuits,2006,41(7):1530-1534.
[4]Sivakumuar Ganesan,Edgar Sanchez-Sinencio,Jose Silva-Martinez.A Highly Linear Low-Noise Amplifier.IEEE Transactions on Microwave Theory and Techniques,2006,54(11):4079-4085.
[5]Yongwang Ding,Ramesh Harjani.A+18dbm IIP3 LNA in 0.35-um CMOS.International Solid-State Circuit conference of Year 2001.
[6]Paul Leroux,Johan Janssens,Michiel Steyaert.A 0.8-dB NF ESD-Protected 9-mW CMOS LNA Operating at 1.23 GHz.IEEE Journal of Solid-State Circuits,2002,37(6):760-765.
[7]Trung-Kien Nguyen,Chung-Hwan Kim.CMOS Low-Noise Amplifier Design Optimization Techniques.IEEE Transactions on Microwave Theory and Techniques,2004,52(5):1433-1442.
[8]李志升,李巍,胡嘉盛,等.1.9 GHz CMOS低噪声放大器的结构分析与设计.微电子学,2006,36(4):220-224.
[9]姚飞,成步文.1 GHz 0.5um CMOS低噪声放大器的设计.半导体学报,2004,25(10):1291-1295.
[10]Feng Dong,Shi Bingxue.CMOS Dual-Band Low Noise Amplifier.半导体学报,2004,25(9):1055-1060.
[11]肖珺,李永明,王志华.低功耗CMOS低噪声放大器的设计.微电子学,2006,36(10):670-678.
[12]胡小丽,吴秀山.低频、低功耗CMOS LNA的设计优化技术.中国计量学院学,2006,17(10):305-309.
[13]戴广豪,李文杰,王生荣,等.一种新型2.4 GHz SiGe BiCMOS低噪声放大器.微电子学,2006,36(10):580-583.
[14]桑泽华,李永明.一种用于超宽带系统的宽带LNA的设计.微电子学,2006,36(2):114-117.
[15]廖有春,唐长文,闵昊.一种用于电视调谐器的宽带CMOS低噪声放大器设计.半导体学报,2006,27(11):2029-2034.
[16]池保勇,石秉学,王志华.应用于IEEE 802.11b无线局域网系统的2.4 GHz CMOS单片收发机射频前端.半导体学报,2005,26(9):1731-1739.
[17]JAZZ SBC35(SiGe60) Design Manual.
[18]H.T.Friis.Noise Figures of Radio Receivers.Proceeding of IRE,1944,32(7):419-422.
[19]G.Gonzalez.Microwave Transistor Amplifier:Analysis and Design(Second Edition).New York,USA:Prentice Hall,1997.
[20]EE142 Lecture Notes,UC Berkeley,Fall 2005 by Ali Niknejad.
[21]Behzad Razavi.RF Microelectronics.Prentice Hall,1997.
[22]Thomas H.Lee.The Design of CMOS Radio-Frequency Integrated Circuits(Second Edition).England.Cambridge:Cambridge University Press,2004.
[23]EE240 Lecture Notes,UC Berkeley,Spring 2006 by Ali Niknejad.
[24]BSIM4 Manual,on line at http://www-device.eecs.berkeley.edu/～bsim3/bsim4_get.html.
[25]Nuntachai Poobuapheun[Master thesis].A Prototype Broadband CMOS LNA for Universal Radio Receivers.UC Berkeley.
[26]Richard Lu[Master thesis].CMOS Low Noise Amplifier Design for Wireless Sensor Networks.UC Berkeley.
[27]Derek K.Shaeffer,Thomas H.Lee.A 1.5-V 1.5-GHz CMOS Low-Noise Amplifier.IEEE Journal of Solid-State Circuits,1997,32(5):745-759.
[28]Josef Zipper,Claus Stoger,Guenot Herber.A Single-Chip Dual-Band CDMA 2000Transceiver in 0.13 um CMOS.IEEE Journal of Solid-State Circuits,2007,42(12):2785-2794.
[29]Pete Sivonen,Aarno Parssinen.Analysis and Optimization of Packaged Inductively Degenerated Common-Source Low-Noise Amplifiers with ESD Protection.IEEE Transactions on Microwave Theroy and Techniques,2005,53(4):1304-1313.
[30]Keng Leong Fong,Robert G.Meyer.Monolithic RF Active Mixer Design.IEEE Transactions on Circuits and Systems,1999,46(3):231-239.
[31]EE242 Lecture Notes,UC Berkeley,Spring 2007 by Ali Niknejad.
[32]Joel Vuolevi,Timo Rahkonen.Distortion in RF Power amplifiers.Boston London,Artech House,2003.
[33]Piet Wambacq,Willy Sansen.Distortion Analysis of Analog Integrated Circuits.Boston London,Kluwer Academic Publisher 1998.
[34]Wilson J.Rugh.Nonlinear System Theory-The Volterra/Wiener Approach.
[35]Pietro Andreani,Herik Sjoland.Noise Optimization of an Inductively Degenerated CMOS Low-Noise Amplifier.IEEE Transactions on Circuits and Systems,2001,48(9):835-841.
[36]B.Kim,J.-S.Ko,K.Lee.A new linearization technique for MOSFET RF amplifier using multiple gated transistors.IEEE Microwave and Guided Wave Lett,2000,10(9):371-373.
[37]Paul R.Gray,Paul J.Hurst,Stephen H.Lewis.Analysis and Design of Analog Integrated Circuits(4th Edition).USA:John Wiley & Sons,Inc.2001.
[38]H.A.Haus,W.R.Atkinson.Representation of Noise in Linear Twoports.Proceedings of the IRE,1960,20(1):69-74.
[39]John Rogers,Calvin Plett.Radio Frequency Integrated Circuit Design.Boston.London,Artech House.2003.
[40][美]Reinhold Ludwig,Pavel Bretchko著.王子宇等译.射频电路设计——理论与应用.北京:电子工业出版社,2002.
[41]Hung-Wei Chiu,Shey-Shi Lu.A 2.17-dB NF 5-GHz-Band Monolithic CMOS LNA with 10-mW DC Power Consumption.IEEE Transactions on Microwave Theory and Techniques,2006,53(3):813-824.
[42]Sundaram Narayanan.Intermodulation Distortion of Cascaded Transistor.IEEE Journal of Solid-State Circuits,1969,4(3):97-106.
[43]Giovanni Girlando,Giuseppe Palmisano.Noise Figure and Impedance Matching in RF Cascode Amplifiers.IEEE Transactions on Circuits and Systems,1999,46(11):1388-1396.
[44]Keng Leong Fong.High-Frequency Analysis of Linearity Improvement Technique of Common-Emitter Transconductance Stage Using a Low-Frequency-Trap Network.IEEE Journal of Solid-State Circuits,2000,35(8):1249-1252.
[45]Jung-Suk Goo[PHD thesis].High Frequency Noise in CMOS Low Noise Amplifiers.August 2001,Stanford University.
[46]Trond Ytterdal,Yuhua Cheng,Tor A.Fjeldly Device Modeling for Analog and RF CMOS Circuit Design,2003 John Wiley&Sons.Ltd.
[2]Vladimir Aparin,Lawrence E.Larson.Modified Derivative Superposition Method for Linearzing FET Low-Noise Amplifiers.IEEE Transactions on Microwave Theory and Techniques,2005,53(2):571-581.
[3]Namsoo Kim,Vladimir Aparin,Kenneth Barnett.A cellular-Band CDMA 0.25-um CMOS LNA Linearized Using Active Post-Distortion.IEEE Journal of Solid-State Circuits,2006,41(7):1530-1534.
[4]Sivakumuar Ganesan,Edgar Sanchez-Sinencio,Jose Silva-Martinez.A Highly Linear Low-Noise Amplifier.IEEE Transactions on Microwave Theory and Techniques,2006,54(11):4079-4085.
[5]Yongwang Ding,Ramesh Harjani.A+18dbm IIP3 LNA in 0.35-um CMOS.International Solid-State Circuit conference of Year 2001.
[6]Paul Leroux,Johan Janssens,Michiel Steyaert.A 0.8-dB NF ESD-Protected 9-mW CMOS LNA Operating at 1.23 GHz.IEEE Journal of Solid-State Circuits,2002,37(6):760-765.
[7]Trung-Kien Nguyen,Chung-Hwan Kim.CMOS Low-Noise Amplifier Design Optimization Techniques.IEEE Transactions on Microwave Theory and Techniques,2004,52(5):1433-1442.
[8]李志升,李巍,胡嘉盛,等.1.9 GHz CMOS低噪声放大器的结构分析与设计.微电子学,2006,36(4):220-224.
[9]姚飞,成步文.1 GHz 0.5um CMOS低噪声放大器的设计.半导体学报,2004,25(10):1291-1295.
[10]Feng Dong,Shi Bingxue.CMOS Dual-Band Low Noise Amplifier.半导体学报,2004,25(9):1055-1060.
[11]肖珺,李永明,王志华.低功耗CMOS低噪声放大器的设计.微电子学,2006,36(10):670-678.
[12]胡小丽,吴秀山.低频、低功耗CMOS LNA的设计优化技术.中国计量学院学,2006,17(10):305-309.
[13]戴广豪,李文杰,王生荣,等.一种新型2.4 GHz SiGe BiCMOS低噪声放大器.微电子学,2006,36(10):580-583.
[14]桑泽华,李永明.一种用于超宽带系统的宽带LNA的设计.微电子学,2006,36(2):114-117.
[15]廖有春,唐长文,闵昊.一种用于电视调谐器的宽带CMOS低噪声放大器设计.半导体学报,2006,27(11):2029-2034.
[16]池保勇,石秉学,王志华.应用于IEEE 802.11b无线局域网系统的2.4 GHz CMOS单片收发机射频前端.半导体学报,2005,26(9):1731-1739.
[17]JAZZ SBC35(SiGe60) Design Manual.
[18]H.T.Friis.Noise Figures of Radio Receivers.Proceeding of IRE,1944,32(7):419-422.
[19]G.Gonzalez.Microwave Transistor Amplifier:Analysis and Design(Second Edition).New York,USA:Prentice Hall,1997.
[20]EE142 Lecture Notes,UC Berkeley,Fall 2005 by Ali Niknejad.
[21]Behzad Razavi.RF Microelectronics.Prentice Hall,1997.
[22]Thomas H.Lee.The Design of CMOS Radio-Frequency Integrated Circuits(Second Edition).England.Cambridge:Cambridge University Press,2004.
[23]EE240 Lecture Notes,UC Berkeley,Spring 2006 by Ali Niknejad.
[24]BSIM4 Manual,on line at http://www-device.eecs.berkeley.edu/～bsim3/bsim4_get.html.
[25]Nuntachai Poobuapheun[Master thesis].A Prototype Broadband CMOS LNA for Universal Radio Receivers.UC Berkeley.
[26]Richard Lu[Master thesis].CMOS Low Noise Amplifier Design for Wireless Sensor Networks.UC Berkeley.
[27]Derek K.Shaeffer,Thomas H.Lee.A 1.5-V 1.5-GHz CMOS Low-Noise Amplifier.IEEE Journal of Solid-State Circuits,1997,32(5):745-759.
[28]Josef Zipper,Claus Stoger,Guenot Herber.A Single-Chip Dual-Band CDMA 2000Transceiver in 0.13 um CMOS.IEEE Journal of Solid-State Circuits,2007,42(12):2785-2794.
[29]Pete Sivonen,Aarno Parssinen.Analysis and Optimization of Packaged Inductively Degenerated Common-Source Low-Noise Amplifiers with ESD Protection.IEEE Transactions on Microwave Theroy and Techniques,2005,53(4):1304-1313.
[30]Keng Leong Fong,Robert G.Meyer.Monolithic RF Active Mixer Design.IEEE Transactions on Circuits and Systems,1999,46(3):231-239.
[31]EE242 Lecture Notes,UC Berkeley,Spring 2007 by Ali Niknejad.
[32]Joel Vuolevi,Timo Rahkonen.Distortion in RF Power amplifiers.Boston London,Artech House,2003.
[33]Piet Wambacq,Willy Sansen.Distortion Analysis of Analog Integrated Circuits.Boston London,Kluwer Academic Publisher 1998.
[34]Wilson J.Rugh.Nonlinear System Theory-The Volterra/Wiener Approach.
[35]Pietro Andreani,Herik Sjoland.Noise Optimization of an Inductively Degenerated CMOS Low-Noise Amplifier.IEEE Transactions on Circuits and Systems,2001,48(9):835-841.
[36]B.Kim,J.-S.Ko,K.Lee.A new linearization technique for MOSFET RF amplifier using multiple gated transistors.IEEE Microwave and Guided Wave Lett,2000,10(9):371-373.
[37]Paul R.Gray,Paul J.Hurst,Stephen H.Lewis.Analysis and Design of Analog Integrated Circuits(4th Edition).USA:John Wiley & Sons,Inc.2001.
[38]H.A.Haus,W.R.Atkinson.Representation of Noise in Linear Twoports.Proceedings of the IRE,1960,20(1):69-74.
[39]John Rogers,Calvin Plett.Radio Frequency Integrated Circuit Design.Boston.London,Artech House.2003.
[40][美]Reinhold Ludwig,Pavel Bretchko著.王子宇等译.射频电路设计——理论与应用.北京:电子工业出版社,2002.
[41]Hung-Wei Chiu,Shey-Shi Lu.A 2.17-dB NF 5-GHz-Band Monolithic CMOS LNA with 10-mW DC Power Consumption.IEEE Transactions on Microwave Theory and Techniques,2006,53(3):813-824.
[42]Sundaram Narayanan.Intermodulation Distortion of Cascaded Transistor.IEEE Journal of Solid-State Circuits,1969,4(3):97-106.
[43]Giovanni Girlando,Giuseppe Palmisano.Noise Figure and Impedance Matching in RF Cascode Amplifiers.IEEE Transactions on Circuits and Systems,1999,46(11):1388-1396.
[44]Keng Leong Fong.High-Frequency Analysis of Linearity Improvement Technique of Common-Emitter Transconductance Stage Using a Low-Frequency-Trap Network.IEEE Journal of Solid-State Circuits,2000,35(8):1249-1252.
[45]Jung-Suk Goo[PHD thesis].High Frequency Noise in CMOS Low Noise Amplifiers.August 2001,Stanford University.
[46]Trond Ytterdal,Yuhua Cheng,Tor A.Fjeldly Device Modeling for Analog and RF CMOS Circuit Design,2003 John Wiley&Sons.Ltd.