基于IEC 61850过程总线结构的数字化保护系统性能研究
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摘要
基于IEC 61850过程总线结构的数字化继电保护系统是数字化变电站综合自动化系统的重要体系之一,其性能优劣直接影响到电网的安全性和稳定性。过程总线结构数字化保护系统一般由常规/非常规互感器NCIT (Non-conventional Instrument Transformer)、合并单元MU (Merging Unit)、以太网交换机(Ethernet Switch)、保护智能电子装置IED (Intelligent Electronic Device)、同步时钟源(Time Synchronisation Source)、断路器控制器(Breaker Controller)等构成。IEC61850-9-2定义的过程总线,实现了互感器或合并单元与间隔层设备如保护IED、间隔层控制器、测量仪表等的数字化连接,是一次系统和二次系统的桥梁。不同的过程总线组网结构和过程层采样值通信的时间同步精度对数字化保护系统的性能有直接影响,与NCIT并列运行的常规电流互感器(CT)饱和现象对电流差动保护的影响也必须解决。因此,研究上述各种问题对基于过程总线结构的数字化保护系统性能的影响及解决方案具有重要的理论价值和实际意义,本工作是英国国家电网NG (National Grid)、法国阿海珐公司(Areva)、苏格兰电力公司(Scottish Power)等联合资助的基金项目的重要内容,由作者在英国曼彻斯特大学的国家电网电力系统研究中心完成。
本文引入最小径集、灵敏度分析、三阶差分等方法并借助统计学工具,对基于过程总线结构的数字化保护系统的性能进行了深入研究,为英国国家电网公司设计了过程总线组网应用方案,过程层采样值精准时间同步实现方案和新型数字化保护系统模型及性能测试方案,开发了电流差动保护CT饱和检测程序,并应用于工程实际,取得的创新性成果和主要研究工作如下：
1、建立了基于过程总线结构的六种数字化保护系统模型,应用可靠性框图和最小径集算法,求解各模型可靠性数据并进行灵敏度分析,得出最优模型和设备重要度优先级序列。
过程总线的组网方案有星型拓扑、总线拓扑、环形拓扑、网状拓扑等,不同的组网方案对数字化保护系统的可靠性有重要影响。通过分析各方案的优缺点,基于国际主流设备制造商的过程总线数字化保护系统实现方案,为英国匡家电网设计了通用型过程总线组网方案、适用于双母线接线变电站和网格型接线变电站的过程总线组网方案。从功能冗余角度,提出了六种基于过程总线结构的数字化保护系统模型,建立可靠性框图并借助最小径集算法求解各模型的可靠性。由于系统各元件的可靠性数据源于设备制造商和电网运营商的经验值而非实际统计所得,采用两组灵敏度分析工具来研究原始数据不准确或发生变化时最优解的稳定性,得到各设备对保护系统可靠性的影响,确定元件重要度优先级排序,对优化系统投资计划和指导系统维护及故障检修有重要指导作用。
2、针对数字化保护系统过程层采样值SV (Sampled Values)亚微秒级时间同步精度的要求,提出了三种合并单元时间同步模型,分别适用于灵敏度补偿系统、常规互感器和非常规互感器并列运行系统和分布式母线保护系统。将“乒乓”原理同步算法应用于合并单元同步,得出算法执行后的合并单元时钟漂移特性和采样值相角差；提出预测算法应对GPS信号丢失；对基于主从时钟算法的IEEE 1588 V2精准时钟同步协议,提出“主时钟群”概念并采用“民主”算法提高其主时钟故障时的可用率；结合实际工程,引入透明时钟概念,将支持IEEE1588 V2的RuggedCOM RSG 2288以太网交换机应用于过程层组网,确保过程层时间同步的可靠性和精确性。
3、应用OMICRON CMC测试仪和RTDS (Real Time Digital Simulator),开发了新型过程总线结构数字化保护的性能测试系统。研究了IEC 61850对保护系统测试的影响,采用OMICRON CMC测试仪的IEC 61850测试工具和IRIG-B接口单元,设计了支持IEEE 1588 V2过程层时间同步的数字化保护测试系统,实现冗余时间源机制,提高了时间同步(亚微秒级)的可靠性和准确性。与原方案(5个保护柜各需一个GPS天线)相比节省了3套GPS天线及相应的P594同步单元,实现降低成本和简化接线的目的。同时,该测试方案修改扩展灵活,可替换其他厂家的合并单元和保护IED进行设备兼容性和互操作性测试,实现设备的“即插即测”,充分体现和利用了数字化保护系统的优势。开发了两套基于RTDS的合并单元测试方案,通过对OMICRON与RTDS测试方案的对比,提出测试工具的最优选择标准。
4、针对英国国家电网的网格角型接线变电站(Mesh Corner)的运行特点,应用Areva MiCOM系列保护IED,在英国曼彻斯特大学国家电网电力系统研究中心为其建立了由5个保护柜组成的完整保护系统,包括全数字化网格角母线保护柜、全数字化变压器高/低压侧保护柜、馈线近网格角全数字化保护A柜和远端常规硬接线保护B柜。引入统计学工具,针对常规保护系统性能测试参数的不足,提出了一系列适用于该保护系统性能测试的独立参数、相对参数、兼容性和互操作性参数等指标,综合考虑保护系统的整体性能测试和单个设备的性能测试,同时兼顾设备兼容性和互操作性参数,并开发了适用于不同保护配置的测试执行方案,为量化统计分析该新型数字化保护系统的性能参数提供了高效有力的工具。
5、针对本项目CT饱和对馈线B柜的常规硬接线电流差动保护的影响,引入CT二次侧感应电压变化率等判据对原三阶差分CT饱和检测算法进行改进。原算法采用CT二次电流三阶差分的模极大值串检测CT饱和,灵敏度较高但容易发生识别错误,抗噪声能力弱,且后续检测结果对前期检测结果依赖性强易导致检测结果无效,稳定性无法满足实际要求。改进算法克服了原三阶差分检测法的不足,且运算量小,便于实时实现。DigSILENT (DIgital SImuLation and Electrical NeTwork calculation program)仿真结果表明,该方法实用有效,提高了CT饱和检测的准确性和稳定性,有效避免了常规硬接线电流差动保护IED因CT饱和引起的误动、拒动或延时动作等问题。
Digital protection systems based on process bus architecture play a very important role in the application of Digital Substation Automation System (SAS); their performance directly affects power system security and stability. Process bus-based digital protection system generally consists of Conventional/Non-conventional Instrument Transformer (NCIT), Merging Unit (MU), Ethernet Switch, Protective IED (Intelligent Electronic Device), Time Synchronisation Source, Breaker Controller, etc. The process bus defined in IEC 61850-9-2 works as a bridge between primary and secondary systems. It enables the use of a digital link between current/voltage transformers or merging units (MUs) and bay devices such as protective relays, bay controllers or meters. Different process bus architectures and time synchronisation accuracy of process bus communication have great impact on the performance of digital protection systems, the problems caused by saturation of conventional CT for current differential protections which may operate in conjunction with NCIT must be solved as well. Consequently, it is of vital theoretical and practical importance to study the impact and solutions of the aforementioned factors on the performance of protection systems with IEC 61850-9-2 process bus architecture in digital substations. The work summarised in this thesis is also the important content of the project entitled "Protection Performance Study for Secondary Systems with IEC61850 Process Bus Architecture". This project is co-funded by the National Grid Company, U.K., Areva T&D, France, Scottish Power, U.K., Scottish and Southern Energy, U.K. etc and finished by the author in the National Grid Power System Research Centre (NGPSRC) at The University of Manchester.
By utilising the minimal tie sets method, sensitivity analysis, the third order difference method and some statistical tools, the performance of protection systems with IEC 61850-9-2 process bus architecture in digital substations under various conditions are evaluated and solutions are given. Novel performance testing schemes for the digital protection systems are developed and applied in the project, a CT saturation detection algorithm for use in current differential protection is proposed as well. The innovative achievements and main works of the thesis are as follows:
1、Six alternative digital protection system models are proposed based on process bus architecture. Reliability block diagrams are built to assess the functionality of each system and system reliability is calculated using the minimal tie sets method. Sensitivity analysis is carried out on the results to obtain the optimal system architecture and priority ranking of devices.
There are four types of general protection system architectures based on process bus:star topology, bus topology, ring topology and mesh topology. The choices of different process bus architectures affect the reliability of protection systems directly. By analysing the pros and cons of different architectures and evaluating the proposed process bus solutions of world-leading manufactures, generic process bus architecture, double busbar substation process bus architecture and mesh substation process bus architecture are designed for NG substations. Six alternative process bus based protection system models are proposed from a component redundancy perspective. The functionality of each system is assessed using reliability block diagrams based on a success-oriented network. System reliability is calculated using the minimal tie sets method determined by the connection matrix. The input data used to calculate the system reliability are based mainly on engineers'experience and judgement rather than on a systematic measurement and collection process. Sensitivity analysis is used to determine the sensitivity of the results to variations in this input data. It was carried out using two approaches; one highlights those components with the greatest impact on system reliability and the other the importance of the task performed by each component in terms of how it affects the functionality of the system. This type of sensitivity approach is useful, not only to determine which components are likely to contribute most to an increase in system performance if their reliabilities are improved, but also to devise ways in which the architecture of the system can be modified to reduce the dominating effect of certain components on the system performance. The results and conclusions can assist both utilities and manufacturers in understanding alternative IEC 61850 process bus architectures and how they affect the performance of protection systems, so that educated and substantiated decisions can be made regarding system design, implementation and maintenance.
2、Considering the 1μs time synchronisation accuracy requirements of the Sampled Values transmitted via process bus, three alternative time synchronisation scenarios of MU for different applications in digital protection systems are proposed. They are designed for systems with the characteristics like:parallel line compensation where the synchronisation is between two independent MUs located in two bays; the bay device has a local sampling of conventional CT and VT to be synchronised with the data of the MU or via a technique which time correlates the output to the sampled input data and distributed busbar protection respectively. A "Ping-Pong" principle based synchronisation algorithm applied to a decentralised busbar protection scheme and a differential line protection scheme is also proposed. The time offset between merging units (MUs) and the phase difference of the sampled values (SVs) after this synch process are analysed in detail. Prediction techniques are proposed to improve reliability in case of loss of the GPS signal. For the master/slave principle based IEEE 1588 Precision Time Protocol (PTP) standard, master group concept and democratic algorithms are proposed to cope with master clock failure. By introducing the Transparent Clock (TC) concept, RuggedCOM RSG 2288 Ethernet Switches are utilised in the project to ensure the reliability and accuracy of time synchronisation for process level communication.
3、Novel performance testing schemes for digital protection systems are developed based on OMICRON test sets and the RTDS (Real Time Digital Simulator). The impact of IEC 61850 on protection testing is investigated; a performance testing scheme supporting IEEE 1588 V2 for process level communication based on OMICRON test set is developed. The scheme can improve the reliability and accuracy of time synchronisation through a redundant time source. This scheme can reduce three GPS antennas and the P594 time synch units compared with the original scheme (five GPS antennas are needed). The gains are simplified wiring, cost reduction and improved time synch reliability and accuracy for SV. Further more, this test scheme can be modified and expanded easily, the Merging Units and protective IEDs can be swapped readily to facilitate compatibility and interoperability tests. All the devices can simply "plug and test" and this demonstrates the advantages of digital protection systems perfectly. Two merging unit testing platforms are developed based on RTDS and the optimal testing device selection criteria can be concluded by comparing the advantages of OMICRON and RTDS based testing schemes.
4、Integrated protection systems are developed in the NGPSRC based on Areva MiCOM protective IEDs. The systems are specially designed for a National Grid mesh topology substation and consist of five panels:digital mesh corner protection panel, Feeder local panel (digital), Feeder remote panel (conventional hardwired), digital transformer LV panel and digital transformer HV panel. A set of performance evaluation indices including absolute/relative and compatibility/interoperability indices are defined. It can be used to evaluate system level and independent component performance. System compatibility and interoperability can also be investigated utilising the schemes. Implementation methodology for performance testing of feeder protection and mesh corner busbar protection is proposed and the proposed schemes and methodology can work as a valuable and effective tool to quantitatively evaluate the performance of the novel protection systems.
5、CT saturation has impact on the performance of the hardwired current differential protection in Feeder remote panel B. An improved CT saturation detection algorithm is developed based on the third order difference method by utilising the rate of change criteria of the CT secondary induced voltage. The algorithm evaluates the start and end of each saturation period using the "largest modulus series"; this is derived from the third order difference function applied to the secondary current. The ratios of the absolute values of the CT secondary induced voltage are also used as criteria to determine when the CT is saturated to reduce the possibility of false detection due to the effect of noise. The algorithm is validated by implementing it in a DigSILENT model of a typical 110kV network and its associated protection. Simulation results obtained for various case studies indicate that the proposed algorithm successfully detects the start/end of CT saturation. It is a reliable algorithm for use in conjunction with the biased current differential relay and can eliminate the maloperation and delayed operation of the relays caused by CT saturation.
本文引入最小径集、灵敏度分析、三阶差分等方法并借助统计学工具,对基于过程总线结构的数字化保护系统的性能进行了深入研究,为英国国家电网公司设计了过程总线组网应用方案,过程层采样值精准时间同步实现方案和新型数字化保护系统模型及性能测试方案,开发了电流差动保护CT饱和检测程序,并应用于工程实际,取得的创新性成果和主要研究工作如下：
1、建立了基于过程总线结构的六种数字化保护系统模型,应用可靠性框图和最小径集算法,求解各模型可靠性数据并进行灵敏度分析,得出最优模型和设备重要度优先级序列。
过程总线的组网方案有星型拓扑、总线拓扑、环形拓扑、网状拓扑等,不同的组网方案对数字化保护系统的可靠性有重要影响。通过分析各方案的优缺点,基于国际主流设备制造商的过程总线数字化保护系统实现方案,为英国匡家电网设计了通用型过程总线组网方案、适用于双母线接线变电站和网格型接线变电站的过程总线组网方案。从功能冗余角度,提出了六种基于过程总线结构的数字化保护系统模型,建立可靠性框图并借助最小径集算法求解各模型的可靠性。由于系统各元件的可靠性数据源于设备制造商和电网运营商的经验值而非实际统计所得,采用两组灵敏度分析工具来研究原始数据不准确或发生变化时最优解的稳定性,得到各设备对保护系统可靠性的影响,确定元件重要度优先级排序,对优化系统投资计划和指导系统维护及故障检修有重要指导作用。
2、针对数字化保护系统过程层采样值SV (Sampled Values)亚微秒级时间同步精度的要求,提出了三种合并单元时间同步模型,分别适用于灵敏度补偿系统、常规互感器和非常规互感器并列运行系统和分布式母线保护系统。将“乒乓”原理同步算法应用于合并单元同步,得出算法执行后的合并单元时钟漂移特性和采样值相角差；提出预测算法应对GPS信号丢失；对基于主从时钟算法的IEEE 1588 V2精准时钟同步协议,提出“主时钟群”概念并采用“民主”算法提高其主时钟故障时的可用率；结合实际工程,引入透明时钟概念,将支持IEEE1588 V2的RuggedCOM RSG 2288以太网交换机应用于过程层组网,确保过程层时间同步的可靠性和精确性。
3、应用OMICRON CMC测试仪和RTDS (Real Time Digital Simulator),开发了新型过程总线结构数字化保护的性能测试系统。研究了IEC 61850对保护系统测试的影响,采用OMICRON CMC测试仪的IEC 61850测试工具和IRIG-B接口单元,设计了支持IEEE 1588 V2过程层时间同步的数字化保护测试系统,实现冗余时间源机制,提高了时间同步(亚微秒级)的可靠性和准确性。与原方案(5个保护柜各需一个GPS天线)相比节省了3套GPS天线及相应的P594同步单元,实现降低成本和简化接线的目的。同时,该测试方案修改扩展灵活,可替换其他厂家的合并单元和保护IED进行设备兼容性和互操作性测试,实现设备的“即插即测”,充分体现和利用了数字化保护系统的优势。开发了两套基于RTDS的合并单元测试方案,通过对OMICRON与RTDS测试方案的对比,提出测试工具的最优选择标准。
4、针对英国国家电网的网格角型接线变电站(Mesh Corner)的运行特点,应用Areva MiCOM系列保护IED,在英国曼彻斯特大学国家电网电力系统研究中心为其建立了由5个保护柜组成的完整保护系统,包括全数字化网格角母线保护柜、全数字化变压器高/低压侧保护柜、馈线近网格角全数字化保护A柜和远端常规硬接线保护B柜。引入统计学工具,针对常规保护系统性能测试参数的不足,提出了一系列适用于该保护系统性能测试的独立参数、相对参数、兼容性和互操作性参数等指标,综合考虑保护系统的整体性能测试和单个设备的性能测试,同时兼顾设备兼容性和互操作性参数,并开发了适用于不同保护配置的测试执行方案,为量化统计分析该新型数字化保护系统的性能参数提供了高效有力的工具。
5、针对本项目CT饱和对馈线B柜的常规硬接线电流差动保护的影响,引入CT二次侧感应电压变化率等判据对原三阶差分CT饱和检测算法进行改进。原算法采用CT二次电流三阶差分的模极大值串检测CT饱和,灵敏度较高但容易发生识别错误,抗噪声能力弱,且后续检测结果对前期检测结果依赖性强易导致检测结果无效,稳定性无法满足实际要求。改进算法克服了原三阶差分检测法的不足,且运算量小,便于实时实现。DigSILENT (DIgital SImuLation and Electrical NeTwork calculation program)仿真结果表明,该方法实用有效,提高了CT饱和检测的准确性和稳定性,有效避免了常规硬接线电流差动保护IED因CT饱和引起的误动、拒动或延时动作等问题。
Digital protection systems based on process bus architecture play a very important role in the application of Digital Substation Automation System (SAS); their performance directly affects power system security and stability. Process bus-based digital protection system generally consists of Conventional/Non-conventional Instrument Transformer (NCIT), Merging Unit (MU), Ethernet Switch, Protective IED (Intelligent Electronic Device), Time Synchronisation Source, Breaker Controller, etc. The process bus defined in IEC 61850-9-2 works as a bridge between primary and secondary systems. It enables the use of a digital link between current/voltage transformers or merging units (MUs) and bay devices such as protective relays, bay controllers or meters. Different process bus architectures and time synchronisation accuracy of process bus communication have great impact on the performance of digital protection systems, the problems caused by saturation of conventional CT for current differential protections which may operate in conjunction with NCIT must be solved as well. Consequently, it is of vital theoretical and practical importance to study the impact and solutions of the aforementioned factors on the performance of protection systems with IEC 61850-9-2 process bus architecture in digital substations. The work summarised in this thesis is also the important content of the project entitled "Protection Performance Study for Secondary Systems with IEC61850 Process Bus Architecture". This project is co-funded by the National Grid Company, U.K., Areva T&D, France, Scottish Power, U.K., Scottish and Southern Energy, U.K. etc and finished by the author in the National Grid Power System Research Centre (NGPSRC) at The University of Manchester.
By utilising the minimal tie sets method, sensitivity analysis, the third order difference method and some statistical tools, the performance of protection systems with IEC 61850-9-2 process bus architecture in digital substations under various conditions are evaluated and solutions are given. Novel performance testing schemes for the digital protection systems are developed and applied in the project, a CT saturation detection algorithm for use in current differential protection is proposed as well. The innovative achievements and main works of the thesis are as follows:
1、Six alternative digital protection system models are proposed based on process bus architecture. Reliability block diagrams are built to assess the functionality of each system and system reliability is calculated using the minimal tie sets method. Sensitivity analysis is carried out on the results to obtain the optimal system architecture and priority ranking of devices.
There are four types of general protection system architectures based on process bus:star topology, bus topology, ring topology and mesh topology. The choices of different process bus architectures affect the reliability of protection systems directly. By analysing the pros and cons of different architectures and evaluating the proposed process bus solutions of world-leading manufactures, generic process bus architecture, double busbar substation process bus architecture and mesh substation process bus architecture are designed for NG substations. Six alternative process bus based protection system models are proposed from a component redundancy perspective. The functionality of each system is assessed using reliability block diagrams based on a success-oriented network. System reliability is calculated using the minimal tie sets method determined by the connection matrix. The input data used to calculate the system reliability are based mainly on engineers'experience and judgement rather than on a systematic measurement and collection process. Sensitivity analysis is used to determine the sensitivity of the results to variations in this input data. It was carried out using two approaches; one highlights those components with the greatest impact on system reliability and the other the importance of the task performed by each component in terms of how it affects the functionality of the system. This type of sensitivity approach is useful, not only to determine which components are likely to contribute most to an increase in system performance if their reliabilities are improved, but also to devise ways in which the architecture of the system can be modified to reduce the dominating effect of certain components on the system performance. The results and conclusions can assist both utilities and manufacturers in understanding alternative IEC 61850 process bus architectures and how they affect the performance of protection systems, so that educated and substantiated decisions can be made regarding system design, implementation and maintenance.
2、Considering the 1μs time synchronisation accuracy requirements of the Sampled Values transmitted via process bus, three alternative time synchronisation scenarios of MU for different applications in digital protection systems are proposed. They are designed for systems with the characteristics like:parallel line compensation where the synchronisation is between two independent MUs located in two bays; the bay device has a local sampling of conventional CT and VT to be synchronised with the data of the MU or via a technique which time correlates the output to the sampled input data and distributed busbar protection respectively. A "Ping-Pong" principle based synchronisation algorithm applied to a decentralised busbar protection scheme and a differential line protection scheme is also proposed. The time offset between merging units (MUs) and the phase difference of the sampled values (SVs) after this synch process are analysed in detail. Prediction techniques are proposed to improve reliability in case of loss of the GPS signal. For the master/slave principle based IEEE 1588 Precision Time Protocol (PTP) standard, master group concept and democratic algorithms are proposed to cope with master clock failure. By introducing the Transparent Clock (TC) concept, RuggedCOM RSG 2288 Ethernet Switches are utilised in the project to ensure the reliability and accuracy of time synchronisation for process level communication.
3、Novel performance testing schemes for digital protection systems are developed based on OMICRON test sets and the RTDS (Real Time Digital Simulator). The impact of IEC 61850 on protection testing is investigated; a performance testing scheme supporting IEEE 1588 V2 for process level communication based on OMICRON test set is developed. The scheme can improve the reliability and accuracy of time synchronisation through a redundant time source. This scheme can reduce three GPS antennas and the P594 time synch units compared with the original scheme (five GPS antennas are needed). The gains are simplified wiring, cost reduction and improved time synch reliability and accuracy for SV. Further more, this test scheme can be modified and expanded easily, the Merging Units and protective IEDs can be swapped readily to facilitate compatibility and interoperability tests. All the devices can simply "plug and test" and this demonstrates the advantages of digital protection systems perfectly. Two merging unit testing platforms are developed based on RTDS and the optimal testing device selection criteria can be concluded by comparing the advantages of OMICRON and RTDS based testing schemes.
4、Integrated protection systems are developed in the NGPSRC based on Areva MiCOM protective IEDs. The systems are specially designed for a National Grid mesh topology substation and consist of five panels:digital mesh corner protection panel, Feeder local panel (digital), Feeder remote panel (conventional hardwired), digital transformer LV panel and digital transformer HV panel. A set of performance evaluation indices including absolute/relative and compatibility/interoperability indices are defined. It can be used to evaluate system level and independent component performance. System compatibility and interoperability can also be investigated utilising the schemes. Implementation methodology for performance testing of feeder protection and mesh corner busbar protection is proposed and the proposed schemes and methodology can work as a valuable and effective tool to quantitatively evaluate the performance of the novel protection systems.
5、CT saturation has impact on the performance of the hardwired current differential protection in Feeder remote panel B. An improved CT saturation detection algorithm is developed based on the third order difference method by utilising the rate of change criteria of the CT secondary induced voltage. The algorithm evaluates the start and end of each saturation period using the "largest modulus series"; this is derived from the third order difference function applied to the secondary current. The ratios of the absolute values of the CT secondary induced voltage are also used as criteria to determine when the CT is saturated to reduce the possibility of false detection due to the effect of noise. The algorithm is validated by implementing it in a DigSILENT model of a typical 110kV network and its associated protection. Simulation results obtained for various case studies indicate that the proposed algorithm successfully detects the start/end of CT saturation. It is a reliable algorithm for use in conjunction with the biased current differential relay and can eliminate the maloperation and delayed operation of the relays caused by CT saturation.
引文
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