网络分析仪频率合成技术的研究
摘要
随着通信技术的发展，射频测量仪器的需求量越来越大，而目前射频测量仪器的现状不容乐观。西方国家的相关产品占领了国内市场的大部分份额，不仅价格昂贵，而且还对一些高端仪器实施禁运，这些严重阻碍了民族工业的发展。在生产线上，需要大量的仪器进行调试工作，在很多场合并不需要太高的精度，如果全部使用国外高端仪器，那是不经济、不合理、也不现实的做法。在这种状况下，迫切需要低成本、指标适中的射频测量仪器。本课题即是为研制网络分析仪中低成本、小体积、细步进锁相扫频源而开展的。
课题的难点是实现低成本、宽频段、细步进的扫频源。目前实现细步进可以采用小数分频和DDS技术，但是小数分频技术比较复杂，杂散大，实现体积也比较大。由于大规模集成电路的发展，已经出现了单片集成的DDS芯片，可以实现细步进，并且跳频时间极快，满足设计要求。但是DDS的输出频率上限较低，而且在宽带输出时杂散比较严重。
本文根据网络分析仪对扫频源的要求，在理论分析的基础上将DDS和PLL相结合，研制出一种细步进、低成本、宽频带的扫频源，输出300kHz～1300MHz的步进为1Hz的扫频信号。系统分为两大部分，一部分实现固定点频2340MHz的产生，另一部分利用DDS+PLL的技术，实现2340.3MHz～3640MHz的步进为1Hz的锁相扫频信号，两路信号混频后产生所需要的300KHz～1300MHz的扫频信号。
实验结果表明，系统的频率分辨率达到1Hz；DDS输出通过锁相环直接倍频，简化了系统的设计，降低了系统成本，并且也满足了所要求的指标。系统整体相位噪声优于-82dBc／H@10kHz，谐波杂散优于-31dBc。
With the development of communication technology, more and more RF measurement instruments are needed. But the status of RF instrument is not good. Western country's products occupy most of the market. These instruments are expensive, what's worse, many of the high precision instruments are prohibited selling to china. National's industry is blocked seriously. On product line, quantity of measurement instruments are needed, in many situations, there's no need for high precision instruments. Using high precision RF instrument is neither economical nor reasonable. So, low cost, good performance RF measurement instruments are needed. This project aim to research low cost, small size and fine resolution phase lock sweep source, which will be used in network analyzer.
The difficulty of this project are realizing low cost, wide frequency band and fine resolution sweep frequency synthesizer. In order to realize fine resolution, fractional-N PLL or DDS technology can be used. But the former technology is more complex, bigger size and worse spur. Due to the development of LSI, we could use single chip DDS to get fine resolution and fast frequency hopping time. But DDS technology's shortcomings include low output frequency and serious spur when output wide band signal.
According to the demand of the network analyzer, this paper analyzed DDS and PLL technique, and then combined them together, developed a type of fine resolution, low cost, wide band sweep source, which output 300KHz~1300MHz sweep signal with 1Hz frequency resolution. System include two main parts: one generates 2340MHz const frequency and the other make use of DDS+PLL technology realizing 2340.3MHZ～3640MHz phase lock signal with 1Hz resolution. Two signal are mixed to generate 300 kHz～1300MHz frequency sweep signal.
Experiment has testified that, system's resolution achieved 1Hz. DDS output signal is multiplied directly, which make the system less complex, and cost lower. System's entire phase noise is better than -82dBc/Hz@10kHz, humorous spur is better than -31dBc.
课题的难点是实现低成本、宽频段、细步进的扫频源。目前实现细步进可以采用小数分频和DDS技术，但是小数分频技术比较复杂，杂散大，实现体积也比较大。由于大规模集成电路的发展，已经出现了单片集成的DDS芯片，可以实现细步进，并且跳频时间极快，满足设计要求。但是DDS的输出频率上限较低，而且在宽带输出时杂散比较严重。
本文根据网络分析仪对扫频源的要求，在理论分析的基础上将DDS和PLL相结合，研制出一种细步进、低成本、宽频带的扫频源，输出300kHz～1300MHz的步进为1Hz的扫频信号。系统分为两大部分，一部分实现固定点频2340MHz的产生，另一部分利用DDS+PLL的技术，实现2340.3MHz～3640MHz的步进为1Hz的锁相扫频信号，两路信号混频后产生所需要的300KHz～1300MHz的扫频信号。
实验结果表明，系统的频率分辨率达到1Hz；DDS输出通过锁相环直接倍频，简化了系统的设计，降低了系统成本，并且也满足了所要求的指标。系统整体相位噪声优于-82dBc／H@10kHz，谐波杂散优于-31dBc。
With the development of communication technology, more and more RF measurement instruments are needed. But the status of RF instrument is not good. Western country's products occupy most of the market. These instruments are expensive, what's worse, many of the high precision instruments are prohibited selling to china. National's industry is blocked seriously. On product line, quantity of measurement instruments are needed, in many situations, there's no need for high precision instruments. Using high precision RF instrument is neither economical nor reasonable. So, low cost, good performance RF measurement instruments are needed. This project aim to research low cost, small size and fine resolution phase lock sweep source, which will be used in network analyzer.
The difficulty of this project are realizing low cost, wide frequency band and fine resolution sweep frequency synthesizer. In order to realize fine resolution, fractional-N PLL or DDS technology can be used. But the former technology is more complex, bigger size and worse spur. Due to the development of LSI, we could use single chip DDS to get fine resolution and fast frequency hopping time. But DDS technology's shortcomings include low output frequency and serious spur when output wide band signal.
According to the demand of the network analyzer, this paper analyzed DDS and PLL technique, and then combined them together, developed a type of fine resolution, low cost, wide band sweep source, which output 300KHz~1300MHz sweep signal with 1Hz frequency resolution. System include two main parts: one generates 2340MHz const frequency and the other make use of DDS+PLL technology realizing 2340.3MHZ～3640MHz phase lock signal with 1Hz resolution. Two signal are mixed to generate 300 kHz～1300MHz frequency sweep signal.
Experiment has testified that, system's resolution achieved 1Hz. DDS output signal is multiplied directly, which make the system less complex, and cost lower. System's entire phase noise is better than -82dBc/Hz@10kHz, humorous spur is better than -31dBc.
引文
[1] 陈宏巍．虚拟标量网络分析仪射频单元设计：[硕士学位论文]．大连海事大学，2006：1~2
[2] 白居宪．低噪声频率合成．西安：西安交通大学出版社，1994：16～17
[3] 高树廷，刘洪升．频率源综述．火控雷达技术，2004，Vol．33，No.1：43～46
[4] 张厥盛，郑继禹等．锁相技术．西安：西安电子科技大学出版社，1992：142～143
[5] 恽小华．现代频率合成技术综述．电子学报，1995，Vol．23，No.10：148～151
[6] Analog Devices, Fractional-N Frequency Synthesizer, ADF4154, Device Datasheet, 2004:6～7
[7] Dean Banerjee, PLL Performance, Simulation, and Design, 3rd Edition, National Semiconductor, 2005: 11～12, 120～122
[8] Donald R. Stephens. Phase-Locked Loops for Wireless Communications. Kluwer Academic Publishers, 2002: 11～19
[9] 庄卉，黄苏华等．锁相与频率合成技术．气象出版社，1996：13～19
[10] Analog Device, Inc., Analog Dialogue 36-03, 2002
[11] 清华大学微带电路编写组．微带电路．北京：人民邮电出版社．1975：100～103
[12] Analog Devices, Inc., 2.7GHz DDS-Based AgiledRF Synthesizer AD9956, Device Oatasheet, 2004: 1～15
[13] Analog Devices, Inc., Integrated Synthesizer and VCO, ADF4360-8, Device Datasheet, 2005: 1～9
[14] Analog Devices, Inc., Integrated Synthesizer and VCO, ADF4360-1, Device Datasheet, 2005: 1～8
[15] Analog Devices, Inc., PLL Frequency Synthesizer, ADF4107, Device Datasheet, 2003: 1～8
[16] Synergy Microwave Corporation, Voltage Controlled Oscillator Surface Mount Model: DCM0190410-5, Device Datasheet, 2005: 1～3
[17] 李健开．并行DDS激励PLL的微波捷变频综技术的研究：[硕士学位论文]．成都：电子科技大学，2006：23～25
[18] 冷涛．C波段小步进低相噪频率合成器的研究与设计：[硕士学位论文]．成都：电子科技大学，2006：9～10
[19] 郑百衡．L波段频率合成器的研究与应用：[硕士学位论文]．成都：电子科技大学，2006：30～32
[20] Analog Devices, Inc., A Technical Tutorial on Digital Signal Synthesis, 1999: 7～13
[21] 李志铁，赵晶，靳煜．DDS原理及其在高速跳频系统中的应用．2005，VOl．25，No.1：105～111
[22] Eva Murphy, Colm Slattery. All About Digital Synthesis. Analog Devices, Inc. A. N., 2004: 1～2
[23] Divid Brandom. DDS Design. May 13, Analog Devices, Inc. A. N., 2004: 71～84
[24] Analog Devices, Inc. CMOS 300 MSPS Quadrature Complete DDS. Device Datasheet, 2006:17
[25] 鲍景富，曾华新．微波信号源中的屏蔽和电磁兼容．电讯技术，1994，Vol．34，No.1：31～34
[26] 赵宏飞．4~8GHz宽带DDS锁相扫频源的研制：[硕士学位论文]．电子科技大学，2002：37~38
[27] 张玉兴．彭清泉．DDS的背景杂散信号分析．电子科技大学学报，Aug．1997，Vol．26，No.4：362～365
[28] 张玉兴．DDS高稳高纯频谱频率源技术．系统工程与电子技术，1997，Vol．，No．：24～28
[29] Mini-Circuits Inc., MCA1-42LH+ datasheet, 2006:1～2
[30] Vadim Manassewitsch. Frequency Synthesizers Theory and Design. Second Edition. A Wiley-Interscience Publication, 1980, 2～7.
[2] 白居宪．低噪声频率合成．西安：西安交通大学出版社，1994：16～17
[3] 高树廷，刘洪升．频率源综述．火控雷达技术，2004，Vol．33，No.1：43～46
[4] 张厥盛，郑继禹等．锁相技术．西安：西安电子科技大学出版社，1992：142～143
[5] 恽小华．现代频率合成技术综述．电子学报，1995，Vol．23，No.10：148～151
[6] Analog Devices, Fractional-N Frequency Synthesizer, ADF4154, Device Datasheet, 2004:6～7
[7] Dean Banerjee, PLL Performance, Simulation, and Design, 3rd Edition, National Semiconductor, 2005: 11～12, 120～122
[8] Donald R. Stephens. Phase-Locked Loops for Wireless Communications. Kluwer Academic Publishers, 2002: 11～19
[9] 庄卉，黄苏华等．锁相与频率合成技术．气象出版社，1996：13～19
[10] Analog Device, Inc., Analog Dialogue 36-03, 2002
[11] 清华大学微带电路编写组．微带电路．北京：人民邮电出版社．1975：100～103
[12] Analog Devices, Inc., 2.7GHz DDS-Based AgiledRF Synthesizer AD9956, Device Oatasheet, 2004: 1～15
[13] Analog Devices, Inc., Integrated Synthesizer and VCO, ADF4360-8, Device Datasheet, 2005: 1～9
[14] Analog Devices, Inc., Integrated Synthesizer and VCO, ADF4360-1, Device Datasheet, 2005: 1～8
[15] Analog Devices, Inc., PLL Frequency Synthesizer, ADF4107, Device Datasheet, 2003: 1～8
[16] Synergy Microwave Corporation, Voltage Controlled Oscillator Surface Mount Model: DCM0190410-5, Device Datasheet, 2005: 1～3
[17] 李健开．并行DDS激励PLL的微波捷变频综技术的研究：[硕士学位论文]．成都：电子科技大学，2006：23～25
[18] 冷涛．C波段小步进低相噪频率合成器的研究与设计：[硕士学位论文]．成都：电子科技大学，2006：9～10
[19] 郑百衡．L波段频率合成器的研究与应用：[硕士学位论文]．成都：电子科技大学，2006：30～32
[20] Analog Devices, Inc., A Technical Tutorial on Digital Signal Synthesis, 1999: 7～13
[21] 李志铁，赵晶，靳煜．DDS原理及其在高速跳频系统中的应用．2005，VOl．25，No.1：105～111
[22] Eva Murphy, Colm Slattery. All About Digital Synthesis. Analog Devices, Inc. A. N., 2004: 1～2
[23] Divid Brandom. DDS Design. May 13, Analog Devices, Inc. A. N., 2004: 71～84
[24] Analog Devices, Inc. CMOS 300 MSPS Quadrature Complete DDS. Device Datasheet, 2006:17
[25] 鲍景富，曾华新．微波信号源中的屏蔽和电磁兼容．电讯技术，1994，Vol．34，No.1：31～34
[26] 赵宏飞．4~8GHz宽带DDS锁相扫频源的研制：[硕士学位论文]．电子科技大学，2002：37~38
[27] 张玉兴．彭清泉．DDS的背景杂散信号分析．电子科技大学学报，Aug．1997，Vol．26，No.4：362～365
[28] 张玉兴．DDS高稳高纯频谱频率源技术．系统工程与电子技术，1997，Vol．，No．：24～28
[29] Mini-Circuits Inc., MCA1-42LH+ datasheet, 2006:1～2
[30] Vadim Manassewitsch. Frequency Synthesizers Theory and Design. Second Edition. A Wiley-Interscience Publication, 1980, 2～7.