RFIC的ESD防护电路与优化设计技术研究
摘要
由于射频集成电路（RFIC）所独有的特点，如对噪声系数敏感、要求良好的匹配和合适的增益等等，与普通的模拟/数字集成电路不同，其静电防护（ESD）设计变得更加复杂和困难。本文主要研究了在深亚微米CMOS技术条件下，RFIC的ESD保护设计及RFIC与ESD保护电路之间的协同优化问题，从ESD仿真测试平台的搭建、器件结构改进、带有ESD保护的匹配网络分析、ESD器件与RF电路协同设计（co-design）方法和消除ESD影响的电路措施改进等方面进行了分析研究。主要研究工作和成果如下：
1.论文针对几种ESD保护器件的特点进行了对比研究，选择了结构简单、寄生参数少、放电效率高且开关参数易调节的LVTSCR器件。分析了深亚微米器件在ESD大应力下的载流子传输特性，采用了载流子输运模型和碰撞电离模型，通过搭建TLP仿真测试平台，对90nm工艺条件下的LVTSCR的工作原理和特性进行了讨论，分析了几个主要参数对LVTSCR特性的影响。结果表明，本文中的LVTSCR器件的开启电压小于4V，与同等工艺条件下的ggNMOS试验结果相比较，具有相同水平的开启电压，而维持电压要小很多（1.1V对3.3V），因此具有更高的放电效率，适合深亚微米条件下的RFIC输入/输出端的ESD保护。论文的研究成果为深亚微米LVTSCR结构的ESD应力研究和TLP仿真测试的改进提供了理论依据。
2.根据LVTSCR的电学特性，分析了不同偏置条件对其开关特性的影响，提出了结构改进方法以获得良好的开关参数。由于SCR类器件具有导通电阻很小但维持电压过低的问题，在应用中容易引起功能电路的闩锁或者ESD结构开启后不能自行关闭。基于提高维持电压即提高器件内部的导通电阻这一原则，在LVTSCR结构改进中采用了几种增大电流路径的办法，最终放弃器件原有的栅极，改为纵向的双槽结构进行限流从而获得了良好的效果，占用了较小的芯片面积。在此基础上，对槽深与维持电压的关系进行了量化分析，并对一定极限下此方法遇到的瓶颈进行了讨论。结果表明，通过结构改进，LVTSCR的维持电压达到了1.5V以上，使该器件可以满足大部分深亚微米低压电路的ESD保护需求。
3.由于在现有的RFIC设计技术中，缺乏ESD器件的模型（包括大应力模型和小信号模型），而现有的等效方法，在RF分析中忽略了太多的寄生效应，因此导致在增加ESD结构后核心电路的性能严重恶化，尤其当工作频率很高（>5GHz）时，寄生参数的细微变化有可能带来端口不匹配、噪声变差或者增益降低。因此，本文建立了一种能够准确量化ESD结构参数并将其引入RF仿真的方法，该方法结合了器件级仿真、器件-电路混合模式仿真以及高频仿真的特点，对带有ESD保护的匹配网络提取S参数并建立查表模型，以引入RF设计中。其中， ESD结构的所有寄生效应在进行小信号分析时将全部被考虑进来，具有无损性，因此能过做到准确的仿真，使RFIC的性能得到最优化。通过一个5.25GHz窄带LNA-ESD设计，结合单/双向二级LVTSCR ESD保护网络，对这种co-design方法的可行性进行了验证，对比了不同ESD网络结构在加入前后及电路优化前后的性能，该结果与文献中的单向二级ggNMOS保护结构相比，在同样的器件尺寸下获得了原有二倍的HBM防护水平。
4.本文利用电源电路中的反馈补偿电路结构，通过调节反馈信号的大小和相位，使得在ESD器件位置的原始信号和反馈信号相互抵消。利用这种补偿技术，在RFIC正常工作时，被保护端口的信号对于ESD结构不可见或部分可见，起到了一种屏蔽的效果，因此使得大面积的ESD器件能够应用于更高的频率范围。通过对改进的双槽结构LVTSCR组成的50Ω传输网络进行分析，结合第五章提出的co-design方法，对加入补偿电路前后的网络传输特性进行了分析和讨论。结果表明，反馈补偿电路能够在一定的频率范围内对ESD结构做到有效隔离，使电路的匹配效果得到改进，通过调整反馈电路的参数可以使其能够具有合适的中心频率和带宽，同时不会牺牲ESD防护的水平。这种方法使得原有的ESD保护结构的适用频率获得了几个GHz的提升。
综上所述，本文以普通的模拟/数字IC ESD防护技术为基础，改进了针对LVTSCR器件的TLP仿真测试方法，对LVTSCR在大应力条件下的特性进行了分析和讨论，通过改进器件结构使其具有更合适的开关特性；提出了一种新的基于网络S参数提取的RF-ESD协同设计方法，和一种对ESD结构的反馈补偿措施，获得了一些有意义的结果，为RFIC的ESD设计提供了指导。
Due to the unique characteristics of radio frequency integrated circuit (RFIC), suchas the sensitivity to noise figure, requirement of good match and gain, different withordinary analog/digital integrated circuits, its electrostatic discharge (ESD) protectiondesign has become more complex and difficult. This dissertation studies the ESDprotection design of RFICs, and the optimization of the above two in condition of deepsub-micron CMOS technology. The content includes the construction of ESDsimulation testing platform, the improvement of device structure, the analysis of ESDprotection with matching network, co-design method of ESD devices with RF circuit,and how to eliminate the impact of ESD structure on the circuit. The major researchwork and results are as follows:
1. In this dissertation, the characteristics of several ESD protection devices arestudied and compared, and the LVTSCR device which has a simple structure, lessparasitic effects, high discharging efficiency and easy-adjust switch parameters, isselected. In simulation, the novel carrier transport model and collision ionization modelare used to analyze of the carrier transport characteristics of deep submicron devicesunder ESD stress. With the TLP simulation test platform, the working principle andcharacteristics of the LVTSCR under90nm process are discussed, and the impact ofseveral parameters on the LVTSCR’s snapback characteristic is analyzed. The resultsshow that the turn-on voltage of LVTSCR is less than4V in this dissertation, which issimilar with the ggNMOS results under the same process, while its hold-on voltage ismuch lower than the latter (1.1V to3.3V). Therefore, the LVTSCR has higherdischarging efficiency, which is suitable for input protection of RFICs. The method alsoprovides a good reference and basis for TLP testing and standardization.
2．Based on the electrical characteristics of LVTSCR, the impact of the differentbias mode on the switching characteristics is analyzed, and the structural improvementsare presented. For the small turn-on resistance and low hold-on voltage, the SCRdevices in applications are tend to cause latch-up of circuit, or ESD structure unableturning itself off when ESD event is over. Increasing hold-on voltage means increasingthe turn-on resistance, thus several measures are used to increase the current path instructural improvements of LVTSCR, and a double-vertical-trench structure is proposed to limit the current, which obtains good results and occupies a small chip area. Then therelationship of trench depth with hold-on voltage is analyzed, and the bottleneck of thismethod encountered is discussed. The results show that the device is improved tomaintain a hold-on voltage above1.5V, which allows the device to meet the ESDprotection requirements of most of the deep sub-micron low-voltage applications.
3. For the lack of ESD device models (including high stress model and small-signalmodel) in existing RFIC techniques, the equivalent method in RF-ESD analysis ignoresa lot of parasitic effects, which results in performance degradation of the core circuitand optimization difficulty when ESD protection is added, especially in high frequency(>5GHz) applications. The subtle change of the parasitic effects may cause themismatch of terminals, degradation of noise figure or gain. Therefore, a method toquantify the ESD structure accurately and introduce it to RF design is presented, whichincorporates the device-level simulation with the device-circuit mixed-mode simulationand high-frequency simulation. In this method, the approach of extracting S-parametersof ESD matching network and establishing table-lookup model to introduce in RFdesign is first used, and all the small-signal parasitic effects of ESD structure are takeninto account, thus accurate simulations can be done and the RFIC performance isoptimized. A5.25GHz narrow-band LNA-ESD design, combined with two-stageone-directional/dual-directional ESD protection based on LVTSCR, is used todemonstrate the feasibility of this co-design method. The RF performance of LNAbefore and after optimization with different ESD protection is discussed. Comparedwith two-stage one-directional ESD protection based on ggNMOS in the literature, theHBM protection level in this work is doubled with the device in same size.
4. Using the feedback compensation circuit used in power supply, the originalsignal and the feedback signal in location of the ESD device will be cancelled eachother by adjusting the magnitude and phase of the feedback signal. With thecompensation technique, in normal working conditions of RFIC, the signal of theprotected port is invisible or partially visible to ESD structure, which plays a shieldingeffect, and therefore making large-size ESD device can be used in high frequency range.With improved dual-trench LVTSCR and the proposed co-design method, theperformance of50Ω transmission line with and without the compensation circuit isdiscussed. The results show that the feedback compensation circuit can effectivelyseparate the ESD structure with transmission line in a certain frequency range, thusimproves the matching of the circuit. It can get an appropriate center frequency andbandwidth by adjusting the parameters of the feedback circuit, which does not sacrifice the ESD protection level. With this approach, the application frequency of an ESDprotection is upgraded for several GHz.
In summary, based on ordinary analog/digital IC ESD protection technology, theTLP simulation test method for LVTSCR device is improved, and the LVTSCR’scharacteristics in condition of great stress are analyzed, and device structure is improvedto get good switching parameters. A new RF-ESD co-design method based onS-parameters extracting and a feedback compensation measure are proposed, and somemeaningful results are obtained, which provides guidance for the RFIC ESD design.
1.论文针对几种ESD保护器件的特点进行了对比研究，选择了结构简单、寄生参数少、放电效率高且开关参数易调节的LVTSCR器件。分析了深亚微米器件在ESD大应力下的载流子传输特性，采用了载流子输运模型和碰撞电离模型，通过搭建TLP仿真测试平台，对90nm工艺条件下的LVTSCR的工作原理和特性进行了讨论，分析了几个主要参数对LVTSCR特性的影响。结果表明，本文中的LVTSCR器件的开启电压小于4V，与同等工艺条件下的ggNMOS试验结果相比较，具有相同水平的开启电压，而维持电压要小很多（1.1V对3.3V），因此具有更高的放电效率，适合深亚微米条件下的RFIC输入/输出端的ESD保护。论文的研究成果为深亚微米LVTSCR结构的ESD应力研究和TLP仿真测试的改进提供了理论依据。
2.根据LVTSCR的电学特性，分析了不同偏置条件对其开关特性的影响，提出了结构改进方法以获得良好的开关参数。由于SCR类器件具有导通电阻很小但维持电压过低的问题，在应用中容易引起功能电路的闩锁或者ESD结构开启后不能自行关闭。基于提高维持电压即提高器件内部的导通电阻这一原则，在LVTSCR结构改进中采用了几种增大电流路径的办法，最终放弃器件原有的栅极，改为纵向的双槽结构进行限流从而获得了良好的效果，占用了较小的芯片面积。在此基础上，对槽深与维持电压的关系进行了量化分析，并对一定极限下此方法遇到的瓶颈进行了讨论。结果表明，通过结构改进，LVTSCR的维持电压达到了1.5V以上，使该器件可以满足大部分深亚微米低压电路的ESD保护需求。
3.由于在现有的RFIC设计技术中，缺乏ESD器件的模型（包括大应力模型和小信号模型），而现有的等效方法，在RF分析中忽略了太多的寄生效应，因此导致在增加ESD结构后核心电路的性能严重恶化，尤其当工作频率很高（>5GHz）时，寄生参数的细微变化有可能带来端口不匹配、噪声变差或者增益降低。因此，本文建立了一种能够准确量化ESD结构参数并将其引入RF仿真的方法，该方法结合了器件级仿真、器件-电路混合模式仿真以及高频仿真的特点，对带有ESD保护的匹配网络提取S参数并建立查表模型，以引入RF设计中。其中， ESD结构的所有寄生效应在进行小信号分析时将全部被考虑进来，具有无损性，因此能过做到准确的仿真，使RFIC的性能得到最优化。通过一个5.25GHz窄带LNA-ESD设计，结合单/双向二级LVTSCR ESD保护网络，对这种co-design方法的可行性进行了验证，对比了不同ESD网络结构在加入前后及电路优化前后的性能，该结果与文献中的单向二级ggNMOS保护结构相比，在同样的器件尺寸下获得了原有二倍的HBM防护水平。
4.本文利用电源电路中的反馈补偿电路结构，通过调节反馈信号的大小和相位，使得在ESD器件位置的原始信号和反馈信号相互抵消。利用这种补偿技术，在RFIC正常工作时，被保护端口的信号对于ESD结构不可见或部分可见，起到了一种屏蔽的效果，因此使得大面积的ESD器件能够应用于更高的频率范围。通过对改进的双槽结构LVTSCR组成的50Ω传输网络进行分析，结合第五章提出的co-design方法，对加入补偿电路前后的网络传输特性进行了分析和讨论。结果表明，反馈补偿电路能够在一定的频率范围内对ESD结构做到有效隔离，使电路的匹配效果得到改进，通过调整反馈电路的参数可以使其能够具有合适的中心频率和带宽，同时不会牺牲ESD防护的水平。这种方法使得原有的ESD保护结构的适用频率获得了几个GHz的提升。
综上所述，本文以普通的模拟/数字IC ESD防护技术为基础，改进了针对LVTSCR器件的TLP仿真测试方法，对LVTSCR在大应力条件下的特性进行了分析和讨论，通过改进器件结构使其具有更合适的开关特性；提出了一种新的基于网络S参数提取的RF-ESD协同设计方法，和一种对ESD结构的反馈补偿措施，获得了一些有意义的结果，为RFIC的ESD设计提供了指导。
Due to the unique characteristics of radio frequency integrated circuit (RFIC), suchas the sensitivity to noise figure, requirement of good match and gain, different withordinary analog/digital integrated circuits, its electrostatic discharge (ESD) protectiondesign has become more complex and difficult. This dissertation studies the ESDprotection design of RFICs, and the optimization of the above two in condition of deepsub-micron CMOS technology. The content includes the construction of ESDsimulation testing platform, the improvement of device structure, the analysis of ESDprotection with matching network, co-design method of ESD devices with RF circuit,and how to eliminate the impact of ESD structure on the circuit. The major researchwork and results are as follows:
1. In this dissertation, the characteristics of several ESD protection devices arestudied and compared, and the LVTSCR device which has a simple structure, lessparasitic effects, high discharging efficiency and easy-adjust switch parameters, isselected. In simulation, the novel carrier transport model and collision ionization modelare used to analyze of the carrier transport characteristics of deep submicron devicesunder ESD stress. With the TLP simulation test platform, the working principle andcharacteristics of the LVTSCR under90nm process are discussed, and the impact ofseveral parameters on the LVTSCR’s snapback characteristic is analyzed. The resultsshow that the turn-on voltage of LVTSCR is less than4V in this dissertation, which issimilar with the ggNMOS results under the same process, while its hold-on voltage ismuch lower than the latter (1.1V to3.3V). Therefore, the LVTSCR has higherdischarging efficiency, which is suitable for input protection of RFICs. The method alsoprovides a good reference and basis for TLP testing and standardization.
2．Based on the electrical characteristics of LVTSCR, the impact of the differentbias mode on the switching characteristics is analyzed, and the structural improvementsare presented. For the small turn-on resistance and low hold-on voltage, the SCRdevices in applications are tend to cause latch-up of circuit, or ESD structure unableturning itself off when ESD event is over. Increasing hold-on voltage means increasingthe turn-on resistance, thus several measures are used to increase the current path instructural improvements of LVTSCR, and a double-vertical-trench structure is proposed to limit the current, which obtains good results and occupies a small chip area. Then therelationship of trench depth with hold-on voltage is analyzed, and the bottleneck of thismethod encountered is discussed. The results show that the device is improved tomaintain a hold-on voltage above1.5V, which allows the device to meet the ESDprotection requirements of most of the deep sub-micron low-voltage applications.
3. For the lack of ESD device models (including high stress model and small-signalmodel) in existing RFIC techniques, the equivalent method in RF-ESD analysis ignoresa lot of parasitic effects, which results in performance degradation of the core circuitand optimization difficulty when ESD protection is added, especially in high frequency(>5GHz) applications. The subtle change of the parasitic effects may cause themismatch of terminals, degradation of noise figure or gain. Therefore, a method toquantify the ESD structure accurately and introduce it to RF design is presented, whichincorporates the device-level simulation with the device-circuit mixed-mode simulationand high-frequency simulation. In this method, the approach of extracting S-parametersof ESD matching network and establishing table-lookup model to introduce in RFdesign is first used, and all the small-signal parasitic effects of ESD structure are takeninto account, thus accurate simulations can be done and the RFIC performance isoptimized. A5.25GHz narrow-band LNA-ESD design, combined with two-stageone-directional/dual-directional ESD protection based on LVTSCR, is used todemonstrate the feasibility of this co-design method. The RF performance of LNAbefore and after optimization with different ESD protection is discussed. Comparedwith two-stage one-directional ESD protection based on ggNMOS in the literature, theHBM protection level in this work is doubled with the device in same size.
4. Using the feedback compensation circuit used in power supply, the originalsignal and the feedback signal in location of the ESD device will be cancelled eachother by adjusting the magnitude and phase of the feedback signal. With thecompensation technique, in normal working conditions of RFIC, the signal of theprotected port is invisible or partially visible to ESD structure, which plays a shieldingeffect, and therefore making large-size ESD device can be used in high frequency range.With improved dual-trench LVTSCR and the proposed co-design method, theperformance of50Ω transmission line with and without the compensation circuit isdiscussed. The results show that the feedback compensation circuit can effectivelyseparate the ESD structure with transmission line in a certain frequency range, thusimproves the matching of the circuit. It can get an appropriate center frequency andbandwidth by adjusting the parameters of the feedback circuit, which does not sacrifice the ESD protection level. With this approach, the application frequency of an ESDprotection is upgraded for several GHz.
In summary, based on ordinary analog/digital IC ESD protection technology, theTLP simulation test method for LVTSCR device is improved, and the LVTSCR’scharacteristics in condition of great stress are analyzed, and device structure is improvedto get good switching parameters. A new RF-ESD co-design method based onS-parameters extracting and a feedback compensation measure are proposed, and somemeaningful results are obtained, which provides guidance for the RFIC ESD design.
引文
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