用于高速光互连的光接收机前端放大电路设计
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摘要
随着集成电路频率的提高,传统的电互连技术因为严重的损耗、串扰和阻抗匹配等问题,在印刷电路板(PCB)上传输10Gbps以上的信号非常困难,成为系统性能提高的瓶颈。而光互连技术因为高带宽、低损耗、无串扰、无阻抗匹配和电磁兼容问题等优势,是电互连技术理想的替代者。
在用于光互连系统的几个功能电路中,构成光接收机前端放大电路的前置放大器和主放大器是两个关键电路。
作为光接收机的关键部分,前置放大器的性能在很大程度上决定了整个光接收机的性能。在高速光纤传输系统中,广泛采用跨阻型前置放大器。本文采用了RGC结构作为跨阻放大器的输入端,克服了包括光探测器结电容在内的大寄生电容造成的带宽不够的问题。
主放大器有两种实现方式:自动增益控制放大器和限幅放大器。由于限幅放大器具有设计简单、功耗低、芯片面积小和外接元件少的优点,本文选择限幅放大器的形式来实现光接收机的主放大器。限幅放大器采用共源级差分结构作为放大单元。放大单元之间采用直接耦合技术降低功耗。
本文采用0.18μm CMOS工艺单片集成了2.5Gbps的光接收机前端放大电路。根据理论分析优化设计,并通过实际模拟,电路取得了较优的增益、带宽和功耗性能。
文章详细的介绍了电路的设计、然后描述了对应电路的版图设计。在Cadence Virtuoso平台下的前仿真结果表明,本设计实现了所要求的速率和功耗。
With the increasing of Integrated Circuits’Frequency, many problems appear, such as attenuation, cross-talk and impedance matching. It is very difficult to transmit electrical signals on PCB whose bit rate reached 10Gbps or above,which has become the bottleneck of the system performance. Compared to the electrical interconnection, optical interconnection is a good candidate due to its advantages of high bandwidth、low attenuation, no cross-talk, no impedance matching and low Electromagnetic Interference(EMI).
In the building blocks of an optical interconnect system, the pre-amplifier and the main amplifier are the critical parts.
The performance of a preamplifier has great effect on the performance of an optical receiver. Transimpedance pre-amplifiers are widely used in the high speed optical transmission systems. The preamplifier exploits the Regulated Cascode(RGC) configuration as the input stage, which isolates the large input parasitic capacitance including photodiode capacitance from the bandwidth determination.
An Automatic Gain Control (AGC) amplifier or a limiting amplifier is generally used to realize the main amplifier. The latter was chosen to realize the main amplifier in our design since it has the features of simple topology, few areas and low power consumption. A differential common source amplifier is used as the basic amplifier. The direct-coupled technology is employed between different amplifier to reduce the power dissipation.
The monolithic integrated front-end amplifier whose processing speed achieved 2.5Gbps was designed in SMIC 0.18μm CMOS technology. On the basis of theory analysis and design optimization, the circuit achieves high performance of gain, bandwidth and power dissipation.
This paper firstly describe the circuit design and then introduce the layout of these circuits. The simulation results from Cadence Virtuoso suggest that the design achieves the needed speed and power consumption.
在用于光互连系统的几个功能电路中,构成光接收机前端放大电路的前置放大器和主放大器是两个关键电路。
作为光接收机的关键部分,前置放大器的性能在很大程度上决定了整个光接收机的性能。在高速光纤传输系统中,广泛采用跨阻型前置放大器。本文采用了RGC结构作为跨阻放大器的输入端,克服了包括光探测器结电容在内的大寄生电容造成的带宽不够的问题。
主放大器有两种实现方式:自动增益控制放大器和限幅放大器。由于限幅放大器具有设计简单、功耗低、芯片面积小和外接元件少的优点,本文选择限幅放大器的形式来实现光接收机的主放大器。限幅放大器采用共源级差分结构作为放大单元。放大单元之间采用直接耦合技术降低功耗。
本文采用0.18μm CMOS工艺单片集成了2.5Gbps的光接收机前端放大电路。根据理论分析优化设计,并通过实际模拟,电路取得了较优的增益、带宽和功耗性能。
文章详细的介绍了电路的设计、然后描述了对应电路的版图设计。在Cadence Virtuoso平台下的前仿真结果表明,本设计实现了所要求的速率和功耗。
With the increasing of Integrated Circuits’Frequency, many problems appear, such as attenuation, cross-talk and impedance matching. It is very difficult to transmit electrical signals on PCB whose bit rate reached 10Gbps or above,which has become the bottleneck of the system performance. Compared to the electrical interconnection, optical interconnection is a good candidate due to its advantages of high bandwidth、low attenuation, no cross-talk, no impedance matching and low Electromagnetic Interference(EMI).
In the building blocks of an optical interconnect system, the pre-amplifier and the main amplifier are the critical parts.
The performance of a preamplifier has great effect on the performance of an optical receiver. Transimpedance pre-amplifiers are widely used in the high speed optical transmission systems. The preamplifier exploits the Regulated Cascode(RGC) configuration as the input stage, which isolates the large input parasitic capacitance including photodiode capacitance from the bandwidth determination.
An Automatic Gain Control (AGC) amplifier or a limiting amplifier is generally used to realize the main amplifier. The latter was chosen to realize the main amplifier in our design since it has the features of simple topology, few areas and low power consumption. A differential common source amplifier is used as the basic amplifier. The direct-coupled technology is employed between different amplifier to reduce the power dissipation.
The monolithic integrated front-end amplifier whose processing speed achieved 2.5Gbps was designed in SMIC 0.18μm CMOS technology. On the basis of theory analysis and design optimization, the circuit achieves high performance of gain, bandwidth and power dissipation.
This paper firstly describe the circuit design and then introduce the layout of these circuits. The simulation results from Cadence Virtuoso suggest that the design achieves the needed speed and power consumption.
引文
[1] G. Dermer and C. Svensson .“Time Domain Modeling of Lossy Interconnects”. 2nd IMAPS Advanced Technology Workshop . Future Digital Interconnects over 1,000 MHz . Austin, Tx, USA, Jan. 17-18, 2000
[2] Chinese Academy of Sciences and Georgia Institute of Technology .“Edge-View Photodetector for Optical Interconnects”. Nature Photonics . Vol.1,November 2007
[3]李连鸣,冯军等,2.5Gbps 0.35μm CMOS激光驱动器.东南大学学报(自然科学版). 2004 ,04
[4]顾畹仪主编,黄永清,陈雪等.光纤通信.人民邮电出版. 2006.5
[5] S.M.Rezaul Hasan. Design of a Low-Power 3.5-GHz Broad-Band CMOS Transimpedance Amplifier for Optical Transceivers. IEEE Transactions on Circuits and Systems. 2005, 52(6) .1062-1063
[6] S.M.Rezaul Hasan. A high Performance Wide-band CMOS Transimpedance Amplifier for Optical Transceivers. System-on-Chip for Real-Time Applications. 2003. Proceedings. The 3rd IEEE International Workshop on . 2003:82-85
[7] C.Toumazou, S.M.Park. Wideband low noise CMOS transimpedance amplifier for gigahertz operation. Electronics Letters. 1996 . 32(13):1194-1196
[8] Behzad Razavi.光通信集成电路设计.清华大学出版社. 2005.5:p73. 64
[9] Sung Min Park. Gigabit CMOS Transimpedance Amplifiers for Optical Communication Applications. Proceedings of the 7th Korea-Russia International Symposium. Korus. 2003:213-214
[10] Sung Min Park, Hoi-Jun Yoo. 2.5Gbit/s CMOS transimpedance amplifier for optical communication applications. Electronics Letters. 2003. 39(2):211-212
[11] Sung Min Park, Hoi-Jun Yoo. 1.25-Gbit/s Regulated Cascode CMOS Transimpedance Amplifier for Gigabit Ethernet Applications. IEEE Journal of Solid-State Circuits. 2004, 39(1):112-115
[12] Wei-Zen Chen, Chao-Hsin Lu. Design and Anaylsis of A 2.5-Gbps Optical Receiver Analog Front-End in a 0.35-μm Digital CMOS Technology. IEEE Transactions on Circuits and Systems. 2006, 53(4):982-983
[13] Wei Tang, David V.Plant. 3.125Gbit/s Low Power Truly-Differential Parallel Optical Receiver Module in 0.13μm CMOS. Circuits and Systems. 2005. 48th Midwest Symposium on.2005. 1:400-404
[14] Chin-Wei Kuo, Chao-Chih Hsiao, Shih-Cheng Yang. 2Gbit/s transimpedance amplifier fabricated by 0.35μm CMOS technologies. Electronics Letters. 2001, 37(19):1158-1160
[15] Wei-Zen Chen, Da-Shin Lin. A 90dB?, 10Gbps Optical Receiver in a 0.18μm CMOS Technology. Asian Solid-State Circuits Conference. Hsinchu .2005. 2005:177-180
[16] Su-Jeong Sim, Jeongmin Park, Sung Min Park . A 1.8V, 60dB?, 11GHz Transimpedance Amplifier with Strong immunity to Input Parasitic Capacitance.ISCAS 2006., Ewha Womans University,2006
[17]王志功著.光纤通信集成电路设计.高等教育出版社. 2003.6
[18] Thomas Lee. The Design of CMOS Radio-Frequency Integrated Circuits.电子工业出版社.2002.6
[19]王延尧等编.光通信设备基础.天津科学技术出版社. 1992.12
[20] Eduard S?ckinger, Wilhelm C.Fischer. A 3GHz, 32dB CMOS Limiting Amplifier for SONET OC-48 Receivers. 2000 IEEE International Solid-State Circuits Conference, 2000:
[21]李泰成,陈平随. SoC设计探索:光纤通讯系统中的高速类比信号处理器设计.新科电子杂志.2004.05
[22] Maxim. Introduction of LVDS, CML, PECL. application notes
[23] Wang Hongxin, Yang Ruixia. An Novel Method of S-Parameter Extraction for Chip. Chinese Journal of Electron Devices.2004:27(1)
[24] J.A. Montiel-Nelson, V.deArmas, R. Sarmiento. A compact layout technique for reducing swithing current effects in high speed circuits. Proceedings of the IEEE 2001 2nd International Symposium on Quality Electronic Design. San Jose, CA, USA,2001.2001:223-228
[25] S. Zhang, W. Dai, TEG: A new post-layout optimization method. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2003,22:446-456
[26]谢家奎玄月清冯军编.电子线路线性部分(第四版).高等教育出版社.
[27] Ethan A.Grain, Michael H.Perrott . A 3.125Gb/s Limiting Amplifier in CMOS With 42dB Gain and 1μs Offset Compensation. IEEE Journal Of Solid-Circuits, VOL 41 NO.2, February 2006.
[28] Sherif Galal , Behzad Razavi . 10-Gb/s Limiting Amplifier and Laser/Modulator Driver in0.18-μm CMOS Technology. IEEE Journal Of Solid-Circuits ,VOL 38 NO.12, December 2003.
[29] Huei-Yan Huang, Jun-Chau Chien , Liang-hung Lu . A 10Gb/s Inductorless CMOS Limiting Amplifier With Third-order Interleaving Active Feedback . IEEE Journal Of Solid-Circuits ,VOL 42 NO.5, May, 2007.
[30] Wei-Zen Chen , Ying-Lien Cheng , Da-Shin Lin . A 1.8V 10-Gb/s Fully Integrated CMOS Optical Receiver Analog Front-end . IEEE Journal Of Solid-Circuits .VOL 40 NO.6, June 2006.
[2] Chinese Academy of Sciences and Georgia Institute of Technology .“Edge-View Photodetector for Optical Interconnects”. Nature Photonics . Vol.1,November 2007
[3]李连鸣,冯军等,2.5Gbps 0.35μm CMOS激光驱动器.东南大学学报(自然科学版). 2004 ,04
[4]顾畹仪主编,黄永清,陈雪等.光纤通信.人民邮电出版. 2006.5
[5] S.M.Rezaul Hasan. Design of a Low-Power 3.5-GHz Broad-Band CMOS Transimpedance Amplifier for Optical Transceivers. IEEE Transactions on Circuits and Systems. 2005, 52(6) .1062-1063
[6] S.M.Rezaul Hasan. A high Performance Wide-band CMOS Transimpedance Amplifier for Optical Transceivers. System-on-Chip for Real-Time Applications. 2003. Proceedings. The 3rd IEEE International Workshop on . 2003:82-85
[7] C.Toumazou, S.M.Park. Wideband low noise CMOS transimpedance amplifier for gigahertz operation. Electronics Letters. 1996 . 32(13):1194-1196
[8] Behzad Razavi.光通信集成电路设计.清华大学出版社. 2005.5:p73. 64
[9] Sung Min Park. Gigabit CMOS Transimpedance Amplifiers for Optical Communication Applications. Proceedings of the 7th Korea-Russia International Symposium. Korus. 2003:213-214
[10] Sung Min Park, Hoi-Jun Yoo. 2.5Gbit/s CMOS transimpedance amplifier for optical communication applications. Electronics Letters. 2003. 39(2):211-212
[11] Sung Min Park, Hoi-Jun Yoo. 1.25-Gbit/s Regulated Cascode CMOS Transimpedance Amplifier for Gigabit Ethernet Applications. IEEE Journal of Solid-State Circuits. 2004, 39(1):112-115
[12] Wei-Zen Chen, Chao-Hsin Lu. Design and Anaylsis of A 2.5-Gbps Optical Receiver Analog Front-End in a 0.35-μm Digital CMOS Technology. IEEE Transactions on Circuits and Systems. 2006, 53(4):982-983
[13] Wei Tang, David V.Plant. 3.125Gbit/s Low Power Truly-Differential Parallel Optical Receiver Module in 0.13μm CMOS. Circuits and Systems. 2005. 48th Midwest Symposium on.2005. 1:400-404
[14] Chin-Wei Kuo, Chao-Chih Hsiao, Shih-Cheng Yang. 2Gbit/s transimpedance amplifier fabricated by 0.35μm CMOS technologies. Electronics Letters. 2001, 37(19):1158-1160
[15] Wei-Zen Chen, Da-Shin Lin. A 90dB?, 10Gbps Optical Receiver in a 0.18μm CMOS Technology. Asian Solid-State Circuits Conference. Hsinchu .2005. 2005:177-180
[16] Su-Jeong Sim, Jeongmin Park, Sung Min Park . A 1.8V, 60dB?, 11GHz Transimpedance Amplifier with Strong immunity to Input Parasitic Capacitance.ISCAS 2006., Ewha Womans University,2006
[17]王志功著.光纤通信集成电路设计.高等教育出版社. 2003.6
[18] Thomas Lee. The Design of CMOS Radio-Frequency Integrated Circuits.电子工业出版社.2002.6
[19]王延尧等编.光通信设备基础.天津科学技术出版社. 1992.12
[20] Eduard S?ckinger, Wilhelm C.Fischer. A 3GHz, 32dB CMOS Limiting Amplifier for SONET OC-48 Receivers. 2000 IEEE International Solid-State Circuits Conference, 2000:
[21]李泰成,陈平随. SoC设计探索:光纤通讯系统中的高速类比信号处理器设计.新科电子杂志.2004.05
[22] Maxim. Introduction of LVDS, CML, PECL. application notes
[23] Wang Hongxin, Yang Ruixia. An Novel Method of S-Parameter Extraction for Chip. Chinese Journal of Electron Devices.2004:27(1)
[24] J.A. Montiel-Nelson, V.deArmas, R. Sarmiento. A compact layout technique for reducing swithing current effects in high speed circuits. Proceedings of the IEEE 2001 2nd International Symposium on Quality Electronic Design. San Jose, CA, USA,2001.2001:223-228
[25] S. Zhang, W. Dai, TEG: A new post-layout optimization method. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2003,22:446-456
[26]谢家奎玄月清冯军编.电子线路线性部分(第四版).高等教育出版社.
[27] Ethan A.Grain, Michael H.Perrott . A 3.125Gb/s Limiting Amplifier in CMOS With 42dB Gain and 1μs Offset Compensation. IEEE Journal Of Solid-Circuits, VOL 41 NO.2, February 2006.
[28] Sherif Galal , Behzad Razavi . 10-Gb/s Limiting Amplifier and Laser/Modulator Driver in0.18-μm CMOS Technology. IEEE Journal Of Solid-Circuits ,VOL 38 NO.12, December 2003.
[29] Huei-Yan Huang, Jun-Chau Chien , Liang-hung Lu . A 10Gb/s Inductorless CMOS Limiting Amplifier With Third-order Interleaving Active Feedback . IEEE Journal Of Solid-Circuits ,VOL 42 NO.5, May, 2007.
[30] Wei-Zen Chen , Ying-Lien Cheng , Da-Shin Lin . A 1.8V 10-Gb/s Fully Integrated CMOS Optical Receiver Analog Front-end . IEEE Journal Of Solid-Circuits .VOL 40 NO.6, June 2006.