集成于GPS射频芯片的LDO设计
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摘要
随着电子技术的发展,集成稳压器成为各种电子设备中不可或缺的组成部分,线性稳压器由于具有极低的自有噪声和较高的电源抑制比,结构简单等优点得到广泛使用,为适应宽电压工作环境的需要,现在越来越多的芯片已经集成了低压差线性稳压器。
本文针对一款GPS射频芯片,设计了集成于射频芯片内部的LDO。由于射频芯片中各个模块对电源噪声很敏感,所以需要降低LDO的输出噪声并提高LDO的电源抑制比,而LDO的噪声和电源抑制比很大程度上由基准电压源决定,通过在基准电压源的输出串联一路RC低通滤波器,可以有效降低LDO的输出噪声,并提高LDO的电源抑制比。RC滤波器的大电容可以外接,这样可以节省芯片面积,加大电容值可以显著的降低基准电压源的输出噪声。为了降低射频芯片的功耗,设计有开关电路,在电路闲置期间将芯片的电源关闭。由于要集成于射频芯片内部,所以对芯片面积有严格的要求。本设计输入电压范围2.6V-3.6V,输出电压1.8V,电路包括带隙基准电压源、误差放大器、缓冲器、调整管、反馈网络、过温保护电路以及限流保护电路。射频芯片正常工作电流为15mA,故设计最大输出电流50mA;负载电流在0mA到50mA间变化时,LDO输出电压变化峰值小于5mV;PSRR在1kHz处达到73.7dB,在1GHz的带宽内PSRR最小为36.6dB;在100kHz处LDO的输出噪声密度为33.5 nV /Hz ,在1MHz处输出噪声密度达到8.72 nV /Hz。本设计的版图面积约为280μm×150μm,使用TSMC 0.18μm射频和混合信号CMOS工艺实现,并成功流片。
With the development of electronic technology, integrated voltage regulator is an indispensable part of a variety of electronic equipment. Linear regulator has been widely used, as it has very low noise, high power supply rejection ratio and simple structure. More and more chips are integrated with low dropout linear regulators, for it can provide a stable power supply voltage.
This thesis presents the design and implementation of an on-chip low dropout linear regulator, which is integrated into a GPS radio-frequency chip. Modules in RF chips are very sensitive to the noise of power supply voltage, so it's necessary to reduce the LDO output noise, and increase the PSRR. The noise and PSRR of LDO is dominated by the bandgap reference.To reduce the intrinsic noise and increase the PSRR of the LDO, the bandgap reference with an RC low pass filter can be adopted,and an outside capacitor is available for the RC low pass filter, which can largely reduce the output noise and increase PSRR of the LDO. In order to reduce the power consumption, a switch is adopted to shutdown the LDO when the GPS radio-frequency chip is free. This LDO is designed to have a maximum output current of 50mA,as the GPS radio-frequency chip has a 15mA current consumption,and its layout area should be the smaller the better .The simulation results shows that the maximum output variation is smaller than 5mV at a full current change from 0mA to 50mA,the PSRR of this LDO is 73.7dB at the frequency of 1kHz,and more than 36.6dB in all frequency bands, the output noise is 33.5 nV /Hz @100kHz and 8.72 nV /Hz @1MHz, and the layout area is 280μm×150μm.This LDO is fabricated in TSMC 0.18μm mixed-signal process.
本文针对一款GPS射频芯片,设计了集成于射频芯片内部的LDO。由于射频芯片中各个模块对电源噪声很敏感,所以需要降低LDO的输出噪声并提高LDO的电源抑制比,而LDO的噪声和电源抑制比很大程度上由基准电压源决定,通过在基准电压源的输出串联一路RC低通滤波器,可以有效降低LDO的输出噪声,并提高LDO的电源抑制比。RC滤波器的大电容可以外接,这样可以节省芯片面积,加大电容值可以显著的降低基准电压源的输出噪声。为了降低射频芯片的功耗,设计有开关电路,在电路闲置期间将芯片的电源关闭。由于要集成于射频芯片内部,所以对芯片面积有严格的要求。本设计输入电压范围2.6V-3.6V,输出电压1.8V,电路包括带隙基准电压源、误差放大器、缓冲器、调整管、反馈网络、过温保护电路以及限流保护电路。射频芯片正常工作电流为15mA,故设计最大输出电流50mA;负载电流在0mA到50mA间变化时,LDO输出电压变化峰值小于5mV;PSRR在1kHz处达到73.7dB,在1GHz的带宽内PSRR最小为36.6dB;在100kHz处LDO的输出噪声密度为33.5 nV /Hz ,在1MHz处输出噪声密度达到8.72 nV /Hz。本设计的版图面积约为280μm×150μm,使用TSMC 0.18μm射频和混合信号CMOS工艺实现,并成功流片。
With the development of electronic technology, integrated voltage regulator is an indispensable part of a variety of electronic equipment. Linear regulator has been widely used, as it has very low noise, high power supply rejection ratio and simple structure. More and more chips are integrated with low dropout linear regulators, for it can provide a stable power supply voltage.
This thesis presents the design and implementation of an on-chip low dropout linear regulator, which is integrated into a GPS radio-frequency chip. Modules in RF chips are very sensitive to the noise of power supply voltage, so it's necessary to reduce the LDO output noise, and increase the PSRR. The noise and PSRR of LDO is dominated by the bandgap reference.To reduce the intrinsic noise and increase the PSRR of the LDO, the bandgap reference with an RC low pass filter can be adopted,and an outside capacitor is available for the RC low pass filter, which can largely reduce the output noise and increase PSRR of the LDO. In order to reduce the power consumption, a switch is adopted to shutdown the LDO when the GPS radio-frequency chip is free. This LDO is designed to have a maximum output current of 50mA,as the GPS radio-frequency chip has a 15mA current consumption,and its layout area should be the smaller the better .The simulation results shows that the maximum output variation is smaller than 5mV at a full current change from 0mA to 50mA,the PSRR of this LDO is 73.7dB at the frequency of 1kHz,and more than 36.6dB in all frequency bands, the output noise is 33.5 nV /Hz @100kHz and 8.72 nV /Hz @1MHz, and the layout area is 280μm×150μm.This LDO is fabricated in TSMC 0.18μm mixed-signal process.
引文
[1]中国电源管理芯片市场现状与趋势。赛迪顾问2008.7。
[2]精工电子有限公司S-817系列LDO数据手册。11-13页
[3]毕查德.拉扎维。模拟CMOS集成电路设计。西安:西安交通大学出版社,2003。284-327页。
[4] Phillip E.Al1en,Douglas R.Holberg(冯军,李智群译)。CMOS模拟集成电路设计(第二版).北京:电子工业出版社,2003。92-137页
[5]刘韬,徐志伟,程君侠。一种高电源抑制比CMOS能隙基准电压源.微电子学, Vo1.29,1999。
[6]王红义,土松林,来新泉,孙作治。CMOS电压基准的设计原理.微电子学,2003.10, 33(5):34-37。
[7]杨伟,李儒章。基于Cadence界面的工艺设计包设计方法.微电子学2005.10。504-508页。
[8]徐静萍,来新泉。基于CMOS工艺的低噪声高稳定性LDO的设计.半导体技术,第32卷第12期。
[9]陈碧,罗岚,周帅林。一种低温漂CMOS带隙基准电压源的设计.电子器件, 2004.3, 27(1):79一82。
[10]杨锦文,冯全源。基于嵌入式密勒补偿技术的LDO放大器设计.微电子学与计算机,2006年,第23卷第3期。
[11]郭鹏,沈相国。.LDO的三种频率补偿方案实现.电子器件,第29卷第3期, 2006年9月。
[12] Yueming Jiang, Lee E.K.F. A low voltage low 1/f noise CMOS bandgap reference. Circuits and Systems, ISCAS 2005. IEEE International Symposium on 23-26 May 2005 Page(s):3877 - 3880 Vol. 4.
[13]Yueming Jiang, Lee E.K.F. A 1.2 V bandgap reference based on transimpedance amplifier. Circuits and Systems ISCAS 2000 Geneva.The 2000 IEEE International Symposium on Volume 4, 28-31 May 2000 Page(s):261 - 264 vol.4.
[14] Gunawan M, Meijer G.C.M, Fonderie J, Huijsing J.H. A curvature-corrected low-voltage bandgap reference. Solid-State Circuits, IEEE Journal of Volume 28, Issue 6, June 1993 Page(s):667– 670.
[15] Xinpeng Xing, Zhihua Wang, Dongmei Li. A low voltage high precision CMOS bandgap reference. Norchip, 2007 19-20 Nov. 2007 Page(s):1– 4.
[16] Haibo Wang, Lanlan Liu, Xin Liu,Guotong Du, Yuchun Chang. An Improved Compensated-Temperature and High PSRR Bandgap Reference Circuit Design. Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on2006 Page(s):1742– 1744.
[17] Tom Kugelstadt. Fundamental Theory of PMOS Low-Dropout Voltage Regulators, TI Company, Inc.,1999.
[18] Dongpo Chen,Lenian He and Xiaolang Yan. A Low-dropout Regulator with Unconditional Stability and Low Quiescent Current. Communications, Circuits and Systems Proceedings, 2006 International Conference on Volume 4,25-28 June 2006 Page(s):2215– 2218.
[19] Hoon S.K, Chen S, Maloberti F, Chen J, Aravind B. A low noise high power supply rejection low dropout regulator for wireless system-on-chip applications.Custom Integrated Circuits Conference, 2005. Proceedings of the IEEE 200521-21 Sept. 2005 Page(s):759– 762.
[20] Xiaohua Fan, C. Mishra. Single Miller Capacitor Frequency Compensation Technique for Low-Power Multistage Amplifiers, IEEE J. Solid-State Circuits, vol. 40, no. 3, pp. 584-592, March.2005.
[21] G.A. Rincon-Mora, P.E. Allen. A low-voltage,low quiescent current, low drop-out regulator. IEEE J. Solid-State Circuits, vol.33.no.1, pp.36-44, jan.1998.
[22] Bang S.Lee. Technical Review of Low Dropout Voltage Regulator Operation and Performance, pplication Report, Texas Instruments, Aug. 1999.
[23] Honglai Wang. A CMOS Low-Dropout Regulator with New Compensation Method. Solid-State and Integrated Circuit Technology, ICSICT '06. 8th International Conference on 2006 Page(s):1508 - 1510.
[24]毛毳,何乐年,严晓浪。一种新型的全片内低噪声CMOS低压差线性稳压器。半导体学报,第29卷第8期,2008年8月。
[25] Yang Jinwen, Feng Quanyuan. Single Miller capacitor compensated multistage amplifiers for low dropout regulator. Microwave Conference Proceedings, APMC 2005. Asia-Pacific Conference Proceedings Volume 5, 4-7 Dec. 2005 Page(s):3 pp.
[26] Ker M.-D, Lo W.-Y Lee, C.-M Chen, C.-P Kao. H.-S. ESD protection design for 900MHz RF receiver with 8-kV HBM ESD robustness. IEEE Radio Frequency Integrated Circuits Symp. Dig., 2002, 427-430.
[27] Ker M.-D. Whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits for submicron CMOS VLSI. IEEE Trans. Electron Devices, 1999, 46, 173-183.
[2]精工电子有限公司S-817系列LDO数据手册。11-13页
[3]毕查德.拉扎维。模拟CMOS集成电路设计。西安:西安交通大学出版社,2003。284-327页。
[4] Phillip E.Al1en,Douglas R.Holberg(冯军,李智群译)。CMOS模拟集成电路设计(第二版).北京:电子工业出版社,2003。92-137页
[5]刘韬,徐志伟,程君侠。一种高电源抑制比CMOS能隙基准电压源.微电子学, Vo1.29,1999。
[6]王红义,土松林,来新泉,孙作治。CMOS电压基准的设计原理.微电子学,2003.10, 33(5):34-37。
[7]杨伟,李儒章。基于Cadence界面的工艺设计包设计方法.微电子学2005.10。504-508页。
[8]徐静萍,来新泉。基于CMOS工艺的低噪声高稳定性LDO的设计.半导体技术,第32卷第12期。
[9]陈碧,罗岚,周帅林。一种低温漂CMOS带隙基准电压源的设计.电子器件, 2004.3, 27(1):79一82。
[10]杨锦文,冯全源。基于嵌入式密勒补偿技术的LDO放大器设计.微电子学与计算机,2006年,第23卷第3期。
[11]郭鹏,沈相国。.LDO的三种频率补偿方案实现.电子器件,第29卷第3期, 2006年9月。
[12] Yueming Jiang, Lee E.K.F. A low voltage low 1/f noise CMOS bandgap reference. Circuits and Systems, ISCAS 2005. IEEE International Symposium on 23-26 May 2005 Page(s):3877 - 3880 Vol. 4.
[13]Yueming Jiang, Lee E.K.F. A 1.2 V bandgap reference based on transimpedance amplifier. Circuits and Systems ISCAS 2000 Geneva.The 2000 IEEE International Symposium on Volume 4, 28-31 May 2000 Page(s):261 - 264 vol.4.
[14] Gunawan M, Meijer G.C.M, Fonderie J, Huijsing J.H. A curvature-corrected low-voltage bandgap reference. Solid-State Circuits, IEEE Journal of Volume 28, Issue 6, June 1993 Page(s):667– 670.
[15] Xinpeng Xing, Zhihua Wang, Dongmei Li. A low voltage high precision CMOS bandgap reference. Norchip, 2007 19-20 Nov. 2007 Page(s):1– 4.
[16] Haibo Wang, Lanlan Liu, Xin Liu,Guotong Du, Yuchun Chang. An Improved Compensated-Temperature and High PSRR Bandgap Reference Circuit Design. Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on2006 Page(s):1742– 1744.
[17] Tom Kugelstadt. Fundamental Theory of PMOS Low-Dropout Voltage Regulators, TI Company, Inc.,1999.
[18] Dongpo Chen,Lenian He and Xiaolang Yan. A Low-dropout Regulator with Unconditional Stability and Low Quiescent Current. Communications, Circuits and Systems Proceedings, 2006 International Conference on Volume 4,25-28 June 2006 Page(s):2215– 2218.
[19] Hoon S.K, Chen S, Maloberti F, Chen J, Aravind B. A low noise high power supply rejection low dropout regulator for wireless system-on-chip applications.Custom Integrated Circuits Conference, 2005. Proceedings of the IEEE 200521-21 Sept. 2005 Page(s):759– 762.
[20] Xiaohua Fan, C. Mishra. Single Miller Capacitor Frequency Compensation Technique for Low-Power Multistage Amplifiers, IEEE J. Solid-State Circuits, vol. 40, no. 3, pp. 584-592, March.2005.
[21] G.A. Rincon-Mora, P.E. Allen. A low-voltage,low quiescent current, low drop-out regulator. IEEE J. Solid-State Circuits, vol.33.no.1, pp.36-44, jan.1998.
[22] Bang S.Lee. Technical Review of Low Dropout Voltage Regulator Operation and Performance, pplication Report, Texas Instruments, Aug. 1999.
[23] Honglai Wang. A CMOS Low-Dropout Regulator with New Compensation Method. Solid-State and Integrated Circuit Technology, ICSICT '06. 8th International Conference on 2006 Page(s):1508 - 1510.
[24]毛毳,何乐年,严晓浪。一种新型的全片内低噪声CMOS低压差线性稳压器。半导体学报,第29卷第8期,2008年8月。
[25] Yang Jinwen, Feng Quanyuan. Single Miller capacitor compensated multistage amplifiers for low dropout regulator. Microwave Conference Proceedings, APMC 2005. Asia-Pacific Conference Proceedings Volume 5, 4-7 Dec. 2005 Page(s):3 pp.
[26] Ker M.-D, Lo W.-Y Lee, C.-M Chen, C.-P Kao. H.-S. ESD protection design for 900MHz RF receiver with 8-kV HBM ESD robustness. IEEE Radio Frequency Integrated Circuits Symp. Dig., 2002, 427-430.
[27] Ker M.-D. Whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits for submicron CMOS VLSI. IEEE Trans. Electron Devices, 1999, 46, 173-183.