超宽带环振锁相环研究与设计
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摘要
几乎所有的现代通信系统都需要稳定的周期信号——时钟来提供基本的时序基础。周期时钟信号的产生由于受制造工艺的限制成为高速通信系统急需解决的问题,这些时钟信号一般由锁相环电路产生。本文系统研究了锁相环的环路稳定性能、环路噪声性能,和模块电路设计。从片内集成易行性、小面积、多相位角度出发,选择环形振荡器作为电路核心,研究和实现应用于多边带频分复用超宽带无线接收器中的锁相环设计。
首先,从锁相技术基本理论出发,提出了基于开环最大阈值法的三阶闭环设计方法。这种方法是对已有的二阶闭环近似分析三阶锁相环方法的改进,其对锁相环线性建模真实反应了环路的动态特性,且比传统的三阶闭环分析更直观、简单。同时详细推导了三阶线性模型的输入阶跃响应,并给出了对应的三阶开环(波特图)和三阶闭环(根轨迹)的分析与验证。接着结合模块电路噪声特性分析了环路的噪声性能,根据超宽带系统指标特点使用最小带内积分噪声设计方法确定了环路带宽,对稳定性、噪声和功耗性能进行了权衡,给出了环路参数设计的完整流程。
然后,系统总结了现有的环振噪声分析理论,分析了各种结构电路对几类噪声源的反应机制。并针对高频、低功耗、低噪声环振设计要求,以及高频应用下环振VCO的工艺和温度相关频偏与小增益的矛盾,提出并设计了两种新型电路,均使用0.18μm标准CMOS工艺,1.6V电源电压,经流片验证,测试结果均符合设计目的。
最后,对锁相环中重要模块电荷泵电路和高频分频器进行了详尽的分析并设计了满足设计指标的电路。其中在电荷泵电路分析中给出了环路参考时钟频率杂散和电荷泵噪声的理论推导,设计了高匹配度的电荷泵电路。在高频分频器分析中从多个角度分析了共源耦合结构分频器的工作原理,从而指导电路低功耗设计,并提出了输出幅度稳定,宽工作频率范围的高频分频器。
Almost all modern communication systems need stable periodic signals,clocks, to provide basic timing for functions.The generation of stable periodic signal has been an urgent issue to be resolved due to the fabrication process limitation.This thesis has systematically researched the phase-locked-loop from the aspects of loop stability,loop noise performance and blocking circuit design.Also one low-cost high-performance PLL for MB(Multi-band)-OFDM(Orthogonal Frequency Division Multiplexing) UWB(Ultra Wide Band) transceiver have been designed where ring oscillator is chosen as the core circuit considering the factors like feasibility of integration,small area and multiple phases.
First of all,a new 3-order close-loop linear model promised with the highest phase margin of the 3-order PLL loop is proposed,which updates the 2-order close-loop and 3-order open-loop models.Detailed reasoning procedure of input transient response for PLL 3-order linear model,along with its open-loop bode and close-loop locus root have been obtained to guide the loop stability design. Meanwhile,the optimum open loop bandwidth has been chosen to obtain the minimum integral phase noise in loop band.Then,in order to trade off between the cost and performance of super-fine phase when realizing the low-noise low-power high-performance PLL for UWB application,a optimum loop parameter design flow is tabled.
Then,the thesis has summarized several noise models for oscillator from the side of applicability in form of noise source and ciruit respose mechanism.And in order to trade off between small gain and large frequency variation due to process and temperature fluctuation in high frequency application when realizing the low-jitter low-power high-performance VCO,two novel ring oscillators have been silicon-provided satisfying the requirernent,which have been implemented in 0.18-um standard CMOS process under 1.6 supply voltage.
Finally,a reasoned analysis on charge pump and high-frequency divider was brought forward and directed the circuit desgin.Following the discussion on reference super and noise of CP,a high performance charge pump was shown.And the present divider can work under large frequency range with stable output amplitude.
首先,从锁相技术基本理论出发,提出了基于开环最大阈值法的三阶闭环设计方法。这种方法是对已有的二阶闭环近似分析三阶锁相环方法的改进,其对锁相环线性建模真实反应了环路的动态特性,且比传统的三阶闭环分析更直观、简单。同时详细推导了三阶线性模型的输入阶跃响应,并给出了对应的三阶开环(波特图)和三阶闭环(根轨迹)的分析与验证。接着结合模块电路噪声特性分析了环路的噪声性能,根据超宽带系统指标特点使用最小带内积分噪声设计方法确定了环路带宽,对稳定性、噪声和功耗性能进行了权衡,给出了环路参数设计的完整流程。
然后,系统总结了现有的环振噪声分析理论,分析了各种结构电路对几类噪声源的反应机制。并针对高频、低功耗、低噪声环振设计要求,以及高频应用下环振VCO的工艺和温度相关频偏与小增益的矛盾,提出并设计了两种新型电路,均使用0.18μm标准CMOS工艺,1.6V电源电压,经流片验证,测试结果均符合设计目的。
最后,对锁相环中重要模块电荷泵电路和高频分频器进行了详尽的分析并设计了满足设计指标的电路。其中在电荷泵电路分析中给出了环路参考时钟频率杂散和电荷泵噪声的理论推导,设计了高匹配度的电荷泵电路。在高频分频器分析中从多个角度分析了共源耦合结构分频器的工作原理,从而指导电路低功耗设计,并提出了输出幅度稳定,宽工作频率范围的高频分频器。
Almost all modern communication systems need stable periodic signals,clocks, to provide basic timing for functions.The generation of stable periodic signal has been an urgent issue to be resolved due to the fabrication process limitation.This thesis has systematically researched the phase-locked-loop from the aspects of loop stability,loop noise performance and blocking circuit design.Also one low-cost high-performance PLL for MB(Multi-band)-OFDM(Orthogonal Frequency Division Multiplexing) UWB(Ultra Wide Band) transceiver have been designed where ring oscillator is chosen as the core circuit considering the factors like feasibility of integration,small area and multiple phases.
First of all,a new 3-order close-loop linear model promised with the highest phase margin of the 3-order PLL loop is proposed,which updates the 2-order close-loop and 3-order open-loop models.Detailed reasoning procedure of input transient response for PLL 3-order linear model,along with its open-loop bode and close-loop locus root have been obtained to guide the loop stability design. Meanwhile,the optimum open loop bandwidth has been chosen to obtain the minimum integral phase noise in loop band.Then,in order to trade off between the cost and performance of super-fine phase when realizing the low-noise low-power high-performance PLL for UWB application,a optimum loop parameter design flow is tabled.
Then,the thesis has summarized several noise models for oscillator from the side of applicability in form of noise source and ciruit respose mechanism.And in order to trade off between small gain and large frequency variation due to process and temperature fluctuation in high frequency application when realizing the low-jitter low-power high-performance VCO,two novel ring oscillators have been silicon-provided satisfying the requirernent,which have been implemented in 0.18-um standard CMOS process under 1.6 supply voltage.
Finally,a reasoned analysis on charge pump and high-frequency divider was brought forward and directed the circuit desgin.Following the discussion on reference super and noise of CP,a high performance charge pump was shown.And the present divider can work under large frequency range with stable output amplitude.
引文
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[3].Tai-You Lu,Wei-Zen Chen,"A 3-to-10GHz 14-band CMOS frequency synthesizer with spurs reduction for MB-OFDM UWB system",ISSCC Dig.Tech.Papers,Feb.2008,pp.126-127.
[4].O.Werther,M.Cavin,A.Schneider et al.,"A fully integrated 14-band 3.1-to-10.6GHz 0.13μm SiGe BiCMOS UWB RF transceiver",ISSCC Dig,.Tech.Papers,Feb.2008,pp.122-123.
[5].C.Mishra,A.Valdes-Garcia,"Frequency planning and synthesizer architectures for multiband OFDM UWB radios," IEEE Trans.On Microwave Theory and Tech.,Dec.2005,vol.53,no.12,pp.3744-3756
[6].B.Razavi,T.Aytur,F.-R.Yang et al.,"A 0.13 μm CMOS UWB transceiver," in ISSCC Dig.Tech.Papers,Feb.2005,pp.216 217.
[7].T.Aytur,H-C.Kang,R.Mahadevappa,et al.,"A fully integrated UWB PHY in 0.13um CMOS",ISSCC Dig.Tech.Papers,Feb.2006,pp.124-125.
[8].Geum-Young Tak,Seok-Bong Hyun,Tae Young Kang el al.,"A 6.3-9-GHz CMOS fast settling PLL for MB-OFDM UWB applications," IEEE Journal of Solid-State Circuits,August 2005,vol.40,no.8,pp.1671-1679.
[9].Aly Ismail and Asad A.Abidi,"A 3.1-to-8.2GHz Zero-IF receiver and direct frequency synthesizer in 0.18-μm SiGe BiCMOS for Mode-2 MB-OFDM UWB communication," IEEE Journal of Solid-State Circuits,Dec.2005,vol.40,no.12,pp.2573-2582.
[10].Hui Zheng and Howard C.Luong,"A 1.5V 3.1GHz-8GHz CMOS synthesizer for 9-band MB-OFDM UWB transceivers",IEEE Journal of Solid-State Circuits,June 2007,vol.42,no.6,pp.1250-1260.
[11].Jri Lee,Da-Wei Chiu,"A 7-band 3-SGHz frequency synthesizer with lns band-switching time in 0.18μm CMOS technology," ISSCC Dig.Tech.Papers,Feb.2005,pp.204-205.
[12].Jri Lee,"A 3-to-8GHz fast-hopping frequency synthesizer in 0.18-μm CMOS technology," IEEE Journal of Solid-State Circuits,March 2006,vol.41,no.3,pp.566-573.
[13].Behazd Razavi,"Design of Analog CMOS Integrated Circuits",The McGraw-Hill Companies,Inc,2001
[14].P.Vancorenland and M.Steyaert,"A 1.57-GHz fully integrated very low-phase-noise quadrature VCO",IEEE Journal of Solid-State-Circuits,vol.37,pp.653-656,May 2002
[15].Andrea Lacaita,Salvatore Levantino,and Carlo Samori,"integrated frequency synthesizers for wireless systerms",cambridge university press,2007
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[18].A.Garcia Armada,Understanding the effect of phase noise in orthogonal frequency division multiplexing(OFDM),IEEE T.Broadcast.,41,Jun.2001,153-9.
[19].L.Piazzo and P.Mandarini,Analysis of phase noise effects in OFDM modems,IEEE T.Commun.,50,Oct.2002,1696-1705
[20].F.M.Gardner,Charge-pump phase-lock loops,IEEE T.Commun.,28,Nov.1980,1849-58.
[21].M.Johnson and E.Hudson,"A variable delay line PLL for CPU coprocessor synchronization,"IEEE Journal of Solid-State Circuits,vol.23,pp.1218-1223,Oct.1988
[22].I.A.Young,J.K.Greason,and K.L.Wong,"A PLL Clock Generator with 5 to 110MHz of Lock Range for Microprocessors," IEEE Journal of Solid-State Circuits,vol.27,pp.1599-1607,Nov.1992.
[23].Woogeun Rhee,"Design of Hign-Perfonnance CMOS Charge Pumps In Phase-Locked Loops",IEEE International Symposium on Circuit and System,May.1999,pp.Ⅱ545-548
[24].Jae-Shin Lee,Min-Sun Keel,Shin-I1 Lim and Suki Kim,"Charge pump with perfect current matchingcharacteristics in phase-locked loops",Electronics letters,vol.36,pp.1907-1908,Nov.2000
[25].Geum-Young Tak,Seok-Bong Hyun,Tae Young Kang,et.al,"A 6.3-9-GHz CMOS Fast Settling PLL for MB-OFDM UWB Applications",IEEE Journal of Solid-state Circuits,vol.40,pp.1671-1679,Aug.2005
[26].江旭东,”应用于MB-OFDM UWB系统的频率综合器的研究与设计”,复旦大学硕士学位论文,2008
[27].何捷,“DVB-T接收机中频率综合器的研究”,复旦大学博士学位论文,2005.
[28].陆平,”应用于宽带数据通信的CMOS环振型频率综合器研究”,复旦大学博士学位论文,2007
[29].Alan V.Oppenheim,Alan S.Willsky with S.Hamid Nawab,"Signal and System",Prentice-Hall,1997
[30].Cicero S.Vaucher,Architectures for RF frequency synthesizers,Kluwer Academic Publishers,2002
[31].A.Hajimiri,S.Limotyrakis,T.H.Lee,"Phase noise in multi-gigahertz CMOS ring oscillators",in Proceedings of IEEE Custom Integrated Circuit Conference,May 1998,pp.49-52
[32].B.Razavi,"A Study of Phase Noise in CMOS Oscillator",IEEE Journal of Solid-State Circuits,vol.31,pp.331-343,Mar.1996
[33].A.Hajimiri,T.H.Lee,"A General Theory of Phase Noise in Electrical scillators",IEEE Journal of Solid-State Circuits,vol.33,pp.179-194,Feb.1998
[34].A.Hajimiri,S.Limotyrakis,T.H.Lee,"Jitter and Phase Noise in Ring Oscillators",IEEE Journal of Solid-State Circuits,vol.34,pp.790-804,Jun.1999
[35].Liang Dai,Ramesh Harjani,"Design of Low-Phase-Noise CMOS Ring scillators",IEEE Transaction on Circuits and Systems,vol.45,pp.328-338,May.2002
[36].D.B.Lesson,"A Simple of Feedback Oscillator Noise Spectrum",in Proceedings of IEEE,vol.54,Feb.1966,pp.329-330
[37].John G.Maneatis,"Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques",IEEE Journal of Solid-State Circuits,vol.31,pp.1723-1732,Nov.1996
[38].邓晶晶,李宁,李巍,”正交输出、双调谐、高性能4.488GHz环形振荡器设计”,复旦学报(自然科学版),2008.6,vol.47,No.6,743-748
[39].T.-H.Lin and W.J.Kaiser," A 900-MHz 2.5-mA CMOS frequency synthesizer with an automatic SC tuning loop",IEEE J.Solid-State Circuit,vol.36,no.3,pp.424-431,Mar.2001
[40].A.Aktas and M.Ismail,"CMOS PLL calibration techniques," IEEE Circuits Devices Mag.,vol.20,no.5,pp.6-11,Sept./Oct.2004
[41].W.B.Wilson,U.Moon,K.R.Lakshmilumar,and L.Dai,"A CMOS self-calibration frequency synthesizer," IEEE J.Solid-State Circuit,vol.35,no.10,pp.1437-1444,Oct.2000
[42].Frank Herzel,Gunter Fischer,and Hans Gustat,"An Integrated CMOS RF Synthesizer for 802.11a Wireless LAN",IEEE J.Solid-State Circuits,Vol.38,No.10,pp 1767-1770,2003
[43].Liu H Q,Goh W L,Siek L.A 0.18-μm 10-GHz CMOS ring oscillator for optical transceivers [EB/OL].(2005-07-25)[2007-08-10].http://ieeexplore.ieee.org/ie15/9898/31469/01464890.pdf
[44].Eken Y A,Uyemura J P.A 5.9-GHz voltage-controlled ring oscillator in 0.18-μm CMOS[J],IEEE JSSC,2004,39(1):230-233.
[45].Liu H Q,Goh W L,Siek L.A 0.18-μm 10-GHz CMOS ring oscillator for optical transceivers [EB/OL].(2005-07-25)[2007-08-10].http://ieeexplore.ieee.org/ie15/9898/31469/01464890.pdf.
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[49].U.Singh and M.Green,"Dynamics of High-Frequency CMOS Dividers," IEEE proc.ISCAS,vol.5,pp.26-29,2002.5
[2].C.-F.Liang,S.-I.Liu,Y.-H.Chen et al.,"14-band frequency synthesizer for MB-OFDM UWB application," ISSCC Dig.Tech.Papers,Feb.2006,pp.126-127
[3].Tai-You Lu,Wei-Zen Chen,"A 3-to-10GHz 14-band CMOS frequency synthesizer with spurs reduction for MB-OFDM UWB system",ISSCC Dig.Tech.Papers,Feb.2008,pp.126-127.
[4].O.Werther,M.Cavin,A.Schneider et al.,"A fully integrated 14-band 3.1-to-10.6GHz 0.13μm SiGe BiCMOS UWB RF transceiver",ISSCC Dig,.Tech.Papers,Feb.2008,pp.122-123.
[5].C.Mishra,A.Valdes-Garcia,"Frequency planning and synthesizer architectures for multiband OFDM UWB radios," IEEE Trans.On Microwave Theory and Tech.,Dec.2005,vol.53,no.12,pp.3744-3756
[6].B.Razavi,T.Aytur,F.-R.Yang et al.,"A 0.13 μm CMOS UWB transceiver," in ISSCC Dig.Tech.Papers,Feb.2005,pp.216 217.
[7].T.Aytur,H-C.Kang,R.Mahadevappa,et al.,"A fully integrated UWB PHY in 0.13um CMOS",ISSCC Dig.Tech.Papers,Feb.2006,pp.124-125.
[8].Geum-Young Tak,Seok-Bong Hyun,Tae Young Kang el al.,"A 6.3-9-GHz CMOS fast settling PLL for MB-OFDM UWB applications," IEEE Journal of Solid-State Circuits,August 2005,vol.40,no.8,pp.1671-1679.
[9].Aly Ismail and Asad A.Abidi,"A 3.1-to-8.2GHz Zero-IF receiver and direct frequency synthesizer in 0.18-μm SiGe BiCMOS for Mode-2 MB-OFDM UWB communication," IEEE Journal of Solid-State Circuits,Dec.2005,vol.40,no.12,pp.2573-2582.
[10].Hui Zheng and Howard C.Luong,"A 1.5V 3.1GHz-8GHz CMOS synthesizer for 9-band MB-OFDM UWB transceivers",IEEE Journal of Solid-State Circuits,June 2007,vol.42,no.6,pp.1250-1260.
[11].Jri Lee,Da-Wei Chiu,"A 7-band 3-SGHz frequency synthesizer with lns band-switching time in 0.18μm CMOS technology," ISSCC Dig.Tech.Papers,Feb.2005,pp.204-205.
[12].Jri Lee,"A 3-to-8GHz fast-hopping frequency synthesizer in 0.18-μm CMOS technology," IEEE Journal of Solid-State Circuits,March 2006,vol.41,no.3,pp.566-573.
[13].Behazd Razavi,"Design of Analog CMOS Integrated Circuits",The McGraw-Hill Companies,Inc,2001
[14].P.Vancorenland and M.Steyaert,"A 1.57-GHz fully integrated very low-phase-noise quadrature VCO",IEEE Journal of Solid-State-Circuits,vol.37,pp.653-656,May 2002
[15].Andrea Lacaita,Salvatore Levantino,and Carlo Samori,"integrated frequency synthesizers for wireless systerms",cambridge university press,2007
[16].B.Razavi,RF Microelectronics,New York,NY:Prentice-Hall,1997.
[17].T.H.Lee,The Design of CMOS Radio-Frequency Integrated Circuits,Cambridge,UK:Cambridge University Press,1998,2nd edn,2004.
[18].A.Garcia Armada,Understanding the effect of phase noise in orthogonal frequency division multiplexing(OFDM),IEEE T.Broadcast.,41,Jun.2001,153-9.
[19].L.Piazzo and P.Mandarini,Analysis of phase noise effects in OFDM modems,IEEE T.Commun.,50,Oct.2002,1696-1705
[20].F.M.Gardner,Charge-pump phase-lock loops,IEEE T.Commun.,28,Nov.1980,1849-58.
[21].M.Johnson and E.Hudson,"A variable delay line PLL for CPU coprocessor synchronization,"IEEE Journal of Solid-State Circuits,vol.23,pp.1218-1223,Oct.1988
[22].I.A.Young,J.K.Greason,and K.L.Wong,"A PLL Clock Generator with 5 to 110MHz of Lock Range for Microprocessors," IEEE Journal of Solid-State Circuits,vol.27,pp.1599-1607,Nov.1992.
[23].Woogeun Rhee,"Design of Hign-Perfonnance CMOS Charge Pumps In Phase-Locked Loops",IEEE International Symposium on Circuit and System,May.1999,pp.Ⅱ545-548
[24].Jae-Shin Lee,Min-Sun Keel,Shin-I1 Lim and Suki Kim,"Charge pump with perfect current matchingcharacteristics in phase-locked loops",Electronics letters,vol.36,pp.1907-1908,Nov.2000
[25].Geum-Young Tak,Seok-Bong Hyun,Tae Young Kang,et.al,"A 6.3-9-GHz CMOS Fast Settling PLL for MB-OFDM UWB Applications",IEEE Journal of Solid-state Circuits,vol.40,pp.1671-1679,Aug.2005
[26].江旭东,”应用于MB-OFDM UWB系统的频率综合器的研究与设计”,复旦大学硕士学位论文,2008
[27].何捷,“DVB-T接收机中频率综合器的研究”,复旦大学博士学位论文,2005.
[28].陆平,”应用于宽带数据通信的CMOS环振型频率综合器研究”,复旦大学博士学位论文,2007
[29].Alan V.Oppenheim,Alan S.Willsky with S.Hamid Nawab,"Signal and System",Prentice-Hall,1997
[30].Cicero S.Vaucher,Architectures for RF frequency synthesizers,Kluwer Academic Publishers,2002
[31].A.Hajimiri,S.Limotyrakis,T.H.Lee,"Phase noise in multi-gigahertz CMOS ring oscillators",in Proceedings of IEEE Custom Integrated Circuit Conference,May 1998,pp.49-52
[32].B.Razavi,"A Study of Phase Noise in CMOS Oscillator",IEEE Journal of Solid-State Circuits,vol.31,pp.331-343,Mar.1996
[33].A.Hajimiri,T.H.Lee,"A General Theory of Phase Noise in Electrical scillators",IEEE Journal of Solid-State Circuits,vol.33,pp.179-194,Feb.1998
[34].A.Hajimiri,S.Limotyrakis,T.H.Lee,"Jitter and Phase Noise in Ring Oscillators",IEEE Journal of Solid-State Circuits,vol.34,pp.790-804,Jun.1999
[35].Liang Dai,Ramesh Harjani,"Design of Low-Phase-Noise CMOS Ring scillators",IEEE Transaction on Circuits and Systems,vol.45,pp.328-338,May.2002
[36].D.B.Lesson,"A Simple of Feedback Oscillator Noise Spectrum",in Proceedings of IEEE,vol.54,Feb.1966,pp.329-330
[37].John G.Maneatis,"Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques",IEEE Journal of Solid-State Circuits,vol.31,pp.1723-1732,Nov.1996
[38].邓晶晶,李宁,李巍,”正交输出、双调谐、高性能4.488GHz环形振荡器设计”,复旦学报(自然科学版),2008.6,vol.47,No.6,743-748
[39].T.-H.Lin and W.J.Kaiser," A 900-MHz 2.5-mA CMOS frequency synthesizer with an automatic SC tuning loop",IEEE J.Solid-State Circuit,vol.36,no.3,pp.424-431,Mar.2001
[40].A.Aktas and M.Ismail,"CMOS PLL calibration techniques," IEEE Circuits Devices Mag.,vol.20,no.5,pp.6-11,Sept./Oct.2004
[41].W.B.Wilson,U.Moon,K.R.Lakshmilumar,and L.Dai,"A CMOS self-calibration frequency synthesizer," IEEE J.Solid-State Circuit,vol.35,no.10,pp.1437-1444,Oct.2000
[42].Frank Herzel,Gunter Fischer,and Hans Gustat,"An Integrated CMOS RF Synthesizer for 802.11a Wireless LAN",IEEE J.Solid-State Circuits,Vol.38,No.10,pp 1767-1770,2003
[43].Liu H Q,Goh W L,Siek L.A 0.18-μm 10-GHz CMOS ring oscillator for optical transceivers [EB/OL].(2005-07-25)[2007-08-10].http://ieeexplore.ieee.org/ie15/9898/31469/01464890.pdf
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