面向SRAM型FPGA软错误的可靠性评估与容错算法研究
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摘要
计算可靠性一直以来都是集成电路设计和应用领域所关注的热点问题之一。随着集成电路制造工艺的不断进步和电路集成度的持续增加，由高能粒子辐射和噪声干扰造成的软错误问题也正在日益拓展的FPGA应用领域中逐步显现出来。增强FPGA芯片及系统容软错误的能力，提高其系统可靠性已经成为FPGA的设计领域面对的重要技术问题。
软错误是诸如静态存储单元的存储状态随机发生改变的一种现象。针对软错误效应的可靠性评估与容错防护设计是高可靠FPGA设计的关键技术。传统的针对FPGA的可靠性评估往往需要在流片后利用加速的高能粒子照射获得，但这种方法无益于设计阶段尽早地开展面向软错误的可靠性设计需求。同时，针对当前设计期间FPGA的软错误评估方法缺乏结构完整性以及统一量化的评估指标等问题，本文根据软错误的形成机理，面向FPGA不同结构元素的微结构对软错误进行行为模式的建模，并提出了一个统一的软错误敏感度评估指标和方法，为量化分析FPGA软错误问题提供了新的依据；在此基础上，本文构建了一个面向FPGA配置字软错误的可靠性评估流程和评估工具，有效拓展了设计期间对FPGA软错误效应的分析能力。实践表明，该工具可以帮助识别FPGA中对软错误敏感的结构元素，为容软错误的可靠性设计和开发提供合理的指导和帮助。
在上述工具的基础上，本文进一步研究了面向FPGA配置字软错误的容错缓解技术。鉴于目标应用的特点，本文旨在探求以较低容错代价获得提升FPGA可靠性的方法。根据以上目标，本文深入分析了软错误在FPGA电路中产生、传播和显现的过程；并从FPGA的微结构和固有冗余出发，首次提出了一种面向布线资源配置字软错误和一种面向逻辑资源配置字软错误的原地容错缓解算法。不同于其它容错方法所带来的巨大面积、功耗和性能的开销，本文提出的这两种算法都基于原地重配置的思想，不需要改动既有的FPGA布局布线结果，从而具有最小的面积、性能及功耗损失。实验表明，本文提出的方法能够有效降低配置字软错误引发的FPGA功能失效概率，并与其它方法具有良好的兼容性，能够有效地确保FPGA开发周期的收敛。
最后，本文对三模冗余方法的实际应用也进行了深入的研究，结合敏感度指标并利用组合概率首次对三模冗余结构的容错性能进行了理论分析，为容错系统的合理设计提供了理论的参考。同时在所提出的统一化软错误评估指标和方法的基础上，结合多种容错方法形成了一套面向FPGA软错误的综合评估和优化平台，为FPGA软错误问题的缓解提供了自动化的优化工具，从而有效解决了FPGA软错误的评估和优化问题。
软错误的评估和容错设计是学术界和工业界关注的焦点。本文提出的软错误可靠性评估方法和容软错误缓解技术，可以有效地帮助FPGA设计和开发人员提升FPGA应用的容软错误能力，具有良好的理论意义和实际应用价值。
Computing reliability has been one of the key problems for VLSI designs andapplications. With the continuous advancing in VLSI manufacturing technology andever increasing integrity in VLSI designs, the soft error issue due to radiation fromhigh energy particles and circuit internal noise begins to emerge in the FPGA-basedapplications, which can cause significant reliability degradation. Aiming for morereliable computing, enhancing the robustness of FPGA devices and systems withrespect to the soft error problem is already a challenge for both the FPGA designersand developers.
Soft error is known as the phenomena of a random memory status change in astatic memory cell. Reliability evaluation and fault mitigation for soft errors isgenerally acknowledged as two key problems in FPGA designs. However, traditionalevaluation of FPGA reliability is based on field testing on fabricated devices usingaccelerated particles, which is already too late to change the design if the reliabilityrequirements are not met. At the same time, current method for design time reliabilityevaluation does not cover all structures in FPGA and lacks of a unified metric for aquantitative evaluation. To this problem, after detailed studies on the mechanism ofsoft errors and modeling of their behaviors from the perspective of FPGA micro-architectures in chapter III, this dissertation first proposes a unified metric ofcriticality to evaluate the sensitivity of soft errors towards failures. Then, an exclusiveevaluating framework for FPGA soft errors is presented, which can effectivelyanalyze the soft error effect as early as possible during the design phase. Theframework has demonstrated its practical use, such as identifying sensitive circuitelements, and providing insightful guidance to FPGA designs and applications againstsoft errors.
Based on the presented framework above, techniques for soft error mitigation onFPGA devices are further investigated in this dissertation. Targeting on mitigation with reasonable overhead on circuit elements that cause higher reliability degradation,this dissertation commences from the studies on soft error occurrence, propagationand manifesting. Motivated from the micro-architecture and inherent redundancy inFPGA, this dissertation for the first time proposes two mitigating algorithms targetingon soft errors in routing and logic resources, respectively. Different from traditionalmitigating techniques which involve higher overhead in area, power and performance,the proposed methods apply in-place reassignment techniques, preserve detailedFPGA placement and routing, and thus incur minimum overhead. The experimentresults have demonstrated significant reductions on soft error induced circuit failuresrates. Our methods are highly compatible to other mitigating methods, and help toguarantee the tight design closure in FPGA design.
In addition, the widely used Triple Modular Redundancy (TMR) technique onsoft error mitigation is also studied in this dissertation. To estimate the reliability of aTMR system, this dissertation applies combinational probabilistic analysis with themetric of criticality, and for the first time provides TMR reliability estimation bytaking the inherent circuit logic masking capability into account. This study will beuseful towards a moderate FPGA design against the soft error issue. At the same time,this dissertation integrates the unified evaluating metric and mitigating methods into acomprehensive and automatic optimization framework, which greatly helps to the softerror evaluation and mitigation problem in FPGA.
The evaluation and mitigation on soft errors in FPGA-based systems is becominga concerning issue for both academia and industry. The proposed soft error evaluationframework and mitigating techniques have demonstrated their effectiveness, andprovided theoretical significance and practical applicability to the critical reliabilityissue in FPGAs.
软错误是诸如静态存储单元的存储状态随机发生改变的一种现象。针对软错误效应的可靠性评估与容错防护设计是高可靠FPGA设计的关键技术。传统的针对FPGA的可靠性评估往往需要在流片后利用加速的高能粒子照射获得，但这种方法无益于设计阶段尽早地开展面向软错误的可靠性设计需求。同时，针对当前设计期间FPGA的软错误评估方法缺乏结构完整性以及统一量化的评估指标等问题，本文根据软错误的形成机理，面向FPGA不同结构元素的微结构对软错误进行行为模式的建模，并提出了一个统一的软错误敏感度评估指标和方法，为量化分析FPGA软错误问题提供了新的依据；在此基础上，本文构建了一个面向FPGA配置字软错误的可靠性评估流程和评估工具，有效拓展了设计期间对FPGA软错误效应的分析能力。实践表明，该工具可以帮助识别FPGA中对软错误敏感的结构元素，为容软错误的可靠性设计和开发提供合理的指导和帮助。
在上述工具的基础上，本文进一步研究了面向FPGA配置字软错误的容错缓解技术。鉴于目标应用的特点，本文旨在探求以较低容错代价获得提升FPGA可靠性的方法。根据以上目标，本文深入分析了软错误在FPGA电路中产生、传播和显现的过程；并从FPGA的微结构和固有冗余出发，首次提出了一种面向布线资源配置字软错误和一种面向逻辑资源配置字软错误的原地容错缓解算法。不同于其它容错方法所带来的巨大面积、功耗和性能的开销，本文提出的这两种算法都基于原地重配置的思想，不需要改动既有的FPGA布局布线结果，从而具有最小的面积、性能及功耗损失。实验表明，本文提出的方法能够有效降低配置字软错误引发的FPGA功能失效概率，并与其它方法具有良好的兼容性，能够有效地确保FPGA开发周期的收敛。
最后，本文对三模冗余方法的实际应用也进行了深入的研究，结合敏感度指标并利用组合概率首次对三模冗余结构的容错性能进行了理论分析，为容错系统的合理设计提供了理论的参考。同时在所提出的统一化软错误评估指标和方法的基础上，结合多种容错方法形成了一套面向FPGA软错误的综合评估和优化平台，为FPGA软错误问题的缓解提供了自动化的优化工具，从而有效解决了FPGA软错误的评估和优化问题。
软错误的评估和容错设计是学术界和工业界关注的焦点。本文提出的软错误可靠性评估方法和容软错误缓解技术，可以有效地帮助FPGA设计和开发人员提升FPGA应用的容软错误能力，具有良好的理论意义和实际应用价值。
Computing reliability has been one of the key problems for VLSI designs andapplications. With the continuous advancing in VLSI manufacturing technology andever increasing integrity in VLSI designs, the soft error issue due to radiation fromhigh energy particles and circuit internal noise begins to emerge in the FPGA-basedapplications, which can cause significant reliability degradation. Aiming for morereliable computing, enhancing the robustness of FPGA devices and systems withrespect to the soft error problem is already a challenge for both the FPGA designersand developers.
Soft error is known as the phenomena of a random memory status change in astatic memory cell. Reliability evaluation and fault mitigation for soft errors isgenerally acknowledged as two key problems in FPGA designs. However, traditionalevaluation of FPGA reliability is based on field testing on fabricated devices usingaccelerated particles, which is already too late to change the design if the reliabilityrequirements are not met. At the same time, current method for design time reliabilityevaluation does not cover all structures in FPGA and lacks of a unified metric for aquantitative evaluation. To this problem, after detailed studies on the mechanism ofsoft errors and modeling of their behaviors from the perspective of FPGA micro-architectures in chapter III, this dissertation first proposes a unified metric ofcriticality to evaluate the sensitivity of soft errors towards failures. Then, an exclusiveevaluating framework for FPGA soft errors is presented, which can effectivelyanalyze the soft error effect as early as possible during the design phase. Theframework has demonstrated its practical use, such as identifying sensitive circuitelements, and providing insightful guidance to FPGA designs and applications againstsoft errors.
Based on the presented framework above, techniques for soft error mitigation onFPGA devices are further investigated in this dissertation. Targeting on mitigation with reasonable overhead on circuit elements that cause higher reliability degradation,this dissertation commences from the studies on soft error occurrence, propagationand manifesting. Motivated from the micro-architecture and inherent redundancy inFPGA, this dissertation for the first time proposes two mitigating algorithms targetingon soft errors in routing and logic resources, respectively. Different from traditionalmitigating techniques which involve higher overhead in area, power and performance,the proposed methods apply in-place reassignment techniques, preserve detailedFPGA placement and routing, and thus incur minimum overhead. The experimentresults have demonstrated significant reductions on soft error induced circuit failuresrates. Our methods are highly compatible to other mitigating methods, and help toguarantee the tight design closure in FPGA design.
In addition, the widely used Triple Modular Redundancy (TMR) technique onsoft error mitigation is also studied in this dissertation. To estimate the reliability of aTMR system, this dissertation applies combinational probabilistic analysis with themetric of criticality, and for the first time provides TMR reliability estimation bytaking the inherent circuit logic masking capability into account. This study will beuseful towards a moderate FPGA design against the soft error issue. At the same time,this dissertation integrates the unified evaluating metric and mitigating methods into acomprehensive and automatic optimization framework, which greatly helps to the softerror evaluation and mitigation problem in FPGA.
The evaluation and mitigation on soft errors in FPGA-based systems is becominga concerning issue for both academia and industry. The proposed soft error evaluationframework and mitigating techniques have demonstrated their effectiveness, andprovided theoretical significance and practical applicability to the critical reliabilityissue in FPGAs.
引文
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