次亚微米CMOS工艺下的ESD防护技术研究
摘要
随着硅基CMOS工艺技术的不断进步,器件的特征尺寸已缩减至纳米阶段,目的是提高芯片的集成度、性能和运算速度,并降低单位芯片的制造成本。但由于新工艺技术的应用及电路性能的提高,使静电放电(electrostatic discharge, ESD)防护设计的设计难度加大,使得近几年ESD防护技术的发展变缓。目前ESD相关方面的研究是以ESD防护的器件级建模为主,这种研究方法忽视了防护结构面积及寄生效应对实际生产的影响,使得理论成果对于芯片生产指导有限。因此国内主流代工厂生产出的芯片其ESD防护部分仍然以传统的二极管和MOS结构为主,而较小规模的芯片设计厂商不仅其产品的ESD防护设计水平更低,其自身制造水平也以次亚微米工艺为主
本论文采用华润上华0.6μm CSMC6S06DPDM-CT02CMOS工艺与香港应用科学与技术研究院(ASTRI)的相关ESD测试设备作为研究平台,以工艺—器件—电路—版图—全芯片作为研究主线,对次亚微米CMOS工艺条件下防护器件的ESD可靠性问题进行了系统研究。文中对现有ESD防护技术进行了全面的对比归纳,提出了多种全新的电路结构与版图布局方案。本论文的研究成果为次亚微米CMOS工艺条件下ESD防护技术的研究提供了理论依据。
本文的主要研究内容概括如下：
1.工艺与器件级ESD防护技术研究：通过对防护器件在ESD大电流条件下电、热特性的分析,得到了可用于定义仿真边界条件的器件失效量化表征量；利用器件的热平衡机理建立了ESD防护器件的解析模型；通过对ISE-TCAD中物理模型的对比研究,获得了可用于0.6μm CSMC6S06DPDM-CT02CMOS工艺条件下的ESD事件仿真优化物理模型；最后利用仿真与流片测试相结合的方法,对次亚微米工艺条件下源漏注入工艺、阱工艺、外延层与衬底工艺、栅氧工艺、Silicide工艺引起的ESD防护器件失效机理进行系统研究,并根据研究结论提出了改善各工艺条件下ESD防护器件性能的方案。
2.电路与版图级ESD防护技术研究：1)电阻部分：以扩散电阻作为研究对象,对其在ESD大电流条件下的电流饱和现象进行了深入研究,由于该现象限制了ESD电流的快速泄放,使得扩散电阻无法作为独立的ESD防护结构使用,流片测试得到的结果验证了研究理论的正确性；2)二极管部分：针对ESD大电流条件下的二极管正、反向特性进行了研究,获得了二极管阳极有效宽度与ESD防护性能之间的关系,并利用仿真与流片测试结果,设计出了一种能够最大化阳极宽度的环形叉指平行布线二极管防护结构；3)MOS部分：从ESD大电流条件下的栅极接地NMOS(gate grounded NMOS, ggNMOS) snapback特性入手,对ggNMOS结构重要的电学指标进行了研究,通过仿真与流片测试,获得了ggNMOS版图参数、结构参数与ESD鲁棒性之间的关系,并针对多指条结构的不均匀导通问题,利用MOS结构的寄生电容特性,设计出了一种能够抑制“触发死区”现象的改进型栅耦合栅接地NMOS(gate coupled gate grounded NMOS, gc-ggNMOS)防护结构；4)最后总结前述的研究结论,以多ESD泄放通路作为设计目标,创新性地设计出了一种单指双通路ESD防护结构,通过与传统ggNMOS结构的流片测试结果对比表明,该全新防护结构能够在全面提高ESD鲁棒性指标的同时,有效降低芯片面积,该防护结构最终通过了5000V的人体放电模式(human body model, HBM)(?)试。3.全芯片级ESD防护技术研究：在系统分析了各种测试条件下ESD电流径对全芯
片防护性能影响的基础上,通过传输线脉冲测试与失效分(transmission line pulsing, TLP)析研究,得到了总线杂散电容、电阻对全芯片防护设计影响的规律,并利用研究结果提出了可以提升芯片ESD耐压等级的版图布局方案；通过闩锁测试,分析了芯片端口处ESD防护结构形成闩锁的原因,并设计出了一种全新的抑制闩锁形成的版图布局方案。最终的研究结果显示,在不增加芯片面积、工艺步骤,且不影响核心电路正常工作的情况下,基于本文全芯片ESD防护设计理论制造出的HC132芯片最终通过了HBM条件下5000V的ESD耐压等级测试。全文最后根据总线串扰理论,提出了一种新的可以抑制ESD总线串扰的封装方案,将ESD防护设计方法从传统的片内设计扩展到了片外设计领域。
Along with the progress of silicon CMOS process technology, device’s feature size hasstepped into the nano-phase for the purpose to improve chip performance and operation speed,and to reduce cost of manufacture per chip as well. However, because of the generation ofnew technology and the improvement of circuit performance, the protection design of ESD(electrostatic discharge, ESD) is becoming more difficult. Therefore, ESD protectiontechnology has experienced a slowing development in recent years. Study on ESD is mainlyabout device-level modeling of ESD protection at present. This approach ignores the fact thatthe protection structure area and parasitic effect have some influence on actual production,which lead to limited guidance of theoretical results for chip production. So that the ESDprotection parts in chips of China’s mainstream foundry’s production are still mainly based ontraditional diodes and MOS structure. What’s more, ESD protection design level of smallerchip design manufacturer’s production is lower, and the production level itself is mostlysub-submicron technology-based.
This paper uses0.6m CSMC6S06DPDM-CT02CMOS technology and the Hong KongApplied Science and Technology Research Institute (ASTRI)’s ESD test equipment as aresearch platform, technology-device-circuit-layout-full chip as the main line, systematicallystudying the protection device’s ESD reliability issues under the conditions of sub-submicron.Existing ESD protection technologies are compared comprehensively in this paper. Moreover,a variety of new concept of circuit structure and scheme of layout are proposed. The paper’sresearch results provide a theoretical basis for the research of ESD protection technologyunder the condition of sub-submicron CMOS process.
The main contents of this paper are summarized as follows:
1. Study of process and device level ESD protection technology: By analyzing electricaland thermal characteristics of protection device under ESD high current, the value ofquantitative characteristics of device failure which can be used to define the simulationboundary condition is found. By using heat balance mechanism in devices, analytical modelof ESD protection device is established. Through comparing physical models in ISE-TCAD,an optimized physical model of ESD event simulation is obtained, which can be used under0.6m CSMC6S06DPDM-CT02CMOS process condition. Finally, this paper studies thefailure mechanism of ESD protection devices which is manufactured by source and drainsimplantation process, well process, epitaxial layer and substrate process, gate oxide processand Silicide process under sub-submicron process condition, and uses the research results topropose the scheme to improve characteristics of ESD protection device under all process conditions.
2. Study of circuit and layout level ESD protection technology:1) As for a resistor, thispaper uses diffusion resistance as object of study, and deeply studies its current saturationunder ESD high current condition. Since the phenomenon limits the ESD current rapiddischarge, diffusion resistance can not work as a separate ESD protection structure. The resultof chip test verifies the correctness of the research theory.2) For diode part, this paper studiesits forward and reverse characteristics under the condition of ESD high current, and finds therelationship between the effective width of the diode anode and ESD protection performance.Moreover, by using simulation and silicon test result, the diode with annular inter-digitalparallel wiring diode protection structure is designed to maximize the width of the anode.3)For MOS part, the paper starts from gate grounded NMOS, ggNMOS snapback characteristics,studies ggNMOS structure’s important electrical indicators, and obtains the relationshipbetween ggNMOS layout parameter, structure parameter and ESD robustness by simulatingand chip fabrication and test. Aiming at non-uniform conduction problem of multi-fingerstructure, by using the parasitic capacitance feature of MOS structure, this paper designs animproved gate coupled gate grounded NMOS gc-ggNMOS protection structure to inhibit thetrigger dead zone phenomenon.4) At last the paper makes a conclusion of previous studyresult. Aiming at designing ESD discharge path, a single finger and dual-channel ESDprotection structure is innovatively designed. Comparison with traditional ggNMOS structuretape-out and test results show that the new protection structure is able to improve ESDrobustness index, while effectively reduce utilization of the chip area. This protectionstructure has passed5000V human body model (HBM) test.
3. Study of full-chip ESD protection technology: Through studying transmission linepulsing testing (TLP) and failure analysis, on the basis that the effect of ESD current path onperformance of full-chip protection is systematically studied under all test conditions, law thatbus stray capacitance and resistance’s influence on full-chip protection design is obtained.And layout plan that can help to improve chip ESD withstand voltage level is proposed byusing research results. Through the latch test, this paper analyzes the reason why ESDprotection structure forms latch at chip’s port, and therefore designs a new layout program toinhibit the formation of the latch. The final research results show that without increasing chiparea and process steps, and in the case not to influence the core circuit’s normal performances,based on the full-chip ESD protection design theory, the HC132chip finally passes the5000VESD withstand test under HBM condition. According to the bus crosstalk theory, the paperputs forward an innovative package program to inhibit ESD bus crosstalk, and extends the ESD protection design method from traditional on-chip design to off-chip design.
本论文采用华润上华0.6μm CSMC6S06DPDM-CT02CMOS工艺与香港应用科学与技术研究院(ASTRI)的相关ESD测试设备作为研究平台,以工艺—器件—电路—版图—全芯片作为研究主线,对次亚微米CMOS工艺条件下防护器件的ESD可靠性问题进行了系统研究。文中对现有ESD防护技术进行了全面的对比归纳,提出了多种全新的电路结构与版图布局方案。本论文的研究成果为次亚微米CMOS工艺条件下ESD防护技术的研究提供了理论依据。
本文的主要研究内容概括如下：
1.工艺与器件级ESD防护技术研究：通过对防护器件在ESD大电流条件下电、热特性的分析,得到了可用于定义仿真边界条件的器件失效量化表征量；利用器件的热平衡机理建立了ESD防护器件的解析模型；通过对ISE-TCAD中物理模型的对比研究,获得了可用于0.6μm CSMC6S06DPDM-CT02CMOS工艺条件下的ESD事件仿真优化物理模型；最后利用仿真与流片测试相结合的方法,对次亚微米工艺条件下源漏注入工艺、阱工艺、外延层与衬底工艺、栅氧工艺、Silicide工艺引起的ESD防护器件失效机理进行系统研究,并根据研究结论提出了改善各工艺条件下ESD防护器件性能的方案。
2.电路与版图级ESD防护技术研究：1)电阻部分：以扩散电阻作为研究对象,对其在ESD大电流条件下的电流饱和现象进行了深入研究,由于该现象限制了ESD电流的快速泄放,使得扩散电阻无法作为独立的ESD防护结构使用,流片测试得到的结果验证了研究理论的正确性；2)二极管部分：针对ESD大电流条件下的二极管正、反向特性进行了研究,获得了二极管阳极有效宽度与ESD防护性能之间的关系,并利用仿真与流片测试结果,设计出了一种能够最大化阳极宽度的环形叉指平行布线二极管防护结构；3)MOS部分：从ESD大电流条件下的栅极接地NMOS(gate grounded NMOS, ggNMOS) snapback特性入手,对ggNMOS结构重要的电学指标进行了研究,通过仿真与流片测试,获得了ggNMOS版图参数、结构参数与ESD鲁棒性之间的关系,并针对多指条结构的不均匀导通问题,利用MOS结构的寄生电容特性,设计出了一种能够抑制“触发死区”现象的改进型栅耦合栅接地NMOS(gate coupled gate grounded NMOS, gc-ggNMOS)防护结构；4)最后总结前述的研究结论,以多ESD泄放通路作为设计目标,创新性地设计出了一种单指双通路ESD防护结构,通过与传统ggNMOS结构的流片测试结果对比表明,该全新防护结构能够在全面提高ESD鲁棒性指标的同时,有效降低芯片面积,该防护结构最终通过了5000V的人体放电模式(human body model, HBM)(?)试。3.全芯片级ESD防护技术研究：在系统分析了各种测试条件下ESD电流径对全芯
片防护性能影响的基础上,通过传输线脉冲测试与失效分(transmission line pulsing, TLP)析研究,得到了总线杂散电容、电阻对全芯片防护设计影响的规律,并利用研究结果提出了可以提升芯片ESD耐压等级的版图布局方案；通过闩锁测试,分析了芯片端口处ESD防护结构形成闩锁的原因,并设计出了一种全新的抑制闩锁形成的版图布局方案。最终的研究结果显示,在不增加芯片面积、工艺步骤,且不影响核心电路正常工作的情况下,基于本文全芯片ESD防护设计理论制造出的HC132芯片最终通过了HBM条件下5000V的ESD耐压等级测试。全文最后根据总线串扰理论,提出了一种新的可以抑制ESD总线串扰的封装方案,将ESD防护设计方法从传统的片内设计扩展到了片外设计领域。
Along with the progress of silicon CMOS process technology, device’s feature size hasstepped into the nano-phase for the purpose to improve chip performance and operation speed,and to reduce cost of manufacture per chip as well. However, because of the generation ofnew technology and the improvement of circuit performance, the protection design of ESD(electrostatic discharge, ESD) is becoming more difficult. Therefore, ESD protectiontechnology has experienced a slowing development in recent years. Study on ESD is mainlyabout device-level modeling of ESD protection at present. This approach ignores the fact thatthe protection structure area and parasitic effect have some influence on actual production,which lead to limited guidance of theoretical results for chip production. So that the ESDprotection parts in chips of China’s mainstream foundry’s production are still mainly based ontraditional diodes and MOS structure. What’s more, ESD protection design level of smallerchip design manufacturer’s production is lower, and the production level itself is mostlysub-submicron technology-based.
This paper uses0.6m CSMC6S06DPDM-CT02CMOS technology and the Hong KongApplied Science and Technology Research Institute (ASTRI)’s ESD test equipment as aresearch platform, technology-device-circuit-layout-full chip as the main line, systematicallystudying the protection device’s ESD reliability issues under the conditions of sub-submicron.Existing ESD protection technologies are compared comprehensively in this paper. Moreover,a variety of new concept of circuit structure and scheme of layout are proposed. The paper’sresearch results provide a theoretical basis for the research of ESD protection technologyunder the condition of sub-submicron CMOS process.
The main contents of this paper are summarized as follows:
1. Study of process and device level ESD protection technology: By analyzing electricaland thermal characteristics of protection device under ESD high current, the value ofquantitative characteristics of device failure which can be used to define the simulationboundary condition is found. By using heat balance mechanism in devices, analytical modelof ESD protection device is established. Through comparing physical models in ISE-TCAD,an optimized physical model of ESD event simulation is obtained, which can be used under0.6m CSMC6S06DPDM-CT02CMOS process condition. Finally, this paper studies thefailure mechanism of ESD protection devices which is manufactured by source and drainsimplantation process, well process, epitaxial layer and substrate process, gate oxide processand Silicide process under sub-submicron process condition, and uses the research results topropose the scheme to improve characteristics of ESD protection device under all process conditions.
2. Study of circuit and layout level ESD protection technology:1) As for a resistor, thispaper uses diffusion resistance as object of study, and deeply studies its current saturationunder ESD high current condition. Since the phenomenon limits the ESD current rapiddischarge, diffusion resistance can not work as a separate ESD protection structure. The resultof chip test verifies the correctness of the research theory.2) For diode part, this paper studiesits forward and reverse characteristics under the condition of ESD high current, and finds therelationship between the effective width of the diode anode and ESD protection performance.Moreover, by using simulation and silicon test result, the diode with annular inter-digitalparallel wiring diode protection structure is designed to maximize the width of the anode.3)For MOS part, the paper starts from gate grounded NMOS, ggNMOS snapback characteristics,studies ggNMOS structure’s important electrical indicators, and obtains the relationshipbetween ggNMOS layout parameter, structure parameter and ESD robustness by simulatingand chip fabrication and test. Aiming at non-uniform conduction problem of multi-fingerstructure, by using the parasitic capacitance feature of MOS structure, this paper designs animproved gate coupled gate grounded NMOS gc-ggNMOS protection structure to inhibit thetrigger dead zone phenomenon.4) At last the paper makes a conclusion of previous studyresult. Aiming at designing ESD discharge path, a single finger and dual-channel ESDprotection structure is innovatively designed. Comparison with traditional ggNMOS structuretape-out and test results show that the new protection structure is able to improve ESDrobustness index, while effectively reduce utilization of the chip area. This protectionstructure has passed5000V human body model (HBM) test.
3. Study of full-chip ESD protection technology: Through studying transmission linepulsing testing (TLP) and failure analysis, on the basis that the effect of ESD current path onperformance of full-chip protection is systematically studied under all test conditions, law thatbus stray capacitance and resistance’s influence on full-chip protection design is obtained.And layout plan that can help to improve chip ESD withstand voltage level is proposed byusing research results. Through the latch test, this paper analyzes the reason why ESDprotection structure forms latch at chip’s port, and therefore designs a new layout program toinhibit the formation of the latch. The final research results show that without increasing chiparea and process steps, and in the case not to influence the core circuit’s normal performances,based on the full-chip ESD protection design theory, the HC132chip finally passes the5000VESD withstand test under HBM condition. According to the bus crosstalk theory, the paperputs forward an innovative package program to inhibit ESD bus crosstalk, and extends the ESD protection design method from traditional on-chip design to off-chip design.
引文
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