无源超高频电子标签芯片设计研究
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摘要
射频识别作为一种新兴的自动识别技术,具有体积小、容量大、寿命长、可重复使用等特点,该技术与互联网、通讯等技术相结合,可实现全球范围内物品的跟踪与信息共享。随着该技术的不断发展,其应用领域正日益扩大,已成为当前的热点研究领域,具有广泛的应用前景。
本论文重点研究了无源超高频射频识别标签芯片设计。首先,系统论述了RFID的系统组成及其基本工作原理,并对相关协议标准进行了分析比较。其次,对无源超高频射频识别标签芯片的系统架构进行了分析与设计,对标签芯片设计的关键技术指标进行了分析,并对无源低功耗低成本标签芯片设计的关键技术难点进行了研究。在此基础上,提出了一种用于无源超高频射频识别标签芯片开发的验证开发平台,对标签芯片进行了功能验证。然后,在功能验证的基础上,重点研究了无源超高频射频识别标签芯片射频模拟前端电路和控制逻辑电路的系统架构,并采用低功耗设计技术对其进行了设计,射频模拟前端电路设计包括了整流器、匹配网络、反向散射电路、稳压器、AM解调器、电压参考源、本地振荡器以及上电复位电路等,控制逻辑电路设计包括了时钟同步模块、解码模块、编码模块、CRC校验模块、功率管理单元、控制单元、移位寄存器和存储器等。
采用Chartered 0.35μm 2P4M EEPROM工艺进行流片,最终完成了符合ISO/IEC 18000-6B标准的低功耗高性能无源超高频射频识别标签芯片,并对其进行了性能测试。测试结果表明,该超高频射频识别标签芯片工作在915MHz,其读取距离大于3m,工作电流小于10μA,其中,射频模拟前端电路的设计工作电流小于8μA,控制逻辑电路的设计工作电流小于2μA,标签芯片的测试结果与仿真结果基本一致,该标签芯片很好的满足了设计指标的要求。
Radio frequency identification (RFID), which is an emerging automatic identification technology, has the advantage of small size, high volume, long life and reusable. If the technology combines with the Internet and communications, it will be realized to track global goods and share their information. With the technology developing, its applications are multiplying rapidly. RFID is becoming a hot topic, and has very wide application fields.
The design of a passive ultra high frequency (UHF) RFID transponder chip is researched in this dissertation. First, the RFID system structure and the fundamentals are discussed, and the relevant protocols are compared. Secondly, the system architecture of the passive UHF RFID transponder IC is analyzed and designed. The key design parameters of the UHF RFID transponder are presented and how to design a low-power and low-cost passive transponder IC is studied. Furthermore, a novel verification development platform for passive UHF RFID transponders is presented. Then, on the basis of the functional verification, the system architectures of the radio frequency analog front end (RF AFE) and the control logic circuit for the passive UHF RFID transponder are studied and designed with low-power design techniques. The RF AFE circuit includes rectifier, matching network, backscatter, regulator, AM demodulator, voltage reference, local oscillator and power on reset circuit, and so on. The control logic circuit contains clock synchronization module, decoding module, coding module, cyclic redundancy checksum (CRC) module, power management unit, control unit, shift register and memory.
The low-power high-performance passive UHF RFID transponder IC is fabricated with Chartered 0.35μm two-poly four-metal (2P4M) CMOS process with Schottky diodes and EEPROM, which is compatible with the ISO/IEC 18000-6B standard. The testing results show that the chip’s reading range is more than 3m at the 915 MHz ISM band with a total supply current consumption less than 10μA. Also, the current of the RF AFE circuit is less than 8μA, and the current of the control logic circuit is less than 2μA. The testing results of the chip are consistent with the simulation results. The transponder IC meets the requirements of the design specifications.
本论文重点研究了无源超高频射频识别标签芯片设计。首先,系统论述了RFID的系统组成及其基本工作原理,并对相关协议标准进行了分析比较。其次,对无源超高频射频识别标签芯片的系统架构进行了分析与设计,对标签芯片设计的关键技术指标进行了分析,并对无源低功耗低成本标签芯片设计的关键技术难点进行了研究。在此基础上,提出了一种用于无源超高频射频识别标签芯片开发的验证开发平台,对标签芯片进行了功能验证。然后,在功能验证的基础上,重点研究了无源超高频射频识别标签芯片射频模拟前端电路和控制逻辑电路的系统架构,并采用低功耗设计技术对其进行了设计,射频模拟前端电路设计包括了整流器、匹配网络、反向散射电路、稳压器、AM解调器、电压参考源、本地振荡器以及上电复位电路等,控制逻辑电路设计包括了时钟同步模块、解码模块、编码模块、CRC校验模块、功率管理单元、控制单元、移位寄存器和存储器等。
采用Chartered 0.35μm 2P4M EEPROM工艺进行流片,最终完成了符合ISO/IEC 18000-6B标准的低功耗高性能无源超高频射频识别标签芯片,并对其进行了性能测试。测试结果表明,该超高频射频识别标签芯片工作在915MHz,其读取距离大于3m,工作电流小于10μA,其中,射频模拟前端电路的设计工作电流小于8μA,控制逻辑电路的设计工作电流小于2μA,标签芯片的测试结果与仿真结果基本一致,该标签芯片很好的满足了设计指标的要求。
Radio frequency identification (RFID), which is an emerging automatic identification technology, has the advantage of small size, high volume, long life and reusable. If the technology combines with the Internet and communications, it will be realized to track global goods and share their information. With the technology developing, its applications are multiplying rapidly. RFID is becoming a hot topic, and has very wide application fields.
The design of a passive ultra high frequency (UHF) RFID transponder chip is researched in this dissertation. First, the RFID system structure and the fundamentals are discussed, and the relevant protocols are compared. Secondly, the system architecture of the passive UHF RFID transponder IC is analyzed and designed. The key design parameters of the UHF RFID transponder are presented and how to design a low-power and low-cost passive transponder IC is studied. Furthermore, a novel verification development platform for passive UHF RFID transponders is presented. Then, on the basis of the functional verification, the system architectures of the radio frequency analog front end (RF AFE) and the control logic circuit for the passive UHF RFID transponder are studied and designed with low-power design techniques. The RF AFE circuit includes rectifier, matching network, backscatter, regulator, AM demodulator, voltage reference, local oscillator and power on reset circuit, and so on. The control logic circuit contains clock synchronization module, decoding module, coding module, cyclic redundancy checksum (CRC) module, power management unit, control unit, shift register and memory.
The low-power high-performance passive UHF RFID transponder IC is fabricated with Chartered 0.35μm two-poly four-metal (2P4M) CMOS process with Schottky diodes and EEPROM, which is compatible with the ISO/IEC 18000-6B standard. The testing results show that the chip’s reading range is more than 3m at the 915 MHz ISM band with a total supply current consumption less than 10μA. Also, the current of the RF AFE circuit is less than 8μA, and the current of the control logic circuit is less than 2μA. The testing results of the chip are consistent with the simulation results. The transponder IC meets the requirements of the design specifications.
引文
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