单路与多路CMOS工艺单片光电集成接收机研究与制作
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摘要
随着数据传输量的不断增大,传统的电互连已经不能满足要求。目前在信息传输方面,呈现出光互连与电互连共存的局面,并且由于光互连的优越性,在不久的将来光互连有可能全面取代电互连。在光互连系统中,高速高灵敏度的光接收机设计是一个关键点。传统的光接收机中,光电探测器以及高速模拟电路模块的设计制造大部分采用非CMOS技术,虽然能够获得较为优越的性能,但是工艺不成熟,制作成本高,设计和加工周期长。CMOS超大规模集成电路以及工艺技术的发展,推动了光互连CMOS高速光电探测器和前置放大电路的发展,使得有可能将光接收机中的光电探测器与接收机前置模拟放大电路部分集成到同一块芯片上,这样在光电探测器与前置模拟放大电路之间就可以直接通过CMOS工艺中的金属层来进行连接,从而可以最大限度的消除封装和模块间互连所产生的寄生效应以及外界环境的电磁干扰和噪声,降低了光接收机制作的工艺复杂度,制作成本较低。并且,随着CMOS工艺技术的不断成熟,特征尺寸不断减小,接收机各个模块的速度能够很快的提高,具有广阔的发展前景。
本文围绕高速高灵敏度光接收机中的光电探测器和前置放大电路展开研究,首先讨论了光接收机的基本结构、性能参数,分别分析了光电探测器和前置放大电路的原理、性能、结构,阐述了在光接收机设计过程中各部分所面临的问题和各个性能参数之间必要的折中。分别对光电探测器以及前端放大电路进行了模拟。在此基础上,设计了单路OEIC接收机和12路OEIC接收机并流片测试,具体包括:
1.设计了多种与标准CMOS工艺兼容的硅基光电探测器结构,通过软件进行仿真得出其性能参数,分别采用无锡上华0.6μm CMOS工艺和台积电0.18μm CMOS工艺进行了单独的流片,并进行了测试。
2.设计了光接收机前置放大电路。在TIA电路中,带宽的提高和噪声性能的提高几乎是矛盾的,因此需要在二者之间进行适当的折衷。我们提出了光接收机灵敏度的具体分析方法,并通过仿真确定电路参数与接收机灵敏度的关系;同时结合CMOS集成电路工艺的发展,提出了新型的在TIA中进行前均衡频率补偿的方法,来提高其带宽。
3.针对VSR4-1.0协议的要求,进行了12路并行光接收机的研究。在研制过程中,并行光接收机与单路光接收机的一个重要不同点就是在通道之间存在串扰。我们尝试了抑制串扰通常所采用的隔离方法,同时寻找到一种新型的通过电路设计分析来减小通道间串扰的新方法。
4.在上述模拟仿真和分析的基础上,设计了光接收机各部分和整体的版图,并且进行了流片和测试,测试结果证实了仿真中的想法。
5.进行了12路光接收机模块的制作。
本论文的研究成果在于将光接收机中的光电探测器和前置放大电路集成到同一块衬底上,实现了高速高灵敏度的单路和12路并行光接收机,为单片集成CMOS光接收机的实用化打下了坚实的基础。
With the rapid improvement of data amount, traditional electrical interconnection (EI) becomes non-satisfiable for huge capability. Now in the data transmission aspect, there are both electrical and optical interconnections (OI), and because of the advantages of optical interconnect, we can forecast that in the near future it will totally substitute EI. In OI system, the design of high speed, high sensitivity optical receiver is always a key point. In the past, the photodetector of optical receiver and the high speed analog circuit module were all fabricated by non-CMOS technologies, for their excellent performance with the limitation of expensive manufacturing costs and much longer design and fabrication cycle. The development of CMOS technology has promoted the photodetector and high speed front-end circuit design for OI, made it possible to integrate these two parts into one single chip, and connect them by the metal layer in CMOS process. Through this way, the parasitic effects of packaging and module connection were eliminated, the EMI and noise from outside were restrained, and also the complexity of fabrication was reduced. Furthermore, with the progress in CMOS technology, the feature size has kept shrinking, made the development of speed and sensitivity of photo receiver more rapid.
This thesis focuses on the research on photodetector and TIA circuit in optical receiver. At first, the basic system structure and parameters of the receiver have been described; the principle, topology and characteristics of PD and TIA have been analyzed; the challenges and trade-off in receiver design have been discussed.
In this foundation, the single channel and 12 channels parallel optical receiver have been simulated, taped out, and tested respectively, and the optical receiver module has been fabricated. In more detail, it includes:
1. Several kinds of PD structures compatible with standard CMOS process have been designed and simulated, Selected structures have been taped out with CSMC( a foundary in WuXi, China) 0.6μm CMOS process and TSMC(a foundary in Taiwan, China) 0.18μm CMOS process.
2. The TIA circuit of optical receiver has been designed. In the circuit design, we should trade-off between bandwidth and noise. The method of sensitivity analysis has been described, and the relation between circuit parameters and receiver’s sensitivity has been found out through simulation. At the same time, new topologies of TIA circuit which use pre-equalizer to extend the bandwidth have been presented.
3. According to the requirement of VSR4-1.0, the research of 12-channel parallel optical receiver has been described. In this process, the main deference to single channel is that there are inter-channel crosstalks among channels. The traditional crosstalk restrainment method of isolation has been attempted. More over, a novel way to cancel it by study crosstalk issues from circuit design perspective has been given.
4. After the simulation and analysis, the overall layout of the photoreceiver has been designed, and has been taped out and tested. The results confirmed the ideas in simulation.
5. The 12-channel parallel optical receiver module has been fabricated.
The achievements of this thesis are that integrated the PD and TIA circuit into one single chip, implemented high speed, high sensitivity single channel and 12-channel parallel photoreceiver. It will provide valuable guides to the realization of high speed optical interconnection.
本文围绕高速高灵敏度光接收机中的光电探测器和前置放大电路展开研究,首先讨论了光接收机的基本结构、性能参数,分别分析了光电探测器和前置放大电路的原理、性能、结构,阐述了在光接收机设计过程中各部分所面临的问题和各个性能参数之间必要的折中。分别对光电探测器以及前端放大电路进行了模拟。在此基础上,设计了单路OEIC接收机和12路OEIC接收机并流片测试,具体包括:
1.设计了多种与标准CMOS工艺兼容的硅基光电探测器结构,通过软件进行仿真得出其性能参数,分别采用无锡上华0.6μm CMOS工艺和台积电0.18μm CMOS工艺进行了单独的流片,并进行了测试。
2.设计了光接收机前置放大电路。在TIA电路中,带宽的提高和噪声性能的提高几乎是矛盾的,因此需要在二者之间进行适当的折衷。我们提出了光接收机灵敏度的具体分析方法,并通过仿真确定电路参数与接收机灵敏度的关系;同时结合CMOS集成电路工艺的发展,提出了新型的在TIA中进行前均衡频率补偿的方法,来提高其带宽。
3.针对VSR4-1.0协议的要求,进行了12路并行光接收机的研究。在研制过程中,并行光接收机与单路光接收机的一个重要不同点就是在通道之间存在串扰。我们尝试了抑制串扰通常所采用的隔离方法,同时寻找到一种新型的通过电路设计分析来减小通道间串扰的新方法。
4.在上述模拟仿真和分析的基础上,设计了光接收机各部分和整体的版图,并且进行了流片和测试,测试结果证实了仿真中的想法。
5.进行了12路光接收机模块的制作。
本论文的研究成果在于将光接收机中的光电探测器和前置放大电路集成到同一块衬底上,实现了高速高灵敏度的单路和12路并行光接收机,为单片集成CMOS光接收机的实用化打下了坚实的基础。
With the rapid improvement of data amount, traditional electrical interconnection (EI) becomes non-satisfiable for huge capability. Now in the data transmission aspect, there are both electrical and optical interconnections (OI), and because of the advantages of optical interconnect, we can forecast that in the near future it will totally substitute EI. In OI system, the design of high speed, high sensitivity optical receiver is always a key point. In the past, the photodetector of optical receiver and the high speed analog circuit module were all fabricated by non-CMOS technologies, for their excellent performance with the limitation of expensive manufacturing costs and much longer design and fabrication cycle. The development of CMOS technology has promoted the photodetector and high speed front-end circuit design for OI, made it possible to integrate these two parts into one single chip, and connect them by the metal layer in CMOS process. Through this way, the parasitic effects of packaging and module connection were eliminated, the EMI and noise from outside were restrained, and also the complexity of fabrication was reduced. Furthermore, with the progress in CMOS technology, the feature size has kept shrinking, made the development of speed and sensitivity of photo receiver more rapid.
This thesis focuses on the research on photodetector and TIA circuit in optical receiver. At first, the basic system structure and parameters of the receiver have been described; the principle, topology and characteristics of PD and TIA have been analyzed; the challenges and trade-off in receiver design have been discussed.
In this foundation, the single channel and 12 channels parallel optical receiver have been simulated, taped out, and tested respectively, and the optical receiver module has been fabricated. In more detail, it includes:
1. Several kinds of PD structures compatible with standard CMOS process have been designed and simulated, Selected structures have been taped out with CSMC( a foundary in WuXi, China) 0.6μm CMOS process and TSMC(a foundary in Taiwan, China) 0.18μm CMOS process.
2. The TIA circuit of optical receiver has been designed. In the circuit design, we should trade-off between bandwidth and noise. The method of sensitivity analysis has been described, and the relation between circuit parameters and receiver’s sensitivity has been found out through simulation. At the same time, new topologies of TIA circuit which use pre-equalizer to extend the bandwidth have been presented.
3. According to the requirement of VSR4-1.0, the research of 12-channel parallel optical receiver has been described. In this process, the main deference to single channel is that there are inter-channel crosstalks among channels. The traditional crosstalk restrainment method of isolation has been attempted. More over, a novel way to cancel it by study crosstalk issues from circuit design perspective has been given.
4. After the simulation and analysis, the overall layout of the photoreceiver has been designed, and has been taped out and tested. The results confirmed the ideas in simulation.
5. The 12-channel parallel optical receiver module has been fabricated.
The achievements of this thesis are that integrated the PD and TIA circuit into one single chip, implemented high speed, high sensitivity single channel and 12-channel parallel photoreceiver. It will provide valuable guides to the realization of high speed optical interconnection.
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