数字复接器的FPGA设计与实现
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摘要
本课题主要是用FPGA实现一个数字复接器。其主要功能是在复接端将四个支路的2.048Mbps数据通过正码速调整技术，将其合路成一路8.448Mbps的高速数据流，在分接端又将此高速数据流恢复成原来的四路2.048Mbps的数据。此支路低速数据流与高速数据流既可以是没有编码的一般的非归零码流，也可以是编成了适合于在线路上传输的HDB3线路码。本课题中的时钟提取部分和平滑时钟部分都是用的锁相环来实现的。本文首先分析了线路码的一般问题；其次分析了正码速调整的基本原理及所涉及的一般问题，并说明了用FPGA进行电路设计的一般方法；最后分析了本系统所产生的抖动，如抖动的产生，分类以及如何减小抖动等，并对本课题所产生的两类抖动即正码速调整引入的侯时抖动和平滑锁相环引入的抖动进行了分析，并用Matlab仿真工具对锁相环的抖动与其环路带宽之间的关系进行了仿真与计算。
本人的工作主要包括：
1．利用FPGA完成了复接、分接系统的设计和调试。
2．利用FPGA完成了HDB3线路码的设计与调试。
3．利用锁相环完成了码速恢复。
4．对本复接分接系统所产生的抖动进行了理论分析和仿真。
5．对FPGA进行了误码率测试，误码性能优于10~(-9)。
The subject is mainly accomplish a digital multiplexer by FPGA. The function can be accomplished that multiplexes four branches of 2.048Mb/s into one data flow of 8.448Mb/s and then demultiplexes the data flow into four branches, positive justification used during the course of multiplex. The code of the four branches can be the NRZ or HDB3 who is appropriate to be transmitted for a long distance. The clock recovery circuit and clock smooth circuit are accomplished with phase-locked loop (PLL) in this subject. In the article, at first, common problems of line coding are analysed; the second, the elementary theory of positive justification is analysed, and the general method about how to design the digital circuit with FPGA is narrated; At last, the author had analysed the jitter in this subject, such as the jitter generation classification and how to minimize jitter, analysed the waiting jitter introduced by positive justification and phase jitter introduced by the phase-locked loop circuit, simulated and calculated the relationship between the jitter of phase-locked loop and its bandwidth with the Matlab.
The following tasks are performed by the author:
1. The design and debug of the multiplex system and demultiplex system are accomplished by FPGA.
2. The design and debug of line coding HDB3 are accomplished by FPGA.
3. The gappy clock is recovered by the PLL.
4. Jitter generated in the multiplexer and PLL are analysed and simulated.
5. The error bit rate of the multiplexes is tested with the error and jitter test set, and the error bit rate is up to 10"9.
本人的工作主要包括：
1．利用FPGA完成了复接、分接系统的设计和调试。
2．利用FPGA完成了HDB3线路码的设计与调试。
3．利用锁相环完成了码速恢复。
4．对本复接分接系统所产生的抖动进行了理论分析和仿真。
5．对FPGA进行了误码率测试，误码性能优于10~(-9)。
The subject is mainly accomplish a digital multiplexer by FPGA. The function can be accomplished that multiplexes four branches of 2.048Mb/s into one data flow of 8.448Mb/s and then demultiplexes the data flow into four branches, positive justification used during the course of multiplex. The code of the four branches can be the NRZ or HDB3 who is appropriate to be transmitted for a long distance. The clock recovery circuit and clock smooth circuit are accomplished with phase-locked loop (PLL) in this subject. In the article, at first, common problems of line coding are analysed; the second, the elementary theory of positive justification is analysed, and the general method about how to design the digital circuit with FPGA is narrated; At last, the author had analysed the jitter in this subject, such as the jitter generation classification and how to minimize jitter, analysed the waiting jitter introduced by positive justification and phase jitter introduced by the phase-locked loop circuit, simulated and calculated the relationship between the jitter of phase-locked loop and its bandwidth with the Matlab.
The following tasks are performed by the author:
1. The design and debug of the multiplex system and demultiplex system are accomplished by FPGA.
2. The design and debug of line coding HDB3 are accomplished by FPGA.
3. The gappy clock is recovered by the PLL.
4. Jitter generated in the multiplexer and PLL are analysed and simulated.
5. The error bit rate of the multiplexes is tested with the error and jitter test set, and the error bit rate is up to 10"9.
引文
(1) 王瀚晟，曾烈光．全数字化PDH复接系统的设计．电信科学．1998，4，
(2) 牛立新，杨钧．用FPGA实现PDH到SDH的高阶映射，光通信研究．1997，2
(3) Brian Faith，Joaquin Avlles．利用高速、大容量FPGA的片上RAM实现155MbpsATM．电子产品世界。1999．9
(4) Xilinx公司，用Spartan TM-Ⅱ实现Reed-Solomon编码／译码方案．电子产品世界：设计新苑．2000．6
(5) 王永和，卜长．采用FPGA实现Ⅱ／4 DQPSK调制器．北方交通大学学报．Vol 24 No 5 Oct 2000．
(6) 王建军．用FPGA技术实现数字通信中的扰码与解扰．电子技术应用．1998，5
(7) 王维涛，林岗，周汀．一个低码率级连码系统的设计与FPGA实现．微电子学．Vol 31．No 3．Jun 2001
(8) 张赞，杨征，龚建荣，FPGA在软件无线电中的应用．电子工程师：通信技术与设备．Vol 27 No 1 2001
(9) 黎文，方伟，朱维乐．用于DVD的MPEG2实时解复用器的FPGA设计和实现．电子科技大学学报．Vol 29．No 3．Apr 2000
(10) 李维英，陈育斌，李建东．FPGA在多进制正交扩频通信系统中的应用．电子技术应用．2000，4
(11) 宋文妙，范寒柏，鄂秀焕．用FPGA实现交织和解交织技术，电力系统通信，2001，3
(12) 丁北生．FPGA技术在数据通信中的应用．实用测试技术．No 3．May 1998
(13) Patrick R. Trischitta,Evel. Varma.Jitter in Digital Transmission Systems.1989. AT&T Bell Laboratories.
(14) Kiyoshi Ishii, Keiji Kishine, Haruhiko Ichino. A Jitter Suppression Technique for a 2.48832Gb/s Clock and Data Recovery Circuit.IEEE International Symposium on Circuits and systems.May 28-31.2000.Genewa.Switzerland
(15) Payam Heydari, Massoud Pedram. Analysis of Jitter due to Power-Supply Noise in Phase_Locked Loop.IEEE 2000 Custom Integrated Circuit Conference.
(16) 阎忠平，叶秉．PDH／SDH的抖动和性能漂移及有关测试问题．现代电力．Vol．17，No．4，Nov．2000．
(17) Patrick Larsson. Measurements and Analysis of PLL Jitter Caused by Digital Switching Noise. IEEEJounal of Solid-State Circuits. Vol 36.No 7. July 2001.
(18) 万心平，张厥盛．集成锁相环路—原理、特性、应用．人民邮电出版社．1995，3
(19) 孙玉．数字复接技术
(20) 肖定中，肖萍萍．数字通信终端及复接设备，北京邮电学院出版社．1991
(21) 王建利，冯重熙，曾烈光．关于侯时抖动最大值的计算．通信学报．Vol．17No，2 March 1996．
(22) Yoshitaka,Takasaki.Digital Transmission Design and Jitter Analysis. Artech House.1991.
(23) Dean Banerjee.PLL Performance, Simulation and Design.National Semiconductor.2001
(24) 李忠文．2048KHz锁相环路设计．现代有线传输．1995年第2期。
(25) 谭扬林．数字通信原理．电子工业出版社．2001-12
(26) 曹志刚，钱亚生，现代通信原理
(27) 刘颖，王春悦，赵蓉．数字通信原理与技术．北京邮电出版社．1999-10．
(28) 宋万杰，罗丰，吴顺君．CPLD技术及其应用．西安电子科技大学出版社．1999-9．
(29) 施阳．Matlab语言精要及动态仿真工具Simulink．西北工业大学出版社，1997-6．
(30) 程卫国，冯峰，姚东等．Matlab5．3应用指南．人民邮电出版社，1999-11．
(2) 牛立新，杨钧．用FPGA实现PDH到SDH的高阶映射，光通信研究．1997，2
(3) Brian Faith，Joaquin Avlles．利用高速、大容量FPGA的片上RAM实现155MbpsATM．电子产品世界。1999．9
(4) Xilinx公司，用Spartan TM-Ⅱ实现Reed-Solomon编码／译码方案．电子产品世界：设计新苑．2000．6
(5) 王永和，卜长．采用FPGA实现Ⅱ／4 DQPSK调制器．北方交通大学学报．Vol 24 No 5 Oct 2000．
(6) 王建军．用FPGA技术实现数字通信中的扰码与解扰．电子技术应用．1998，5
(7) 王维涛，林岗，周汀．一个低码率级连码系统的设计与FPGA实现．微电子学．Vol 31．No 3．Jun 2001
(8) 张赞，杨征，龚建荣，FPGA在软件无线电中的应用．电子工程师：通信技术与设备．Vol 27 No 1 2001
(9) 黎文，方伟，朱维乐．用于DVD的MPEG2实时解复用器的FPGA设计和实现．电子科技大学学报．Vol 29．No 3．Apr 2000
(10) 李维英，陈育斌，李建东．FPGA在多进制正交扩频通信系统中的应用．电子技术应用．2000，4
(11) 宋文妙，范寒柏，鄂秀焕．用FPGA实现交织和解交织技术，电力系统通信，2001，3
(12) 丁北生．FPGA技术在数据通信中的应用．实用测试技术．No 3．May 1998
(13) Patrick R. Trischitta,Evel. Varma.Jitter in Digital Transmission Systems.1989. AT&T Bell Laboratories.
(14) Kiyoshi Ishii, Keiji Kishine, Haruhiko Ichino. A Jitter Suppression Technique for a 2.48832Gb/s Clock and Data Recovery Circuit.IEEE International Symposium on Circuits and systems.May 28-31.2000.Genewa.Switzerland
(15) Payam Heydari, Massoud Pedram. Analysis of Jitter due to Power-Supply Noise in Phase_Locked Loop.IEEE 2000 Custom Integrated Circuit Conference.
(16) 阎忠平，叶秉．PDH／SDH的抖动和性能漂移及有关测试问题．现代电力．Vol．17，No．4，Nov．2000．
(17) Patrick Larsson. Measurements and Analysis of PLL Jitter Caused by Digital Switching Noise. IEEEJounal of Solid-State Circuits. Vol 36.No 7. July 2001.
(18) 万心平，张厥盛．集成锁相环路—原理、特性、应用．人民邮电出版社．1995，3
(19) 孙玉．数字复接技术
(20) 肖定中，肖萍萍．数字通信终端及复接设备，北京邮电学院出版社．1991
(21) 王建利，冯重熙，曾烈光．关于侯时抖动最大值的计算．通信学报．Vol．17No，2 March 1996．
(22) Yoshitaka,Takasaki.Digital Transmission Design and Jitter Analysis. Artech House.1991.
(23) Dean Banerjee.PLL Performance, Simulation and Design.National Semiconductor.2001
(24) 李忠文．2048KHz锁相环路设计．现代有线传输．1995年第2期。
(25) 谭扬林．数字通信原理．电子工业出版社．2001-12
(26) 曹志刚，钱亚生，现代通信原理
(27) 刘颖，王春悦，赵蓉．数字通信原理与技术．北京邮电出版社．1999-10．
(28) 宋万杰，罗丰，吴顺君．CPLD技术及其应用．西安电子科技大学出版社．1999-9．
(29) 施阳．Matlab语言精要及动态仿真工具Simulink．西北工业大学出版社，1997-6．
(30) 程卫国，冯峰，姚东等．Matlab5．3应用指南．人民邮电出版社，1999-11．