SRAM灵敏放大器模块的HSPICE仿真与设计改进
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摘要
自本世纪５０年代晶体管诞生以来，微电子技术发展异常迅
速，目前已进入甚大规模集成电路和系统集成时代。微电子技
术已经成为整个信息技术和产业的基础，也是一个国家综合国
力的重要标志。在微电子大家族中，半导体存储器是一类重要
的微电子产品。在随机存储器中，除了动态存储器（ＤＲＡＭ）外，
静态存储器（ＳＲＡＭ）由于其自身的低功耗和高速的优势而成为半
导体存储器中不可或缺的重要产品。随着工艺水平的不断提，
器件特征尺寸不断减小，ＳＲＡＭ在不断增大容量的同时其性能也
在不断改善。提高和改善静态存储器的性能依然是集成电路设
计领域的重要课题。
本论文从降低静态存储器功耗的角度出发，重点研究了静
态存储器的关键模
块— — 灵敏放大器的工作机理和结构，设计了一种改进型的锁
存型灵敏放大器Ｈｓｐｉｃｅ的仿真表明，该放大器的功耗大大低于
传统的静态存储器的灵敏放大器模块的功耗。
本论文共分为四章。 第一章对半导体存储器的分类及国
内、外的发展状况做一简单概述。第二章介绍了电路仿真工
具— Ｈｓｐｉｃｅ，它是本论文所使用的主要工具。第三章深入研究
分析了静态随机存取存储器（ＳＲＡＭ）的结构和工作原理它是完成
本课题主要工作的基础。第四章是论文的核心，重点研究了构
成ＳＲＡＭ的重要模块— — 灵敏放大器。首先详细分析了三种ＳＲＡＭ
灵敏放大器模块：运放型、交叉耦合型，锁存器型灵敏放大器
的结构及工作原理，然后对其进行Ｈｓｐｉｃｅ仿真，目的是比较它
们性能的优缺点。在此基础上，针对ＳＲＡＭ对灵敏放大器的功耗
和速度的要求，结合上述仿真结果，完成了一种改进型的灵敏
放大器设计。对该改进型的灵敏放大器进行了Ｈｓｐｉｃｅ仿真分，
仿真结果表明所设计的改进型灵敏放大器在速度几乎不变的前
提下，功耗指标大大降低。
论文最后部分为结论，同时提出了工作的进一步设想和展望。
Microelectronic technology has advanced rapidly since the first
transistor appeared in 1950s,and now we are in the era of VLSI and system
integraton .Microelectronic technology has been the cornerstone of whole
information industry . In the large family of semiconductor products,
semiconductor memories attract much attention because of its
broadapplications . Static random access memory(SRAM)has become an
indispensable member of semiconductor memory family due to its low power
consumption and high-speederformance.Following enhanced process technology,as
thefeaturesizeof device becomes smaller,the storage ability of SRAM increases continuesly,and
at the same time , its perafrmance performance hasbeen improved
dramatically.It is still an important researching topic in IC design field
to raise and to improve SRAM performance.
For the purpose to reduce the SRAM power dissipation,and based on the study
of the working mechanisms and the structure of sensitive ampifier used as
the keymodule of SRAM,this thesis proposed and implemented an improved
Latch-stylesensitive amplifier,Hspice simulation indicates that its power
dissipation is muchlower than that ofthe triditional sensitive amplifier used
in SRAM.
This thesis consists of four chapters.The first one summarises the
classification and the current developing state of SRAMs at home and
abroad.Chapter two gives a short introduction EDA tool---Hspice,a main
simulation tools used in this work.The next chapter is the keystone to
accomplish the prpose mentioned above,in wchich a deep understanding and a
tedailed analysis of SRAMs’basic structures and theirdistinguishments are
performed.After finishing these necessary preparations,three kinds of sense
amplifiers,used as SRAM’S key modules,are analyzed in chapter four, mainly
focused on their tructures and operational mechanisms,and then simulated by
Hspice, in order to compare their advantages and disadvantages.Then,a
novelstructure of sensetive latch-style-improved amplifier,in the view point of
power dissipation, is proposed,and Hspice-simulation results of the design are also
provided in details . Hspice-simulation results indicate that the
performance of thesensetive latch-style-improved amplifier has been
improved , its power dissipation ismuch lower than that of the
traditional sensitive ampifiers used in SRAM , with an almost
unchanged raising time.
The last part of this thesis is a conclusion,companing with some
looking forwardand suggestion to continue this work.
速，目前已进入甚大规模集成电路和系统集成时代。微电子技
术已经成为整个信息技术和产业的基础，也是一个国家综合国
力的重要标志。在微电子大家族中，半导体存储器是一类重要
的微电子产品。在随机存储器中，除了动态存储器（ＤＲＡＭ）外，
静态存储器（ＳＲＡＭ）由于其自身的低功耗和高速的优势而成为半
导体存储器中不可或缺的重要产品。随着工艺水平的不断提，
器件特征尺寸不断减小，ＳＲＡＭ在不断增大容量的同时其性能也
在不断改善。提高和改善静态存储器的性能依然是集成电路设
计领域的重要课题。
本论文从降低静态存储器功耗的角度出发，重点研究了静
态存储器的关键模
块— — 灵敏放大器的工作机理和结构，设计了一种改进型的锁
存型灵敏放大器Ｈｓｐｉｃｅ的仿真表明，该放大器的功耗大大低于
传统的静态存储器的灵敏放大器模块的功耗。
本论文共分为四章。 第一章对半导体存储器的分类及国
内、外的发展状况做一简单概述。第二章介绍了电路仿真工
具— Ｈｓｐｉｃｅ，它是本论文所使用的主要工具。第三章深入研究
分析了静态随机存取存储器（ＳＲＡＭ）的结构和工作原理它是完成
本课题主要工作的基础。第四章是论文的核心，重点研究了构
成ＳＲＡＭ的重要模块— — 灵敏放大器。首先详细分析了三种ＳＲＡＭ
灵敏放大器模块：运放型、交叉耦合型，锁存器型灵敏放大器
的结构及工作原理，然后对其进行Ｈｓｐｉｃｅ仿真，目的是比较它
们性能的优缺点。在此基础上，针对ＳＲＡＭ对灵敏放大器的功耗
和速度的要求，结合上述仿真结果，完成了一种改进型的灵敏
放大器设计。对该改进型的灵敏放大器进行了Ｈｓｐｉｃｅ仿真分，
仿真结果表明所设计的改进型灵敏放大器在速度几乎不变的前
提下，功耗指标大大降低。
论文最后部分为结论，同时提出了工作的进一步设想和展望。
Microelectronic technology has advanced rapidly since the first
transistor appeared in 1950s,and now we are in the era of VLSI and system
integraton .Microelectronic technology has been the cornerstone of whole
information industry . In the large family of semiconductor products,
semiconductor memories attract much attention because of its
broadapplications . Static random access memory(SRAM)has become an
indispensable member of semiconductor memory family due to its low power
consumption and high-speederformance.Following enhanced process technology,as
thefeaturesizeof device becomes smaller,the storage ability of SRAM increases continuesly,and
at the same time , its perafrmance performance hasbeen improved
dramatically.It is still an important researching topic in IC design field
to raise and to improve SRAM performance.
For the purpose to reduce the SRAM power dissipation,and based on the study
of the working mechanisms and the structure of sensitive ampifier used as
the keymodule of SRAM,this thesis proposed and implemented an improved
Latch-stylesensitive amplifier,Hspice simulation indicates that its power
dissipation is muchlower than that ofthe triditional sensitive amplifier used
in SRAM.
This thesis consists of four chapters.The first one summarises the
classification and the current developing state of SRAMs at home and
abroad.Chapter two gives a short introduction EDA tool---Hspice,a main
simulation tools used in this work.The next chapter is the keystone to
accomplish the prpose mentioned above,in wchich a deep understanding and a
tedailed analysis of SRAMs’basic structures and theirdistinguishments are
performed.After finishing these necessary preparations,three kinds of sense
amplifiers,used as SRAM’S key modules,are analyzed in chapter four, mainly
focused on their tructures and operational mechanisms,and then simulated by
Hspice, in order to compare their advantages and disadvantages.Then,a
novelstructure of sensetive latch-style-improved amplifier,in the view point of
power dissipation, is proposed,and Hspice-simulation results of the design are also
provided in details . Hspice-simulation results indicate that the
performance of thesensetive latch-style-improved amplifier has been
improved , its power dissipation ismuch lower than that of the
traditional sensitive ampifiers used in SRAM , with an almost
unchanged raising time.
The last part of this thesis is a conclusion,companing with some
looking forwardand suggestion to continue this work.
引文
1 Jan M.Rabaey. Digital Integrated Circuit，Prentice Hall，1996，pp:553-621.
2 Richard C.Jaeger. Microelectronic Circuit Design，The McGraw-Hill Companies，
Inc.，1997，pp:361-364.
3 王小海，集成电子技术教程，浙江大学出版社，1990:180-185.
4 Roubik Gregorian ， Introduction To CMOS Op-Amp And Comparators ，
Wiley-Interscience，1999:95-100.
5 杨素行，模拟电子技术基础简明教程（第二版），高等教育出版社，1996，
pp:120-125
6 Phillip E.Allen andDonglas R.Holberg，CMOS ANALOG CIRCUIT DESIGN，
Saunders College Publishing Translation，1987，pp:353-438.
7 Behzad Razavi，Design Of Analog CMOS Integrated Circuits，McGraw-Hill，
2001, pp:291-344.
8 Ashok k. Sharma，Semiconductor Memories，IEEE Press，1997，pp:10-17.
9 Santin et al.U.S.Pat.No.5，056，063，Oct.1991.
10 张建人，MOS 集成电路分析与设计基础，电子工业出版社，1990，pp:313-330.
11 盛水源，世界电子元器件，总第 74 期，2001, pp:63-66.
12 S.Asai,Proceeding of the IEEE,Vol.74,no.12,1986, pp:1623-1635.
13 P.Gray and R.Meyer,Analysis and Design of Analog Integrated Circuits,3rd ed，
John Wiley and Sons, 1993, pp:156-158.
14 T.Jinbo et al.,IEEE Journal Of Solid State Circuits,vol.27,no.11,1992,
pp:1547-1554.
15 K.Iton,IEEE Journal of solid State Circuits,vol.25,no.3,1990, pp:778-798.
16 H.Kalter et al.,IEEE Journal of Solid State Circuits,vol.25,no.5,1990,
pp:1118-1128.
17 T.Hirose et al.,IEEE Journal of Solid State Circuits,vol.25,no.5,1990,
pp:1068-1074.
18 D.Hodges and H.Jackson, Analysis and Design of Digital Integrated Circuits,
- 58 -
参考文献
McGraw-Hill, 1988, pp:168-178.
19 S.Flannagan, Proceedings IEDM 1988,1988, pp:40-43.
20 T.Dillinger, VLSI Engineering，Prentice Hall,1988, pp:200-210.
21 D.Frohman, Solid State Electronics, vol.17, no.5,1974, pp:517-529.
22 J.Chang, IEEE Trans. Electron Devices, ED-24,1977, pp:511-518.
23 J.P.Colinge, Silicon-On-Insulator Technology:Materials to VLSI ， Kluwer
Academic Publishers,1991, pp:150-156.
24 王守武，夏永伟，孔令坤，张冬萱，半导体学报，第 6 卷，第 3 期，1985，
pp:225-235.
25 夏永伟，王守武，半导体学报，第 11 卷，第 12 期，1990，pp:963-965.
26 F.T.Bray,T.Brown and L.Rockett, IEEE Transactions on Nuclear Science, vol.45,
no.6,1998, pp:51-56.
27 S.T.Liu,W.C.Jenkins and H.L.Hughes, IEEE Transactions on Nuclear Science,
vol.45, no.6,1998, pp:57-64.
28 Takaysu and Mitsuo Isobe, IEEE J.Solid-State Circuits, vol.SC-19, no.5,1984,
pp:578-584.
29 J.Barnes and A.L.DE Jesus, IEEE J.Solid-State Circuits, vol.SC-19, no.4,1984,
pp:455-461.
30 P.E.Gronowski et al., IEEE JSSC, vol.33, no.5,1998, pp:676-686.
31 W.C.Madden and W.J.Bowhill, U.S.Pat. No.4,910,713, 1990.
32 T.Kobayashi et al., IEEE JSSC, vol.28, no.4,1993, pp:523-527.
33 M.Matsui et al., IEEE JSSC, vol.29, no.12,1994, pp:1483-1490.
34 H.Kawaguchi and T.Sakurai, IEEE JSSC, vol.33, no.5,1998, pp:807-811.
35 Y.P.Tsividis and P.R.Gray, IEEE Journal of Solid State Circuits, vol.SC-11,
no.6,1976, pp:748-753.
36 W.C.Black et al., IEEE Journal of solid State Circuits, vol.SC-15, no.6,1980,
pp:929-938.
37 B.K.Ahuja,IEEE Journal of solid State Circuits,vol.SC-18.no.6,1983, pp:629-633.
38 D.B.Ribner and M.A.Copeland, IEEE Journal of solid State Circuits, vol.SC-18.
no.6,1984, pp:919-925.
- 59 -
北京工业大学工学硕士学位论文
39 P.R.Gray and R.G.Meyer, IEEE Journal of Solid State Circuits, vol.SC-17,
no.6,1982, pp:969-982.
40 T.C.Choi, R.T.Kaneshiro,R.W.Brodersen,P.R.Gray,W.B.Jett and M.Wilcox, IEEE
Journal of Solid State Circuits, vol.SC-18, no.6,1983, pp:625-664.
41 W.M.C.Sansen,M.Steyaert and P.J.V.Vandeloo, IEEE Transactions on
Instrumentation and Measurement, vol.IM-34, no.1,1985, pp:59-64.
42 R.G.Eschauzier,L.P.T.Kerklaan and J.H.Huising,IEEE J.of Solid-State Circuits,
vol.27, no.6,1992, pp:1709-1711.
43 B.J.Hosticka, IEEE J.of Solid-State Circuits, vol.14, no.5,1979, pp:1111-1114.
44 K.Bult and G.J.G.H.Geelen, IEEE J.of Solid-State Circuits, vol.25, no.7,1990,
pp:1379-1384.
2 Richard C.Jaeger. Microelectronic Circuit Design，The McGraw-Hill Companies，
Inc.，1997，pp:361-364.
3 王小海，集成电子技术教程，浙江大学出版社，1990:180-185.
4 Roubik Gregorian ， Introduction To CMOS Op-Amp And Comparators ，
Wiley-Interscience，1999:95-100.
5 杨素行，模拟电子技术基础简明教程（第二版），高等教育出版社，1996，
pp:120-125
6 Phillip E.Allen andDonglas R.Holberg，CMOS ANALOG CIRCUIT DESIGN，
Saunders College Publishing Translation，1987，pp:353-438.
7 Behzad Razavi，Design Of Analog CMOS Integrated Circuits，McGraw-Hill，
2001, pp:291-344.
8 Ashok k. Sharma，Semiconductor Memories，IEEE Press，1997，pp:10-17.
9 Santin et al.U.S.Pat.No.5，056，063，Oct.1991.
10 张建人，MOS 集成电路分析与设计基础，电子工业出版社，1990，pp:313-330.
11 盛水源，世界电子元器件，总第 74 期，2001, pp:63-66.
12 S.Asai,Proceeding of the IEEE,Vol.74,no.12,1986, pp:1623-1635.
13 P.Gray and R.Meyer,Analysis and Design of Analog Integrated Circuits,3rd ed，
John Wiley and Sons, 1993, pp:156-158.
14 T.Jinbo et al.,IEEE Journal Of Solid State Circuits,vol.27,no.11,1992,
pp:1547-1554.
15 K.Iton,IEEE Journal of solid State Circuits,vol.25,no.3,1990, pp:778-798.
16 H.Kalter et al.,IEEE Journal of Solid State Circuits,vol.25,no.5,1990,
pp:1118-1128.
17 T.Hirose et al.,IEEE Journal of Solid State Circuits,vol.25,no.5,1990,
pp:1068-1074.
18 D.Hodges and H.Jackson, Analysis and Design of Digital Integrated Circuits,
- 58 -
参考文献
McGraw-Hill, 1988, pp:168-178.
19 S.Flannagan, Proceedings IEDM 1988,1988, pp:40-43.
20 T.Dillinger, VLSI Engineering，Prentice Hall,1988, pp:200-210.
21 D.Frohman, Solid State Electronics, vol.17, no.5,1974, pp:517-529.
22 J.Chang, IEEE Trans. Electron Devices, ED-24,1977, pp:511-518.
23 J.P.Colinge, Silicon-On-Insulator Technology:Materials to VLSI ， Kluwer
Academic Publishers,1991, pp:150-156.
24 王守武，夏永伟，孔令坤，张冬萱，半导体学报，第 6 卷，第 3 期，1985，
pp:225-235.
25 夏永伟，王守武，半导体学报，第 11 卷，第 12 期，1990，pp:963-965.
26 F.T.Bray,T.Brown and L.Rockett, IEEE Transactions on Nuclear Science, vol.45,
no.6,1998, pp:51-56.
27 S.T.Liu,W.C.Jenkins and H.L.Hughes, IEEE Transactions on Nuclear Science,
vol.45, no.6,1998, pp:57-64.
28 Takaysu and Mitsuo Isobe, IEEE J.Solid-State Circuits, vol.SC-19, no.5,1984,
pp:578-584.
29 J.Barnes and A.L.DE Jesus, IEEE J.Solid-State Circuits, vol.SC-19, no.4,1984,
pp:455-461.
30 P.E.Gronowski et al., IEEE JSSC, vol.33, no.5,1998, pp:676-686.
31 W.C.Madden and W.J.Bowhill, U.S.Pat. No.4,910,713, 1990.
32 T.Kobayashi et al., IEEE JSSC, vol.28, no.4,1993, pp:523-527.
33 M.Matsui et al., IEEE JSSC, vol.29, no.12,1994, pp:1483-1490.
34 H.Kawaguchi and T.Sakurai, IEEE JSSC, vol.33, no.5,1998, pp:807-811.
35 Y.P.Tsividis and P.R.Gray, IEEE Journal of Solid State Circuits, vol.SC-11,
no.6,1976, pp:748-753.
36 W.C.Black et al., IEEE Journal of solid State Circuits, vol.SC-15, no.6,1980,
pp:929-938.
37 B.K.Ahuja,IEEE Journal of solid State Circuits,vol.SC-18.no.6,1983, pp:629-633.
38 D.B.Ribner and M.A.Copeland, IEEE Journal of solid State Circuits, vol.SC-18.
no.6,1984, pp:919-925.
- 59 -
北京工业大学工学硕士学位论文
39 P.R.Gray and R.G.Meyer, IEEE Journal of Solid State Circuits, vol.SC-17,
no.6,1982, pp:969-982.
40 T.C.Choi, R.T.Kaneshiro,R.W.Brodersen,P.R.Gray,W.B.Jett and M.Wilcox, IEEE
Journal of Solid State Circuits, vol.SC-18, no.6,1983, pp:625-664.
41 W.M.C.Sansen,M.Steyaert and P.J.V.Vandeloo, IEEE Transactions on
Instrumentation and Measurement, vol.IM-34, no.1,1985, pp:59-64.
42 R.G.Eschauzier,L.P.T.Kerklaan and J.H.Huising,IEEE J.of Solid-State Circuits,
vol.27, no.6,1992, pp:1709-1711.
43 B.J.Hosticka, IEEE J.of Solid-State Circuits, vol.14, no.5,1979, pp:1111-1114.
44 K.Bult and G.J.G.H.Geelen, IEEE J.of Solid-State Circuits, vol.25, no.7,1990,
pp:1379-1384.