Sigma-Delta分数频率合成器研究与设计
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摘要
频率合成器是无线通信中射频前端的主要构件模块之一,性能直接决定射频接收机的频率选择性。本文以3G通信为应用目标,研究了基于Sigma-Delta调制技术的分数频率合成器的相关问题。
论文首先阐明了采用Sigma-Delta调制技术实现分数频率合成器的意义,介绍了常用来刻画合成器性能的规格参数,以及不同表述形式的具有相同意义的规格参数之间的联系和转换方法。
Sigma-Delta调制器内置的非线性使得其理论研究存在困难。在研究一般Sigma-Delta调制器的极限环特征和稳定性基础之上,主要研究了适合分数频率合成器应用的三阶Sigma-Delta调制器的极限环特征和稳定性。合成器环路的非线性会将Sigma-Delta调制器的输出高频噪声折叠到低频,降低合成器输出带内相位噪声,文中所提出了加权熵分析方法,能够简单有效判断Sigma-Delta调制器对环路非线性的灵敏程度。
环路滤波器是单片集成频率合成器的面积瓶颈,在研究双路径滤波器和电容值倍乘技术的基础上,结合二者优点提出了隐式双路径滤波器结构,在减少面积基础上改善了环路滤波器性能。此外,由于采用跨导增强技术,使得滤波器低频输出噪声性能和可适用频率范围大大改善。
通过研究相位切换双模预分频器的结构,提出了对相位切换双模预分频器进行改造直接实现多模分频的方法,采用反向开关策略,消除了分频器的输出毛刺问题,使得多模分频器更为简单、可靠。
压控振荡器是频率合成器中的关键模块,其相位噪声直接影响合成器的输出相位噪声。相/频检测器和电荷泵存在许多非理想因素如死区、电流失配等,影响合成器输出带内噪声,需要对众多改善技术进行比较研究,选择适合本文应用的技术。
为了分析和验证合成器整体性能,需要建立分析模型。文中分别为合成器建立独立的频域和时域模型。频域模型以M.H.Perrott模型为基础,通过扩展使其更具开放性,除了能分析相位噪声还能分析其它非理想特性的影响,同时还能接受其它仿真器的部分仿真结果,用以验证整个合成器性能。时域模型采用事件驱动方式建立,破除了仿真精度和仿真时间之间的矛盾。
为了验证文中研究结论,采用TSMC 0.18μm MM/RF 1P6M Salicide 1.8V/3.3V工艺设计了验证电路。合成器相位噪声为-86dBc@10KHz、-102.5dBc@100KHz和-125.2dBc@1MHz,除了在100KHz处稍微偏大外,其它满足要求。频率切换时间大约为100μS。芯片面积为2000μm×2400μm,功耗大约20mW。
The frequency synthesizer is a key building block of radio frequency front-end for wireless communications and its performance determines the frequency selectivity of radio frequency receivers. The fractional frequency synthesizer, which is based on Sigma-Delta modulation and targeted for 3G communications, is researched in this thesis.
The thesis first illustrates the significance of the application of Sigma-Delta modulation in the implementation of the fractional frequency synthesizer. Then the general specification parameters are introduced and the difference and conversion methods among different definition forms for the same parameter are clarified.
The intrinsic non-linearity of the Sigma-Delta modulator makes its theory research very hard. Based on the research on the limit cycle and stability of general Sigma-Delta modulator, more research is focused on the limit cycle and stability of the third order Sigma-Delta modulator which is eligible for the application of the fractional frequency synthesizer. The non-linearity resulting from the frequency synthesizer loop folds the high frequency noise of the Sigma-Delta modulator into low frequency and degrades the output in-band phase noise of the frequency synthesizer. A simple weighted entropy method is proposed to figure the sensitivity of the Sigma-Delta modulator to non-linearity.
The loop filter is an area bottleneck of the monolithic integrating frequency synthesizer. Based on the research on the dual-path filter and the capacitance multiplication technique, an implicit dual-path filter is proposed in the thesis. The implicit dual-path filter combines the advantage of both dual-path filter and capacitance multiplication technique and improves its performance without sacrificing the area. Furthermore, the performance of low frequency output noise and the applicable frequency range of the filter are improved by employing trans-conductor enhanceing technique.
Based on the research on the phase switching dual-modulus prescaler, a direct multi-modulus frequency divider is brought out by modifying the phase switching dual-modulus prescaler. The output spike of the frequency divider is eliminated by adopting the inverse switching strategy, which makes the multi-modulus frequency divider simpler and more robust.
The voltage controlled oscillator is one of the key building blocks in the frequency synthesizer and its phase noise directly affects the output phase noise of the whole frequency synthesizer. The non-ideality of the phase/frequency detector and the charge pump, such as dead zone and current mismatch, affects the output in-band phase noise of the frequency synthesizer. The most eligible one is selected for the target application by comparing several methods of rejecting non-ideality.
In order to analyze and validate the performance of the frequency synthesizer, it is necessary to make models for the whole frequency synthesizer. An independent frequency domain model and an independent time domain model are made for the Sigma-Delta fractional frequency synthesizer. The frequency domain model, based on the model proposed by M. H. Perrott turns to be more open through extension and is able to analyze phase noise as well as the influence of other non-ideality. Moreover, the frequency domain model can receive parts of results from other simulator to verify the performance of the whole frequency synthesizer. The time domain model is driven by events, which eliminates the conflict between simulation accuracy and simulation time
A Sigma-Delta fractional frequency synthesizer is designed with TSMC 0.18μm MM/RF 1P6M Salicide 1.8V/3.3V process to validate the research conclusion of the thesis. The achievable phase noise is–86dBc@10KHz, -102.5dBc@100KHz and–125.2dBc@1MHz which meets the specification except for a little violation at 100KHz. The frequency switching time is rough 100μS. The chip occupies an area of 2.0×2.4 mm2 with power consumption 20mW from 1.8V power supply.
论文首先阐明了采用Sigma-Delta调制技术实现分数频率合成器的意义,介绍了常用来刻画合成器性能的规格参数,以及不同表述形式的具有相同意义的规格参数之间的联系和转换方法。
Sigma-Delta调制器内置的非线性使得其理论研究存在困难。在研究一般Sigma-Delta调制器的极限环特征和稳定性基础之上,主要研究了适合分数频率合成器应用的三阶Sigma-Delta调制器的极限环特征和稳定性。合成器环路的非线性会将Sigma-Delta调制器的输出高频噪声折叠到低频,降低合成器输出带内相位噪声,文中所提出了加权熵分析方法,能够简单有效判断Sigma-Delta调制器对环路非线性的灵敏程度。
环路滤波器是单片集成频率合成器的面积瓶颈,在研究双路径滤波器和电容值倍乘技术的基础上,结合二者优点提出了隐式双路径滤波器结构,在减少面积基础上改善了环路滤波器性能。此外,由于采用跨导增强技术,使得滤波器低频输出噪声性能和可适用频率范围大大改善。
通过研究相位切换双模预分频器的结构,提出了对相位切换双模预分频器进行改造直接实现多模分频的方法,采用反向开关策略,消除了分频器的输出毛刺问题,使得多模分频器更为简单、可靠。
压控振荡器是频率合成器中的关键模块,其相位噪声直接影响合成器的输出相位噪声。相/频检测器和电荷泵存在许多非理想因素如死区、电流失配等,影响合成器输出带内噪声,需要对众多改善技术进行比较研究,选择适合本文应用的技术。
为了分析和验证合成器整体性能,需要建立分析模型。文中分别为合成器建立独立的频域和时域模型。频域模型以M.H.Perrott模型为基础,通过扩展使其更具开放性,除了能分析相位噪声还能分析其它非理想特性的影响,同时还能接受其它仿真器的部分仿真结果,用以验证整个合成器性能。时域模型采用事件驱动方式建立,破除了仿真精度和仿真时间之间的矛盾。
为了验证文中研究结论,采用TSMC 0.18μm MM/RF 1P6M Salicide 1.8V/3.3V工艺设计了验证电路。合成器相位噪声为-86dBc@10KHz、-102.5dBc@100KHz和-125.2dBc@1MHz,除了在100KHz处稍微偏大外,其它满足要求。频率切换时间大约为100μS。芯片面积为2000μm×2400μm,功耗大约20mW。
The frequency synthesizer is a key building block of radio frequency front-end for wireless communications and its performance determines the frequency selectivity of radio frequency receivers. The fractional frequency synthesizer, which is based on Sigma-Delta modulation and targeted for 3G communications, is researched in this thesis.
The thesis first illustrates the significance of the application of Sigma-Delta modulation in the implementation of the fractional frequency synthesizer. Then the general specification parameters are introduced and the difference and conversion methods among different definition forms for the same parameter are clarified.
The intrinsic non-linearity of the Sigma-Delta modulator makes its theory research very hard. Based on the research on the limit cycle and stability of general Sigma-Delta modulator, more research is focused on the limit cycle and stability of the third order Sigma-Delta modulator which is eligible for the application of the fractional frequency synthesizer. The non-linearity resulting from the frequency synthesizer loop folds the high frequency noise of the Sigma-Delta modulator into low frequency and degrades the output in-band phase noise of the frequency synthesizer. A simple weighted entropy method is proposed to figure the sensitivity of the Sigma-Delta modulator to non-linearity.
The loop filter is an area bottleneck of the monolithic integrating frequency synthesizer. Based on the research on the dual-path filter and the capacitance multiplication technique, an implicit dual-path filter is proposed in the thesis. The implicit dual-path filter combines the advantage of both dual-path filter and capacitance multiplication technique and improves its performance without sacrificing the area. Furthermore, the performance of low frequency output noise and the applicable frequency range of the filter are improved by employing trans-conductor enhanceing technique.
Based on the research on the phase switching dual-modulus prescaler, a direct multi-modulus frequency divider is brought out by modifying the phase switching dual-modulus prescaler. The output spike of the frequency divider is eliminated by adopting the inverse switching strategy, which makes the multi-modulus frequency divider simpler and more robust.
The voltage controlled oscillator is one of the key building blocks in the frequency synthesizer and its phase noise directly affects the output phase noise of the whole frequency synthesizer. The non-ideality of the phase/frequency detector and the charge pump, such as dead zone and current mismatch, affects the output in-band phase noise of the frequency synthesizer. The most eligible one is selected for the target application by comparing several methods of rejecting non-ideality.
In order to analyze and validate the performance of the frequency synthesizer, it is necessary to make models for the whole frequency synthesizer. An independent frequency domain model and an independent time domain model are made for the Sigma-Delta fractional frequency synthesizer. The frequency domain model, based on the model proposed by M. H. Perrott turns to be more open through extension and is able to analyze phase noise as well as the influence of other non-ideality. Moreover, the frequency domain model can receive parts of results from other simulator to verify the performance of the whole frequency synthesizer. The time domain model is driven by events, which eliminates the conflict between simulation accuracy and simulation time
A Sigma-Delta fractional frequency synthesizer is designed with TSMC 0.18μm MM/RF 1P6M Salicide 1.8V/3.3V process to validate the research conclusion of the thesis. The achievable phase noise is–86dBc@10KHz, -102.5dBc@100KHz and–125.2dBc@1MHz which meets the specification except for a little violation at 100KHz. The frequency switching time is rough 100μS. The chip occupies an area of 2.0×2.4 mm2 with power consumption 20mW from 1.8V power supply.
引文
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