高k栅堆栈电荷陷阱型MONOS存储器的研究
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摘要
电荷陷阱型存储器作为传统悬浮栅Flash存储器的后时代应用，目前所面临的技术挑战是在不断缩小的工艺节点要求下，实现在降低工作电压的同时，获得大的存储窗口、快的编程/擦除速度、好的疲劳特性以及10年数据保持力。对于Metal-Oxide-Nitride-Oxide-Silicon (MONOS)型存储器，使用高k材料替代传统的SiO2和Si3N4，对其阻挡层、电荷存储层和隧穿层各功能层从材料、结构及制备工艺等方面进行优化，是改善和提高电荷陷阱型存储器性能的主要途径。本论文即围绕上述内容开展研究工作。在实验方面，对多种高k介质材料作为电荷存储层进行了研究比较,并设计制备了新型双存储层结构、高k/低k双隧穿层结构，对制备工艺进行了优化，以获得存储窗口、编程/擦除速度、数据保持力和疲劳特性之间的较好折衷；在理论方面，建立了MONOS存储器编程状态下的电子保持特性模型。
在电荷存储层高k介质材料以及制备工艺方面，开展了以下研究工作：①通过在La基氧化物中添加过渡金属Hf、Ti、Y，形成La系二元混合金属氧化物作为MONOS存储器的电荷存储层。实验发现，氮化的LaHfO(LaHfON)由于N的引入增加了电荷陷阱密度，提高了陷阱的电荷俘获效率，同时强的Hf-N、La-N键的形成以及好的LaHfON/SiO2界面质量增强了介质稳定性，有利于电荷的保持；La基氧化物中掺Y比掺Ti更有利于增加存储层的电荷陷阱密度，提高电荷俘获效率，并在淀积后的退火处理过程中能更有效地抑制存储层与SiO2界面附近过渡层的形成，从而减少了浅能级陷阱或缺陷的产生，使存储器在获得大的存储窗口和快的电荷注入速度的同时，也具有好的的疲劳特性和电荷保持力；②采用GdO作为电荷存储层，研究溅射过程中不同气体环境(N2或O2)以及淀积后不同热退火处理工艺对介质薄膜质量和存储性能的影响。实验结果表明，N引入GdO介质中导致大量电子陷阱产生，大大增加了存储窗口，且通过5500C/2min的NH3退火处理，能够有效抑制存储层/SiO2界面附近浅能级陷阱的产生，调整存储层中陷阱分布，可获得存储窗口、编程/擦除速度以及疲劳和电荷保持特性之间的较好折衷。
在新型栅堆栈结构方面：①提出了Au/HfAlO/AlN/(HfON/SiO2)/Si多层栅堆栈结构：采用k值相差较大的高k HfON介质层与SiO2结合形成HfON/SiO2双隧穿层结构，提高了电荷注入效率和速度；具有深能级陷阱的AlN作为电荷存储层提供了优良的电荷俘获能力和电荷存储稳定性；高功函数的Au电极以及具有合适k值和势垒高度的HfAlO阻挡层能够有效减少擦除期间来自控制栅的电子注入以及保持期间存储层中电荷的泄漏，缩短擦除时间，提高数据保持力；②从带隙工程出发，提出并制备了由高k介质TiON/HfON组成的双存储层结构，利用淀积后快速热退火过程中Ti、Hf元素的互扩散，形成Ti、Hf含量渐变的Hf1-xTixON混合层，从而形成从隧穿层到阻挡层带隙逐渐增加的锥形能带结构(禁带宽度随Ti含量的增加而单调减小)。Hf1-xTixON混合层具有高的电荷陷阱密度，其锥形能带结构形成的多能级陷阱分布有利于提高陷阱俘获电荷的能力和电荷注入效率，从而获得大的存储窗口和快的编程/擦除速度。另外，存储层锥形能带结构与隧穿层之间较高的势垒高度能有效阻挡陷阱电荷的逸出，从而提高了电荷保持力。
在理论模型研究方面，以陷阱至导带(TB)隧穿作为存储电子的泄漏机制，采用类三角形陷阱能级分布，并考虑陷阱空间分布分别为均匀分布或局域分布两种情况，建立了MONOS型存储器编程状态下的电子保持特性理论模型。通过将模拟仿真结果与实验测量数据进行比较，验证了所建电荷保持特性模型的正确性和准确性。
As next-generation application of the traditional floating-gate flash memory, charge-trapping memory presently faces some severe technique challenges as the technology nodecontinuously scales down, i.e. at low operating voltages, large memory window, fastprogram/erase (P/E) speed, good endurance and10-year data retention must be attained.For metal-oxide-nitride-oxide-silicon (MONOS) memory, the conventional SiO2and Si3N4are substituted by the high-k dielectrics, and hence optimization of the material, structureand fabricating processes of its blocking layer (BL), charge storage layer (CSL) andtunneling layer (TL) will be the main approach of improving performances ofcharge-trapping memory. These are just research work performed in this dissertation.Experimentally, some high-k dielectric materials as CSL are investigated and compared, thenovel dual-CSL and dual-TL structures of high-k/low-k are designed and prepared, andoptimization of the fabrication processes has been carried out to achieve a good trade-offamong the memory window, P/E speed, endurance property and retention characteristics.Theoretically, the electron-retention model of MONOS memory under the programmingstate has been established.
Some investigations have been done on the high-k dielectric materials and fabricatingprocesses of the CSL:①The La-based binary-mixing oxides as the CSL of MONOSmemory are prepared by doping Hf, or Ti, or Y into La oxide and their effects on theperformances of the devices are investigated and compared in detail. It is experimentallyfound that high density of traps with deeper levels and thus high trapping efficiency, strongHf-N and La-N bonds and stable HfLaON/SiO2interface and thus reasonable data retentioncan be achieved by incorporation of N into HfLaO to form HfLaON. Compared to deviceswith LaTiO CSL, the devices with LaYO CSL exhibits larger memory window, higherprogram speed, better retention and endurance properties, suggesting that the Y-doped Laoxide could provide a large amount of bulk traps and thus high charge-trapping efficiency,and effectively suppress formation of the interfacial silicate layer near the CSL/SiO2interface during post-deposition anneal, reducing generation of shallow-level traps or defects;②Using GdO as CSL, the effects of different sputtering ambient (N2or O2) andanneal processing on quality of GdO thin film and performances of the memory areinvestigated. Experimental results indicate that the memory window is greatly increaseddue to generation of a large quantity of electron traps induced by incorporation of N intothe GdO dielectric, and furthermore, a good trade-off among the memory window, P/Espeed, endurance, and retention characteristics can be achieved by NH3annealing at5500Cfor2min, which can effectively suppress creation of shallow-level traps near the CSL/SiO2interface, and thus give suitable spatial distribution of traps with deeper energy level in thebulk of the CSL.
Regarding novel stacked gate structure:①A stacked gate structure of Au/HfAlO/AlN/(HfON/SiO2)/Si is proposed and prepared by in-situ sputtering method, where the ultrathindual-TL of HfON/SiO2is used to increase speed and efficiency of charge injection, the AlNCSL with deep-level traps is employed to provide large memory window, good chargecapturing capability and stability of charge trapping, Au electrode with high work functionand HfAlO BL with suitable k value and barrier height can effectively reduce electroninjection from the control gate into CSL during erasing and leakage of those charges in CSLduring retention, thus shortening erase time and enhancing data retention.②Based onbandgap engineering, a dual CSL composed of TiON/HfON is proposed and prepared, anda tapered bandgap structure with bandgap increasing from the TL to the BL is formed dueto the inter-diffusion between Ti and Hf near the TiON/HfON interface which leads to anintermixing layer of HfxTiyON with varying Hf/Ti ratio in the dual CSL during post-deposition annealing. A large quantity of electron traps exists in the dual CSL due to themixing of HfON and TiON. The tapered bandgap structure can give a multi-level trapdistribution, which is beneficial for enhancing charge capturing capability of traps andcharge injection efficiency, thus obtaining large memory window and high P/E speed. Inaddition, a large barrier height between the TiON and TL can effectively block escaping ofthose trapping charges, enhancing data retention.
Theoretically, an analytical model of electron retention under the programming state isestablished by taking trap-to-band (TB) tunneling as leakage mechanism of the trappedelectrons, assuming a triangle-like energy-level distribution of traps and considering the trap spatial distribution as the uniform or local profiles respectively. The correctness andaccuracy of the model are confirmed by good agreement of the simulated results withexperimental data.
在电荷存储层高k介质材料以及制备工艺方面，开展了以下研究工作：①通过在La基氧化物中添加过渡金属Hf、Ti、Y，形成La系二元混合金属氧化物作为MONOS存储器的电荷存储层。实验发现，氮化的LaHfO(LaHfON)由于N的引入增加了电荷陷阱密度，提高了陷阱的电荷俘获效率，同时强的Hf-N、La-N键的形成以及好的LaHfON/SiO2界面质量增强了介质稳定性，有利于电荷的保持；La基氧化物中掺Y比掺Ti更有利于增加存储层的电荷陷阱密度，提高电荷俘获效率，并在淀积后的退火处理过程中能更有效地抑制存储层与SiO2界面附近过渡层的形成，从而减少了浅能级陷阱或缺陷的产生，使存储器在获得大的存储窗口和快的电荷注入速度的同时，也具有好的的疲劳特性和电荷保持力；②采用GdO作为电荷存储层，研究溅射过程中不同气体环境(N2或O2)以及淀积后不同热退火处理工艺对介质薄膜质量和存储性能的影响。实验结果表明，N引入GdO介质中导致大量电子陷阱产生，大大增加了存储窗口，且通过5500C/2min的NH3退火处理，能够有效抑制存储层/SiO2界面附近浅能级陷阱的产生，调整存储层中陷阱分布，可获得存储窗口、编程/擦除速度以及疲劳和电荷保持特性之间的较好折衷。
在新型栅堆栈结构方面：①提出了Au/HfAlO/AlN/(HfON/SiO2)/Si多层栅堆栈结构：采用k值相差较大的高k HfON介质层与SiO2结合形成HfON/SiO2双隧穿层结构，提高了电荷注入效率和速度；具有深能级陷阱的AlN作为电荷存储层提供了优良的电荷俘获能力和电荷存储稳定性；高功函数的Au电极以及具有合适k值和势垒高度的HfAlO阻挡层能够有效减少擦除期间来自控制栅的电子注入以及保持期间存储层中电荷的泄漏，缩短擦除时间，提高数据保持力；②从带隙工程出发，提出并制备了由高k介质TiON/HfON组成的双存储层结构，利用淀积后快速热退火过程中Ti、Hf元素的互扩散，形成Ti、Hf含量渐变的Hf1-xTixON混合层，从而形成从隧穿层到阻挡层带隙逐渐增加的锥形能带结构(禁带宽度随Ti含量的增加而单调减小)。Hf1-xTixON混合层具有高的电荷陷阱密度，其锥形能带结构形成的多能级陷阱分布有利于提高陷阱俘获电荷的能力和电荷注入效率，从而获得大的存储窗口和快的编程/擦除速度。另外，存储层锥形能带结构与隧穿层之间较高的势垒高度能有效阻挡陷阱电荷的逸出，从而提高了电荷保持力。
在理论模型研究方面，以陷阱至导带(TB)隧穿作为存储电子的泄漏机制，采用类三角形陷阱能级分布，并考虑陷阱空间分布分别为均匀分布或局域分布两种情况，建立了MONOS型存储器编程状态下的电子保持特性理论模型。通过将模拟仿真结果与实验测量数据进行比较，验证了所建电荷保持特性模型的正确性和准确性。
As next-generation application of the traditional floating-gate flash memory, charge-trapping memory presently faces some severe technique challenges as the technology nodecontinuously scales down, i.e. at low operating voltages, large memory window, fastprogram/erase (P/E) speed, good endurance and10-year data retention must be attained.For metal-oxide-nitride-oxide-silicon (MONOS) memory, the conventional SiO2and Si3N4are substituted by the high-k dielectrics, and hence optimization of the material, structureand fabricating processes of its blocking layer (BL), charge storage layer (CSL) andtunneling layer (TL) will be the main approach of improving performances ofcharge-trapping memory. These are just research work performed in this dissertation.Experimentally, some high-k dielectric materials as CSL are investigated and compared, thenovel dual-CSL and dual-TL structures of high-k/low-k are designed and prepared, andoptimization of the fabrication processes has been carried out to achieve a good trade-offamong the memory window, P/E speed, endurance property and retention characteristics.Theoretically, the electron-retention model of MONOS memory under the programmingstate has been established.
Some investigations have been done on the high-k dielectric materials and fabricatingprocesses of the CSL:①The La-based binary-mixing oxides as the CSL of MONOSmemory are prepared by doping Hf, or Ti, or Y into La oxide and their effects on theperformances of the devices are investigated and compared in detail. It is experimentallyfound that high density of traps with deeper levels and thus high trapping efficiency, strongHf-N and La-N bonds and stable HfLaON/SiO2interface and thus reasonable data retentioncan be achieved by incorporation of N into HfLaO to form HfLaON. Compared to deviceswith LaTiO CSL, the devices with LaYO CSL exhibits larger memory window, higherprogram speed, better retention and endurance properties, suggesting that the Y-doped Laoxide could provide a large amount of bulk traps and thus high charge-trapping efficiency,and effectively suppress formation of the interfacial silicate layer near the CSL/SiO2interface during post-deposition anneal, reducing generation of shallow-level traps or defects;②Using GdO as CSL, the effects of different sputtering ambient (N2or O2) andanneal processing on quality of GdO thin film and performances of the memory areinvestigated. Experimental results indicate that the memory window is greatly increaseddue to generation of a large quantity of electron traps induced by incorporation of N intothe GdO dielectric, and furthermore, a good trade-off among the memory window, P/Espeed, endurance, and retention characteristics can be achieved by NH3annealing at5500Cfor2min, which can effectively suppress creation of shallow-level traps near the CSL/SiO2interface, and thus give suitable spatial distribution of traps with deeper energy level in thebulk of the CSL.
Regarding novel stacked gate structure:①A stacked gate structure of Au/HfAlO/AlN/(HfON/SiO2)/Si is proposed and prepared by in-situ sputtering method, where the ultrathindual-TL of HfON/SiO2is used to increase speed and efficiency of charge injection, the AlNCSL with deep-level traps is employed to provide large memory window, good chargecapturing capability and stability of charge trapping, Au electrode with high work functionand HfAlO BL with suitable k value and barrier height can effectively reduce electroninjection from the control gate into CSL during erasing and leakage of those charges in CSLduring retention, thus shortening erase time and enhancing data retention.②Based onbandgap engineering, a dual CSL composed of TiON/HfON is proposed and prepared, anda tapered bandgap structure with bandgap increasing from the TL to the BL is formed dueto the inter-diffusion between Ti and Hf near the TiON/HfON interface which leads to anintermixing layer of HfxTiyON with varying Hf/Ti ratio in the dual CSL during post-deposition annealing. A large quantity of electron traps exists in the dual CSL due to themixing of HfON and TiON. The tapered bandgap structure can give a multi-level trapdistribution, which is beneficial for enhancing charge capturing capability of traps andcharge injection efficiency, thus obtaining large memory window and high P/E speed. Inaddition, a large barrier height between the TiON and TL can effectively block escaping ofthose trapping charges, enhancing data retention.
Theoretically, an analytical model of electron retention under the programming state isestablished by taking trap-to-band (TB) tunneling as leakage mechanism of the trappedelectrons, assuming a triangle-like energy-level distribution of traps and considering the trap spatial distribution as the uniform or local profiles respectively. The correctness andaccuracy of the model are confirmed by good agreement of the simulated results withexperimental data.
引文
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