基于分离电荷存储的MOS结构存储效应及机理研究
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摘要
随着半导体工艺技术的不断发展,存储单元特征尺寸不断减小,传统的多晶硅浮栅快闪存储器正面临着严峻的挑战。而基于分离电荷存储的非易失性存储器,由于具有分散的电荷存储陷阱,因此可以实现在较薄的隧穿层下良好的数据保持能力,以及低工作电压下的快速擦写功能,是下一代嵌入式快闪存储器最理想的解决方案之一。本论文基于分离的电荷存储方式,分别以介质陷阱和金属纳米晶为电荷存储媒介,结合原子层淀积高介电常数介质和电荷隧穿层能带设计,研究了其金属—氧化物—硅(MOS)结构的存储效应和物理机制。具体内容包括以下几个方面:
采用高温热氧化的SiO_2为电荷隧穿层,原子层淀积(ALD)的HfO_2为电荷俘获层,ALD Al_2O_3,为电荷阻挡层,研究了基于SiO_2\HfO_2\Al_2O_3叠层介质的MIS结构存储效应。结果表明,在+/-12 V的电压扫描范围内,其C—V滞回窗口达到7.3 V。经过5 V和1 ms的电压脉冲编程后,其平带电压漂移+1.5 V。此外,还进一步研究了时间和电压对注入电荷量和电荷注入速率的影响以及存储电荷的保留特性,并从电荷注入和泄漏的机制进行分析。
采用电子束蒸发和快速热退火技术,研究在ALD Al_2O_3薄膜表面制备铂(Pt)纳米晶的工艺。结果表明,在700℃下退火30 s后可以得到密度为2.5×10~(11)cm~(-2),平均直径约为8 nm的铂纳米晶。进一步,制备了以ALD Al_2O_3为电荷隧穿层,Pt纳米晶为电荷俘获层,ALD HfO_2为电荷阻挡层的MIS结构,在-3～+8 v的电压扫描范围内,其C-V滞回窗口为2 V;经过10 V和900 ms的电压脉冲编程后,其平带电压漂移为+2.4 V。
采用磁控溅射和快速热退火技术,研究了在ALD Al_2O_3薄膜表面生长钴(Co)纳米晶的工艺。结果表明,经过500℃下退火15 s后,便可得到大小均匀且致密的钴纳米晶。接着,论文以ALD方法制备了Al_2O_3/HfO_2/Al_2O_3(A\H\A)叠层结构的电荷隧穿层,同时以Co纳米晶为电荷俘获层,以ALD HfO_2为电荷阻挡层的MIS结构。通过对其存储效应的研究表明,采用A\H\A隧穿层比采用等厚度的单一Al_2O_3隧穿层更有利于增大C-V滞回窗口,即在+/-12 V的扫描电压范围内,其滞回窗口增大9 V。这是由于具有冠状能带结构的A\H\A隧穿层在编程和擦除状态下电荷的注入势垒能显著降低,因此提高了电荷注入速度。所以,基于A\H\A隧穿层的钴纳米晶存储电容能表现出低电压下快速擦写的功能,即在+/-7 v下编程/擦除100μs,存储窗口即可达到4.1 V,对应的电子和空穴平均注入速率分别为2.4×10~(16)cm~(-2)s~(-1)和1.9×10~(16)cm~(-2)s~(-1)。
With development of semiconductor technology and downscaling of the memory device size, conventional poly-silicon floating gate flash memories are facing severe challenges. Embedded nonvolatile flash memory devices based on discrete charge storages have recently drawn great attention as a promising replacement of the conventional poly-silicon floating gate structure due to improved retention characteristics in the case of a thinner tunneling layer, and faster program/erase (P/E) speed under lower operating voltages. Based on discrete dielectric traps and metal nanocrystals as charge storage media, in combination with atomic-layer-deposited high permittivity (k) dielectrics and energy band engineering of tunnel layer, this thesis presents memory effects of the corresponding metal-oxide-silicon (MOS) structures, and the involved physical mechanisms are also discussed. The details include the following sections:
Using high temperature oxidized SiO_2 as tunnel layer, atomic layer deposited (ALD) HfO_2 as charge trapping layer, ALD Al_2O_3 as blocking layer, charge trapping characteristics of the metal-insulator-silicon (MIS) capacitors with SiO_2/HfO_2/Al_2O_3 stacked dielectrics have been investigated. A capacitance-voltage (C-V) hysteresis memory window as large as 7.3V is achieved for the gate voltage sweeping of +/- 12V, and a flat-band voltage shift of +1.5V is observed in terms of programming under 5 V and 1ms. Furthermore, the time- and voltage-dependent charge trapping characteristics are also investigated, including quantity of injected charges, charge injection rate and retention characteristic of trapped charges. These are discussed according to the mechanisms of charge injection and leakage.
Using e-beam evaporation and rapid thermal annealing (RTA) techniques, growth of Pt nanocrystals on ALD Al_2O_3 film have been studied. The results show that Pt nanocrystals with a high density of 2.5×10~(11) cm~(-2) and a mean diameter of 8 nm have been achieved after annealing at 700℃for 30 s. Further, MIS capacitors with ALD Al_2O_3 as tunnel layer, Pt nanocrystals as charge trapping layer, ALD HfO_2 as blocking layer have been fabricated and tested. A C-V hysteresis memory window of 2 V is achieved for the gate voltage sweeping from -3 V to +8 V, and a flat-band voltage shift of +2.4 V is observed in terms of programming under 10 V and 900 ms.
Using magnetic sputtering and RTA techniques, growth of Co nanocrystals on ALD Al_2O_3 film have been studied. Uniform and compact Co nanocrystals are formed after annealing at 500℃for 15 s. Further, MIS capacitors with ALD Al_2O_3/HfO_2/Al_2O_3 (A\H\A) as tunnel barrier, Co nanocrystals as charge trapping layer, ALD HfO_2 as blocking layer has been fabrication and investigated. Compared to the identically thick Al_2O_3 tunnel barrier, the A\H\A tunnel barrier can increase significantly the C-V hysteresis window, indicating an increase by 9 V for +/-12 V sweep range. This is attributed to a marked decrease in the energy barrier of charge injections for the A\H\A tunnel barrier, and it helps to increase the charge injection rate. Therefore, the Co-nanocrystal memory capacitor with the A\H\A tunnel barrier exhibits a perfect memory window as large as 4.1 V for 100μs program/erase at a low voltage of +/-7 V, which is associated with fast charge injection rates, i.e., ~2.4×10~(16) cm~(-2)s~(-1) for electrons and 1.9×10~(16) cm~(-2)s~(-1) for holes.
采用高温热氧化的SiO_2为电荷隧穿层,原子层淀积(ALD)的HfO_2为电荷俘获层,ALD Al_2O_3,为电荷阻挡层,研究了基于SiO_2\HfO_2\Al_2O_3叠层介质的MIS结构存储效应。结果表明,在+/-12 V的电压扫描范围内,其C—V滞回窗口达到7.3 V。经过5 V和1 ms的电压脉冲编程后,其平带电压漂移+1.5 V。此外,还进一步研究了时间和电压对注入电荷量和电荷注入速率的影响以及存储电荷的保留特性,并从电荷注入和泄漏的机制进行分析。
采用电子束蒸发和快速热退火技术,研究在ALD Al_2O_3薄膜表面制备铂(Pt)纳米晶的工艺。结果表明,在700℃下退火30 s后可以得到密度为2.5×10~(11)cm~(-2),平均直径约为8 nm的铂纳米晶。进一步,制备了以ALD Al_2O_3为电荷隧穿层,Pt纳米晶为电荷俘获层,ALD HfO_2为电荷阻挡层的MIS结构,在-3～+8 v的电压扫描范围内,其C-V滞回窗口为2 V;经过10 V和900 ms的电压脉冲编程后,其平带电压漂移为+2.4 V。
采用磁控溅射和快速热退火技术,研究了在ALD Al_2O_3薄膜表面生长钴(Co)纳米晶的工艺。结果表明,经过500℃下退火15 s后,便可得到大小均匀且致密的钴纳米晶。接着,论文以ALD方法制备了Al_2O_3/HfO_2/Al_2O_3(A\H\A)叠层结构的电荷隧穿层,同时以Co纳米晶为电荷俘获层,以ALD HfO_2为电荷阻挡层的MIS结构。通过对其存储效应的研究表明,采用A\H\A隧穿层比采用等厚度的单一Al_2O_3隧穿层更有利于增大C-V滞回窗口,即在+/-12 V的扫描电压范围内,其滞回窗口增大9 V。这是由于具有冠状能带结构的A\H\A隧穿层在编程和擦除状态下电荷的注入势垒能显著降低,因此提高了电荷注入速度。所以,基于A\H\A隧穿层的钴纳米晶存储电容能表现出低电压下快速擦写的功能,即在+/-7 v下编程/擦除100μs,存储窗口即可达到4.1 V,对应的电子和空穴平均注入速率分别为2.4×10~(16)cm~(-2)s~(-1)和1.9×10~(16)cm~(-2)s~(-1)。
With development of semiconductor technology and downscaling of the memory device size, conventional poly-silicon floating gate flash memories are facing severe challenges. Embedded nonvolatile flash memory devices based on discrete charge storages have recently drawn great attention as a promising replacement of the conventional poly-silicon floating gate structure due to improved retention characteristics in the case of a thinner tunneling layer, and faster program/erase (P/E) speed under lower operating voltages. Based on discrete dielectric traps and metal nanocrystals as charge storage media, in combination with atomic-layer-deposited high permittivity (k) dielectrics and energy band engineering of tunnel layer, this thesis presents memory effects of the corresponding metal-oxide-silicon (MOS) structures, and the involved physical mechanisms are also discussed. The details include the following sections:
Using high temperature oxidized SiO_2 as tunnel layer, atomic layer deposited (ALD) HfO_2 as charge trapping layer, ALD Al_2O_3 as blocking layer, charge trapping characteristics of the metal-insulator-silicon (MIS) capacitors with SiO_2/HfO_2/Al_2O_3 stacked dielectrics have been investigated. A capacitance-voltage (C-V) hysteresis memory window as large as 7.3V is achieved for the gate voltage sweeping of +/- 12V, and a flat-band voltage shift of +1.5V is observed in terms of programming under 5 V and 1ms. Furthermore, the time- and voltage-dependent charge trapping characteristics are also investigated, including quantity of injected charges, charge injection rate and retention characteristic of trapped charges. These are discussed according to the mechanisms of charge injection and leakage.
Using e-beam evaporation and rapid thermal annealing (RTA) techniques, growth of Pt nanocrystals on ALD Al_2O_3 film have been studied. The results show that Pt nanocrystals with a high density of 2.5×10~(11) cm~(-2) and a mean diameter of 8 nm have been achieved after annealing at 700℃for 30 s. Further, MIS capacitors with ALD Al_2O_3 as tunnel layer, Pt nanocrystals as charge trapping layer, ALD HfO_2 as blocking layer have been fabricated and tested. A C-V hysteresis memory window of 2 V is achieved for the gate voltage sweeping from -3 V to +8 V, and a flat-band voltage shift of +2.4 V is observed in terms of programming under 10 V and 900 ms.
Using magnetic sputtering and RTA techniques, growth of Co nanocrystals on ALD Al_2O_3 film have been studied. Uniform and compact Co nanocrystals are formed after annealing at 500℃for 15 s. Further, MIS capacitors with ALD Al_2O_3/HfO_2/Al_2O_3 (A\H\A) as tunnel barrier, Co nanocrystals as charge trapping layer, ALD HfO_2 as blocking layer has been fabrication and investigated. Compared to the identically thick Al_2O_3 tunnel barrier, the A\H\A tunnel barrier can increase significantly the C-V hysteresis window, indicating an increase by 9 V for +/-12 V sweep range. This is attributed to a marked decrease in the energy barrier of charge injections for the A\H\A tunnel barrier, and it helps to increase the charge injection rate. Therefore, the Co-nanocrystal memory capacitor with the A\H\A tunnel barrier exhibits a perfect memory window as large as 4.1 V for 100μs program/erase at a low voltage of +/-7 V, which is associated with fast charge injection rates, i.e., ~2.4×10~(16) cm~(-2)s~(-1) for electrons and 1.9×10~(16) cm~(-2)s~(-1) for holes.
引文
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[3]J.D.Lee,S.Hur,and J.D.Choi.Effects of floating-gate interference on NAND flash memory cell operation.IEEE Electron Device Letters,23,264 (2002).
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[5]Z.Liu,C.Lee,V.Narayanan,G.Pei,and E.C.Kan.Metal nanocrystal memories.I.Device design and fabrication.IEEE Transactions Electron Devices 49,1606 (2002).
[6]S.M.Tadayyon,K.Griffiths,P.R.Norton,C.Tripp,and Z.Popovic.Work function modification of indium-tin-oxide used in organic light emitting devices.Journal of Vacuum Science & Technology a-Vacuum Surfaces and Films 17,1773 (1999).
[7]J.J.Lee,and D.L.Kwong.Metal nanocrystal memory with high-k tunneling barrier for improved data retention.IEEE Transactions Electron Devices 52,507 (2005).
[8]M.Depas,B.Vermeire,P.W.Mertens,R.L.Van Meirhaeghe.Determination of tunnelling parameters in ultra-thin oxide layer poly-Si/Si02/Si structures.Solid state electonics,38,1465 (1993)
[9]A.Gupta,P.Fang,M.Song,M.R.Lin,D.Wollesen,K.Chen,and C.Hu.Accurate determination of ultrathin gate oxide thickness andeffective polysilicon doping of CMOS devices.IEEE Electron Device Letters,18,580 (1997)
[10]W.C.Lee,C.Hu.Modeling CMOS tunneling currents through ultrathin gate oxide due to conduction-and valence-band electron and hole tunneling.IEEE Transactions Electron Devices,48,1366 (2001).
[11]W.D.BROWN,J.E.BREWER,Nonvolatile semiconductor memory technology:A comprehensive guide to understanding and using NVSM devices.Wiley-IEEE Press,11-12,23-25(1997).
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