基于Ru-RuO_x纳米晶及高K介质的MOS结构存储效应及机理研究
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摘要
随着半导体工艺技术的不断发展，非挥发性快闪存储器集成密度要求越来越高,存储单元特征尺寸需要不断减小,因而传统的多晶硅浮栅快闪存储器正面临着严峻的挑战,如隧穿氧化层的减薄导致数据保存能力退化等。而基于分离电荷存储的非挥发性存储器,可以采用更薄的隧穿氧化层同时保持着良好的数据保留特性,由此可以带来更低的编程／擦除电压和更快的编程／擦除速度,是下一代快闪存储器最理想的解决方案之一。本论文基于分离的电荷存储方式,分别以金属纳米晶、高介电常数(High-k)介质陷阱及两者的复合结构为电荷存储媒介,结合原子层淀积的Al2O3电荷隧穿层和阻挡层以及电子束蒸发高功函数金属Pd电极,研究了其金属—氧化物—半导体(MOS)结构的存储效应和物理机制。具体内容包括以下几个方面：
(1)采用磁控溅射和快速热退火(RTA)技术,研究了在原子层淀积(ALD)的Al2O3薄膜表面生长钌纳米晶的工艺。结果表明,对初始厚度为2 nm的钌膜在900℃下退火30 s可以得到密度为2.0×1012cm-2,平均直径约为5 nm且分布均匀的钌-氧化钌(Ru-RuOx)纳米晶。接着,研究了以ALD Al2O3为电荷隧穿层和阻挡层,Ru-RuOx纳米晶为电荷俘获层的MOS存储电容的性能。结果显示,在-11～+11 V的电压扫描范围内,该MOS电容表现出11.2 V的C-V滞回窗口。为了进一步研究不同隧穿层与阻挡层的厚度比(T/B)对存储效应的影响,本论文固定Al2O3介质厚度不变(28 nm)而改变隧穿层与阻挡层的相对厚度。测试结果显示,在低操作电压下,随着T/B厚度比的增大,存储电容器的C-V滞回窗口和有效注入电荷密度不断减小,而在高操作电压下则几乎无变化。这是由于电荷通过隧穿层的机制不同,在低压下是以直接隧穿为主,而在高压下则是F-N隧穿为主。对于隧穿层为6 nm,阻挡层为22 nm的存储电容,在+/-7 V编程／擦除1 ms后,可获得5.1 V的存储窗口,并且外推至十年后,仍有84%和82%的正电荷和负电荷保留在其上,具有很好的电荷保持特性。
(2)采用ALD方法生长了不同Al2O3/HfO2 (A/H)比例的混合High-k介质作为电荷俘获层,同时采用ALD Al2O3为隧穿层和阻挡层制备了MOS存储电容器。通过对其存储效应的研究发现,随着混合High-k介质层中HfO2比例的增多,MOS电容的电荷捕获能力依次增强,而电荷保存能力则依次减弱。其中以纯HfO2为电荷俘获层的MOS电容,在+／-14 V的电压扫描范围内其C-V滞回窗口达到3.6 V；在+17 V电压下编程10 ms后,其平带电压(Vfb)向正向漂移2 V。在编程后半个小时只有约55%的电荷保留在HfO2电荷俘获层中,且在+17 V时该MOS电容的漏电流大至1.4×10-5 A/cm2。较差的电荷保持特性可能是由于HfO2在800℃退火后其已形成多晶结构,从而沿着晶粒间界的电荷泄漏增大。
(3)研究了以Ru-RuOx纳米晶／High-k介质为复合电荷俘获层,以Al2O3为电荷隧穿层和阻挡层的MOS存储电容器,同时采用高功函数金属Pd作为电极。实验结果表明,采用Ru-RuOx纳米晶/High-k介质的复合电荷俘获层比采用单一Ru-RuOx纳米晶层更有利于增大MOS电容的C-V滞回窗口,当复合电荷俘获层中High-k介质选用Hf02时,在+9～-9 V的扫描电压范围下,MOS电容的滞回窗口比只采用单一Ru-RuOx纳米晶层大10.3 V。这是由于High-k介质的引入增强了降落在隧穿层上的电场强度,因此提高了电荷注入速率。所以,基于Ru-RuOx纳米晶/HfO2复合电荷俘获层的电容,在+／-9 V电压下编程／擦除100μs,存储窗口即可达到3.4 V,对应的电子和空穴平均注入速率分别为2.8×1011cm-2μs-1和3.0×1011 cm-2μs-1并且外推至十年后仍有很好的电荷保持特性。
With development of semiconductor technology and downscaling of the memory device, conventional poly-silicon floating gate flash memories are facing severe challenges. Embedded nonvolatile flash memory devices based on discrete charge storages have recently drawn great attention as a promising replacement of the conventional poly-silicon floating gate structure due to improved retention characteristics in the case of a thinner tunneling layer, and faster program/erase (P/E) speed under lower operating voltages. Based on discrete dielectric traps, metal nanocrystals and compound of the two structures as charge storage media, in combination with atomic-layer-deposited high permittivity (k) dielectrics and e-beam evaporation high work function metal electrode, this thesis presents memory effects of the corresponding metal-oxide-silicon (MOS) structures, and the involved physical mechanisms are also discussed. The details include the following sections:
(1) Growth of Ru-RuOx composite nanodots (RONs) on atomic-layer-deposited Al2O3 film has been investigated using magnetic sputtering of Ru target followed by post-deposition annealing (PDA). The results reveal that the RONs with a small size of 5～6 nm, high-density of～2×1012 cm-2 and good uniformity have been achieved for the PDA at 900℃for 30 s. Subsequently, the electrical characteristics of MOS capacitor with RONs embedded into ALD Al2O3 dielectrics have been measured, indicating a C-V hysteresis window as large as 11.2 V at -11～+11 V sweeping gate voltage. In order to further investigate the influence of different configurations of tunneling-layer (T)/blocking-layer (B) on memory effect, various MOS capacitors with RONs-embedded into ALD Al2O3 insulator have been fabricated using a high work function Pd electrode. The resulting C-V hysteresis window and effective injected charge density exhibit significant dependence on the configuration of T/B in the case of low gate voltages, and approach equal regarding high gate voltages. This is due to different tunneling barriers associated with direct tunneling mechanism dominated under low gate voltage and F-N tunneling mechanism under high gate voltage. With regard to the configuration of T/B=6-nm/22-nm, a memory window as large as 5.1V is achieved for P/E at a low voltage of +/-7 V for 1 ms, and superior charge retention of more than 80% is achieved after ten years.
(2) Using hybrid high-k dielectrics with different ratio of Al2O3/HfO2 (A/H) as a charge trapping layer, various MOS memory capacitors have been fabricated. The electrical characteristics of MOS capacitors were investigated and it reveals that with increasing HfO2, the capability of charge trapping improves and the retention time of charge storage decreases. When the charge trapping layer is pure HfO2, the C-V hysteresis window of MOS capacitor can reach 3.6 V under+/-14 V sweeping voltage. Further, after being programmed at+17 V for 10 ms, its flat band voltage (Vfb) drifts towards positive for +2 V. However, only about 55% charges are retained in HfO2 half hour later, and the leakage current of MOS capacitor becomes as large as 1.4×10-5 A/cm2. This is attributed to the low HfO2 crystalline temperature, which leads to a large leakage current along the grain boundary.
(3) Using compound of the Ru-RuOx NCs/High-k dielectric as a charge trapping layer, ALD Al2O3 as tunneling and blocking layer, various MOS capacitors with Pd electrode have been fabricated. Compared to single Ru-RuOx NCs charge trapping layer, the compound one can increase significantly the C-V hysteresis window. When the high-k trapping layer is pure HfO2, the C-V hysteresis can increase by 10.3 V for +/-9 V sweeping voltage. This is attributed to an enhancement of the electric field dropping on the tunneling layer, and it helps to increase the charge injection rate. Therefore, the MOS capacitor with Ru-RuOx/HfO2 charge trapping layer exhibits a perfect memory window as large as 3.4 V for 100μs P/E at a low voltage of +/-9 V, which is associated with fast charge injection rates, i.e.,～2.8×1011 cm-2s-1 for electrons and～3.0×1011 cm-2s-1 for holes. Also it shows superior charge retention characteristic after ten years.
(1)采用磁控溅射和快速热退火(RTA)技术,研究了在原子层淀积(ALD)的Al2O3薄膜表面生长钌纳米晶的工艺。结果表明,对初始厚度为2 nm的钌膜在900℃下退火30 s可以得到密度为2.0×1012cm-2,平均直径约为5 nm且分布均匀的钌-氧化钌(Ru-RuOx)纳米晶。接着,研究了以ALD Al2O3为电荷隧穿层和阻挡层,Ru-RuOx纳米晶为电荷俘获层的MOS存储电容的性能。结果显示,在-11～+11 V的电压扫描范围内,该MOS电容表现出11.2 V的C-V滞回窗口。为了进一步研究不同隧穿层与阻挡层的厚度比(T/B)对存储效应的影响,本论文固定Al2O3介质厚度不变(28 nm)而改变隧穿层与阻挡层的相对厚度。测试结果显示,在低操作电压下,随着T/B厚度比的增大,存储电容器的C-V滞回窗口和有效注入电荷密度不断减小,而在高操作电压下则几乎无变化。这是由于电荷通过隧穿层的机制不同,在低压下是以直接隧穿为主,而在高压下则是F-N隧穿为主。对于隧穿层为6 nm,阻挡层为22 nm的存储电容,在+/-7 V编程／擦除1 ms后,可获得5.1 V的存储窗口,并且外推至十年后,仍有84%和82%的正电荷和负电荷保留在其上,具有很好的电荷保持特性。
(2)采用ALD方法生长了不同Al2O3/HfO2 (A/H)比例的混合High-k介质作为电荷俘获层,同时采用ALD Al2O3为隧穿层和阻挡层制备了MOS存储电容器。通过对其存储效应的研究发现,随着混合High-k介质层中HfO2比例的增多,MOS电容的电荷捕获能力依次增强,而电荷保存能力则依次减弱。其中以纯HfO2为电荷俘获层的MOS电容,在+／-14 V的电压扫描范围内其C-V滞回窗口达到3.6 V；在+17 V电压下编程10 ms后,其平带电压(Vfb)向正向漂移2 V。在编程后半个小时只有约55%的电荷保留在HfO2电荷俘获层中,且在+17 V时该MOS电容的漏电流大至1.4×10-5 A/cm2。较差的电荷保持特性可能是由于HfO2在800℃退火后其已形成多晶结构,从而沿着晶粒间界的电荷泄漏增大。
(3)研究了以Ru-RuOx纳米晶／High-k介质为复合电荷俘获层,以Al2O3为电荷隧穿层和阻挡层的MOS存储电容器,同时采用高功函数金属Pd作为电极。实验结果表明,采用Ru-RuOx纳米晶/High-k介质的复合电荷俘获层比采用单一Ru-RuOx纳米晶层更有利于增大MOS电容的C-V滞回窗口,当复合电荷俘获层中High-k介质选用Hf02时,在+9～-9 V的扫描电压范围下,MOS电容的滞回窗口比只采用单一Ru-RuOx纳米晶层大10.3 V。这是由于High-k介质的引入增强了降落在隧穿层上的电场强度,因此提高了电荷注入速率。所以,基于Ru-RuOx纳米晶/HfO2复合电荷俘获层的电容,在+／-9 V电压下编程／擦除100μs,存储窗口即可达到3.4 V,对应的电子和空穴平均注入速率分别为2.8×1011cm-2μs-1和3.0×1011 cm-2μs-1并且外推至十年后仍有很好的电荷保持特性。
With development of semiconductor technology and downscaling of the memory device, conventional poly-silicon floating gate flash memories are facing severe challenges. Embedded nonvolatile flash memory devices based on discrete charge storages have recently drawn great attention as a promising replacement of the conventional poly-silicon floating gate structure due to improved retention characteristics in the case of a thinner tunneling layer, and faster program/erase (P/E) speed under lower operating voltages. Based on discrete dielectric traps, metal nanocrystals and compound of the two structures as charge storage media, in combination with atomic-layer-deposited high permittivity (k) dielectrics and e-beam evaporation high work function metal electrode, this thesis presents memory effects of the corresponding metal-oxide-silicon (MOS) structures, and the involved physical mechanisms are also discussed. The details include the following sections:
(1) Growth of Ru-RuOx composite nanodots (RONs) on atomic-layer-deposited Al2O3 film has been investigated using magnetic sputtering of Ru target followed by post-deposition annealing (PDA). The results reveal that the RONs with a small size of 5～6 nm, high-density of～2×1012 cm-2 and good uniformity have been achieved for the PDA at 900℃for 30 s. Subsequently, the electrical characteristics of MOS capacitor with RONs embedded into ALD Al2O3 dielectrics have been measured, indicating a C-V hysteresis window as large as 11.2 V at -11～+11 V sweeping gate voltage. In order to further investigate the influence of different configurations of tunneling-layer (T)/blocking-layer (B) on memory effect, various MOS capacitors with RONs-embedded into ALD Al2O3 insulator have been fabricated using a high work function Pd electrode. The resulting C-V hysteresis window and effective injected charge density exhibit significant dependence on the configuration of T/B in the case of low gate voltages, and approach equal regarding high gate voltages. This is due to different tunneling barriers associated with direct tunneling mechanism dominated under low gate voltage and F-N tunneling mechanism under high gate voltage. With regard to the configuration of T/B=6-nm/22-nm, a memory window as large as 5.1V is achieved for P/E at a low voltage of +/-7 V for 1 ms, and superior charge retention of more than 80% is achieved after ten years.
(2) Using hybrid high-k dielectrics with different ratio of Al2O3/HfO2 (A/H) as a charge trapping layer, various MOS memory capacitors have been fabricated. The electrical characteristics of MOS capacitors were investigated and it reveals that with increasing HfO2, the capability of charge trapping improves and the retention time of charge storage decreases. When the charge trapping layer is pure HfO2, the C-V hysteresis window of MOS capacitor can reach 3.6 V under+/-14 V sweeping voltage. Further, after being programmed at+17 V for 10 ms, its flat band voltage (Vfb) drifts towards positive for +2 V. However, only about 55% charges are retained in HfO2 half hour later, and the leakage current of MOS capacitor becomes as large as 1.4×10-5 A/cm2. This is attributed to the low HfO2 crystalline temperature, which leads to a large leakage current along the grain boundary.
(3) Using compound of the Ru-RuOx NCs/High-k dielectric as a charge trapping layer, ALD Al2O3 as tunneling and blocking layer, various MOS capacitors with Pd electrode have been fabricated. Compared to single Ru-RuOx NCs charge trapping layer, the compound one can increase significantly the C-V hysteresis window. When the high-k trapping layer is pure HfO2, the C-V hysteresis can increase by 10.3 V for +/-9 V sweeping voltage. This is attributed to an enhancement of the electric field dropping on the tunneling layer, and it helps to increase the charge injection rate. Therefore, the MOS capacitor with Ru-RuOx/HfO2 charge trapping layer exhibits a perfect memory window as large as 3.4 V for 100μs P/E at a low voltage of +/-9 V, which is associated with fast charge injection rates, i.e.,～2.8×1011 cm-2s-1 for electrons and～3.0×1011 cm-2s-1 for holes. Also it shows superior charge retention characteristic after ten years.
引文
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