列车通信网中多功能车辆总线一类设备的FPGA实现
摘要
多功能车辆总线一类设备是一个在列车通信网(TCN，TrainCommunication Network)中普遍使用的网络接口单元。目前我国的新式列车大多采用列车通信网传输列车中大量的控制和服务信息。但使用的列车通信网产品主要为国外进口，因此迫切需要研制具有自主知识产权的列车通信网产品。
论文以一类设备控制器的设计为核心，采取自顶向下的模块设计方法。将设备控制器分为同步层和数据处理层来分别实现对帧的发送与接收处理和对帧数据的提取与存储处理。
同步层包含帧的识别模块、曼彻斯特译码模块、曼彻斯特编码与帧封装三个模块。帧识别模块检测帧的起始位并对帧类型进行判断。译码模块根据采集的样本值来判断曼彻斯特编码的值，采样的难点在于非理想信号带来的采样误差，论文使用结合位同步的多点采样法来提高采样质量。帧分界符中的非数据符不需要进行曼彻斯特编码，编码时在非数据符位关闭编码电路使非数据符保持原来的编码输出。
数据处理层以主控单元(MCU，Main Control Unit)和通信存储器为设计核心。MCU是控制器的核心，对接收的主帧进行分析，判断是从通信存储器相应端口取出应答从帧并发送，还是准备接收从帧并存入通信存储器。通信存储器存储设备的通信数据，合适的地址分配能简化MCU的控制程序，论文固定了通信存储器端口大小使MCU可以根据一个固定的公式进行端口的遍历从而简化了MCU程序的复杂度。数据在传输中由于受到干扰和冲突等问题而出现错误，论文采用循环冗余检验码结合偶检验扩展来对传输数据进行差错控制。
最后，使用FPGA和硬件描述语言Verilog HDL开发出了MVB一类设备。目前该一类设备已运用在SS4G电力机车的制动控制单元(BCU，Brake Control Unit)中并在铁道科学研究院通过了TCN通信测试。一类设备的成功研制为列车通信网中总线管理器等高类设备的开发奠定了坚实的基础。
MVB (Multifunction Vehicle Bus) Class 1 device is a kind of network interface unit which is widely used in Train Communication Network (TCN). Nowadays, to transmit lots of control and service information, the new-style locomotive in our country uses TCN mostly. However, the network equipments are mostly imported from abroad. So it is urgent for our country to develop TCN products of independent intellectual property rights.
This dissertation mainly focuses on the design of Class 1 devices controller, and adopts a top-down module design method, in which Class 1 device controller is divided into synchronization layer and data processing layer. In Each layer, some functions are realized to send and receive frame, and to extract and store of frame data, respectively.
In the Synchronization layer, there are three modules consisted: frame recognition module, Manchester encoding module, and. Manchester coding and frame packaging module. Firstly, in the frame recognition module, the start bit of frame is examined while the type of frame is judged. Then the Manchester coding value is judged in the frame encoding module according to the sample. When sampling, the difficulty is that errors are brought by the non-ideal signals. To enhance the quality of sampling, a multi-spots sampling method combined with bit synchronization is introduced in this dissertation. As non-data symbols are not needed to be coded, the coding circuit is closed for the now-data symbols when coding, thus the non-data symbols can be outputted with its original format.
In the data processing layer, the main control unit (MCU) and traffic memory data are designed as the core. The MCU is the core of the controller, in which the received main frame are analyzed then corresponding action is selected according to the commutation mode of the variable. Alternatively, to extract and send the slave frame from the corresponding ports of Traffic Memory, or to prepare to receive the slave frame and write it into Traffic Memory. While in traffic Memory, communication data is stored, appropriate address assignment will Simplify control program. To Simplified the complexity of MCU program, in this dissertation, the port size of Traffic Memory is invariable so that it can traversals the port by a fixed formula to predigest the complexity of MCU program. Besides, as a lot of errors may occur in the process of data transmission because of disturbance and conflict, Cyclic Redundancy Check combined with dual checkout extension is adopted in this dissertation to implement error control of the transmitted data in the design of MCU.
Finally, MVB Class 1 device is developed using FPGA and Verilog HDL which is a kind of hardware description language. Recently the device has applied in the SS4G electric locomotive Brake Control Unit and passed the TCN communication test in Railway Academy of Science. The successful development of the Class 1 device establishes a stable foundation for the exploitation of the Bus Administrator and gateway of TCN.
论文以一类设备控制器的设计为核心，采取自顶向下的模块设计方法。将设备控制器分为同步层和数据处理层来分别实现对帧的发送与接收处理和对帧数据的提取与存储处理。
同步层包含帧的识别模块、曼彻斯特译码模块、曼彻斯特编码与帧封装三个模块。帧识别模块检测帧的起始位并对帧类型进行判断。译码模块根据采集的样本值来判断曼彻斯特编码的值，采样的难点在于非理想信号带来的采样误差，论文使用结合位同步的多点采样法来提高采样质量。帧分界符中的非数据符不需要进行曼彻斯特编码，编码时在非数据符位关闭编码电路使非数据符保持原来的编码输出。
数据处理层以主控单元(MCU，Main Control Unit)和通信存储器为设计核心。MCU是控制器的核心，对接收的主帧进行分析，判断是从通信存储器相应端口取出应答从帧并发送，还是准备接收从帧并存入通信存储器。通信存储器存储设备的通信数据，合适的地址分配能简化MCU的控制程序，论文固定了通信存储器端口大小使MCU可以根据一个固定的公式进行端口的遍历从而简化了MCU程序的复杂度。数据在传输中由于受到干扰和冲突等问题而出现错误，论文采用循环冗余检验码结合偶检验扩展来对传输数据进行差错控制。
最后，使用FPGA和硬件描述语言Verilog HDL开发出了MVB一类设备。目前该一类设备已运用在SS4G电力机车的制动控制单元(BCU，Brake Control Unit)中并在铁道科学研究院通过了TCN通信测试。一类设备的成功研制为列车通信网中总线管理器等高类设备的开发奠定了坚实的基础。
MVB (Multifunction Vehicle Bus) Class 1 device is a kind of network interface unit which is widely used in Train Communication Network (TCN). Nowadays, to transmit lots of control and service information, the new-style locomotive in our country uses TCN mostly. However, the network equipments are mostly imported from abroad. So it is urgent for our country to develop TCN products of independent intellectual property rights.
This dissertation mainly focuses on the design of Class 1 devices controller, and adopts a top-down module design method, in which Class 1 device controller is divided into synchronization layer and data processing layer. In Each layer, some functions are realized to send and receive frame, and to extract and store of frame data, respectively.
In the Synchronization layer, there are three modules consisted: frame recognition module, Manchester encoding module, and. Manchester coding and frame packaging module. Firstly, in the frame recognition module, the start bit of frame is examined while the type of frame is judged. Then the Manchester coding value is judged in the frame encoding module according to the sample. When sampling, the difficulty is that errors are brought by the non-ideal signals. To enhance the quality of sampling, a multi-spots sampling method combined with bit synchronization is introduced in this dissertation. As non-data symbols are not needed to be coded, the coding circuit is closed for the now-data symbols when coding, thus the non-data symbols can be outputted with its original format.
In the data processing layer, the main control unit (MCU) and traffic memory data are designed as the core. The MCU is the core of the controller, in which the received main frame are analyzed then corresponding action is selected according to the commutation mode of the variable. Alternatively, to extract and send the slave frame from the corresponding ports of Traffic Memory, or to prepare to receive the slave frame and write it into Traffic Memory. While in traffic Memory, communication data is stored, appropriate address assignment will Simplify control program. To Simplified the complexity of MCU program, in this dissertation, the port size of Traffic Memory is invariable so that it can traversals the port by a fixed formula to predigest the complexity of MCU program. Besides, as a lot of errors may occur in the process of data transmission because of disturbance and conflict, Cyclic Redundancy Check combined with dual checkout extension is adopted in this dissertation to implement error control of the transmitted data in the design of MCU.
Finally, MVB Class 1 device is developed using FPGA and Verilog HDL which is a kind of hardware description language. Recently the device has applied in the SS4G electric locomotive Brake Control Unit and passed the TCN communication test in Railway Academy of Science. The successful development of the Class 1 device establishes a stable foundation for the exploitation of the Bus Administrator and gateway of TCN.
引文
[1] 左健存，蒋晓黎．高速列车通信网的技术特点及其在机车车辆上的应用．交通与计算机．1999，17(4)：41～44
[2] International Electrotechnical Commission. IEC61375-1: Electric Railway Equipment-Train Bus Part Ⅰ: Train Network. IEC, 1999
[3] 刘波．基于多功能车辆总线的列车网络关键技术的研究与应用：[硕士学位论文]．长沙：中南大学，2005
[4] ABB Daimler-Benz Transportation, Multifunction Vehicle Bus Controller. Switzerland, 2001. 1～14
[5] 蔡颖，诸昌铃．MVB网络接口单元的FPGA实现．铁道机车车辆．2005，25(3)：27～28
[6] 路向阳．我国列车通信网络发展与应用．机车电传动．2001，(6)：1～5
[7] 阳宪惠．现场总线技术及其应用．北京：清华大学出版社，2002．213～216
[8] 奚国华，路向阳，夏寅．我国列车通信网络的实践与开发探讨．机车电传动．2000，(1)：2～5
[9] 李红．MVB1类设备控制器的FPGA实现：[硕士学位论文]．大连：大连理工大学，2006
[10] 周缵．一个典型的嵌入式系统设计和实现．电子工程专辑．2005年3月
[11] 王锋．基于FPGA的MVB1类设备网卡的设计．机车电传动．2004，(6)：21～23
[12] 褚振勇，翁木云．FPGA设计及应用．西安：电子科技大学出版社，2002．20～28
[13] Kirrmann H., Koopman P. Train Communication Network & FlexRay. Distributed Embedded Systems. Switzerland, 2002. 5～11
[14] 谢步明，赵明元．列车通信网结构及其协议的研究．机车电传动．2000，(5)：1～4
[15] Kirrmann H., Zuber P. The IEC/IEEE train communication network. IEEE Micro. 2001, 21 (2): 81～92
[16] 张元林，梁波．基于MVBC的分布式智能I／O模块的研究．机车电传动．2002，(4)：15～18
[17] Xilinx corporation. Spartan-Ⅱ 2.5V FPGA Family: DC and Switching Characteristics. America, 2001
[18] 王诚，薛小刚，钟信潮．FPGA／CPLD设计工具——Xilinx ISE使用详解．北京：人民邮电出版社，2003．2～4
[19] 夏宇闻．Verilog数字系统设计教程．北京：北京航空航天大学出版社，2003．2～3
[20] 巴斯克尔·J．Verilog HDL硬件描述语言(徐振林等译)．北京：机械工业出版社，2000
[21] 袁俊泉，孙敏琪，曹瑞．Verilog HDL数字系统设计及其应用．西安：西安电子科技大学出版社，2002
[22] 常晓明．Verilog HDL实践与应用系统设计．北京：北京航空航天大学出版社，2003
[23] 邓奉立．64位RISC CPU在FPGA上的实现与验证：[硕士学位论文]．成都电子科技大学，2002
[24] Adtranz. Multifunction Vehicle Bus Controller Data Sheet. Adtranz, 1997
[25] Duagon corporation. TCN Software Architecture. Switzerland, 2003. 14～16
[26] Fabri A., Umiliacchi P. Use of the Internet for Remote Train Monitoring and Control: the ROSIN Project. Proceedings of Rail Technology. London: 1999, http://www.labs.it/rosin/docs/TelecomRail98.pdf
[27] Koopman P., Chakravarty T. Analysis of the Train Communication NetworkProtocol Error Detection Capabilities. At http://citeseer.nj.nec.com/557835.html
[28] Schafers C., Hans G, IEC 61375-1 and UIC 556-International Standards for Train Communication Network, in Proceedings of the51st IEEE Vehicular Technology Conf., Japan, May 2000, pp. 1581～1585
[29] American National Standards Institute (ANSI), Communication Protocol Abroad Trains-1473-1999, 1999
[30] Moreno J.C., Laloya E.J., and Navarro J. MVB Slave Devices: Link Layer and Real Time Protocols Functional Description and Design, Internal Technical Report. Group of Electronic Design in Digital Communications. University of Zaragoza, Jan. 2005
[31] Duagon corporation. Integration Guide for duagon pc104 products. Witzerland, 2003. 4～7
[32] 彭军，刘波．列车通信网的编址与寻址方法的研究．计算机测量与控制．2005，13(1)：79～82
[33] Duagon corporation. Boot Loader MicroMonitor. Switzerland, 2003. 10～11
[34] Duagon corporation. MVB Software Application Interface. Switzerland, 2003. 6～9
[35] Jimenez J., Martin J. Comparison of two designs for the Multifunction Vehicle Bus. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2006, 25(5): 797～805
[36] Chavarria A. Slave node architecture for Train Communications Networks. 26th Annual Conference of the IEEE Electronics Society IECON 2000, Nagoya, 2000: 2431～2464
[37] 何俊．车辆总线数据链路层研究和CPLD实现：[硕士学位论文]．武汉：武汉理工大学，2006
[38] 苟帅．两种基于总线结构的局域网通信协议的分析与实现：[硕士学位论文]．成都：西南交通大学，2002
[39] 雷震甲．计算机网络．西安：西安电子科技大学出版社，2001．28～33
[40] Duagon corporation, d412 Diagnostic System. Switzerland, 2003. 11～12
[41] 甄真．UIC网关PDM模块的设计与实现：[硕士学位论文]．大连：大连理工大学，2006
[42] Xilinx corporation. Platform Flash In-System Programmable Configuration PROMS. America, 2005
[43] Xilinx corporation. Spartan-Ⅱ 2.5V FPGA Family: Introduction and Ordering Information. America, 2001
[44] Moreno J.C., Laloya E.J. and Navarro J. Line Redundancy in MVB-TCN Devices: A Control Unit Design. IEEE MELECON 2006. Department of Electronic Engineering and Communications. University of Zaragoza, Spain, 2005: 789～794
[2] International Electrotechnical Commission. IEC61375-1: Electric Railway Equipment-Train Bus Part Ⅰ: Train Network. IEC, 1999
[3] 刘波．基于多功能车辆总线的列车网络关键技术的研究与应用：[硕士学位论文]．长沙：中南大学，2005
[4] ABB Daimler-Benz Transportation, Multifunction Vehicle Bus Controller. Switzerland, 2001. 1～14
[5] 蔡颖，诸昌铃．MVB网络接口单元的FPGA实现．铁道机车车辆．2005，25(3)：27～28
[6] 路向阳．我国列车通信网络发展与应用．机车电传动．2001，(6)：1～5
[7] 阳宪惠．现场总线技术及其应用．北京：清华大学出版社，2002．213～216
[8] 奚国华，路向阳，夏寅．我国列车通信网络的实践与开发探讨．机车电传动．2000，(1)：2～5
[9] 李红．MVB1类设备控制器的FPGA实现：[硕士学位论文]．大连：大连理工大学，2006
[10] 周缵．一个典型的嵌入式系统设计和实现．电子工程专辑．2005年3月
[11] 王锋．基于FPGA的MVB1类设备网卡的设计．机车电传动．2004，(6)：21～23
[12] 褚振勇，翁木云．FPGA设计及应用．西安：电子科技大学出版社，2002．20～28
[13] Kirrmann H., Koopman P. Train Communication Network & FlexRay. Distributed Embedded Systems. Switzerland, 2002. 5～11
[14] 谢步明，赵明元．列车通信网结构及其协议的研究．机车电传动．2000，(5)：1～4
[15] Kirrmann H., Zuber P. The IEC/IEEE train communication network. IEEE Micro. 2001, 21 (2): 81～92
[16] 张元林，梁波．基于MVBC的分布式智能I／O模块的研究．机车电传动．2002，(4)：15～18
[17] Xilinx corporation. Spartan-Ⅱ 2.5V FPGA Family: DC and Switching Characteristics. America, 2001
[18] 王诚，薛小刚，钟信潮．FPGA／CPLD设计工具——Xilinx ISE使用详解．北京：人民邮电出版社，2003．2～4
[19] 夏宇闻．Verilog数字系统设计教程．北京：北京航空航天大学出版社，2003．2～3
[20] 巴斯克尔·J．Verilog HDL硬件描述语言(徐振林等译)．北京：机械工业出版社，2000
[21] 袁俊泉，孙敏琪，曹瑞．Verilog HDL数字系统设计及其应用．西安：西安电子科技大学出版社，2002
[22] 常晓明．Verilog HDL实践与应用系统设计．北京：北京航空航天大学出版社，2003
[23] 邓奉立．64位RISC CPU在FPGA上的实现与验证：[硕士学位论文]．成都电子科技大学，2002
[24] Adtranz. Multifunction Vehicle Bus Controller Data Sheet. Adtranz, 1997
[25] Duagon corporation. TCN Software Architecture. Switzerland, 2003. 14～16
[26] Fabri A., Umiliacchi P. Use of the Internet for Remote Train Monitoring and Control: the ROSIN Project. Proceedings of Rail Technology. London: 1999, http://www.labs.it/rosin/docs/TelecomRail98.pdf
[27] Koopman P., Chakravarty T. Analysis of the Train Communication NetworkProtocol Error Detection Capabilities. At http://citeseer.nj.nec.com/557835.html
[28] Schafers C., Hans G, IEC 61375-1 and UIC 556-International Standards for Train Communication Network, in Proceedings of the51st IEEE Vehicular Technology Conf., Japan, May 2000, pp. 1581～1585
[29] American National Standards Institute (ANSI), Communication Protocol Abroad Trains-1473-1999, 1999
[30] Moreno J.C., Laloya E.J., and Navarro J. MVB Slave Devices: Link Layer and Real Time Protocols Functional Description and Design, Internal Technical Report. Group of Electronic Design in Digital Communications. University of Zaragoza, Jan. 2005
[31] Duagon corporation. Integration Guide for duagon pc104 products. Witzerland, 2003. 4～7
[32] 彭军，刘波．列车通信网的编址与寻址方法的研究．计算机测量与控制．2005，13(1)：79～82
[33] Duagon corporation. Boot Loader MicroMonitor. Switzerland, 2003. 10～11
[34] Duagon corporation. MVB Software Application Interface. Switzerland, 2003. 6～9
[35] Jimenez J., Martin J. Comparison of two designs for the Multifunction Vehicle Bus. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2006, 25(5): 797～805
[36] Chavarria A. Slave node architecture for Train Communications Networks. 26th Annual Conference of the IEEE Electronics Society IECON 2000, Nagoya, 2000: 2431～2464
[37] 何俊．车辆总线数据链路层研究和CPLD实现：[硕士学位论文]．武汉：武汉理工大学，2006
[38] 苟帅．两种基于总线结构的局域网通信协议的分析与实现：[硕士学位论文]．成都：西南交通大学，2002
[39] 雷震甲．计算机网络．西安：西安电子科技大学出版社，2001．28～33
[40] Duagon corporation, d412 Diagnostic System. Switzerland, 2003. 11～12
[41] 甄真．UIC网关PDM模块的设计与实现：[硕士学位论文]．大连：大连理工大学，2006
[42] Xilinx corporation. Platform Flash In-System Programmable Configuration PROMS. America, 2005
[43] Xilinx corporation. Spartan-Ⅱ 2.5V FPGA Family: Introduction and Ordering Information. America, 2001
[44] Moreno J.C., Laloya E.J. and Navarro J. Line Redundancy in MVB-TCN Devices: A Control Unit Design. IEEE MELECON 2006. Department of Electronic Engineering and Communications. University of Zaragoza, Spain, 2005: 789～794