Sigma-Delta ADC的低压低功耗设计技术研究
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摘要
随着集成电路特征线宽的持续缩小，芯片的工作频率、集成度和复杂性大幅增加，功耗也随之急剧增加。而近年来以电池供电的移动电话、数码相机、PDA等便携式电子产品迅速发展，消费者对便携式设备的续航能力有着持续增长的需求。因此，集成电路的低压低功耗设计已成为学术界和工程界的研究热点和难点。而Sigma-Delta模数转换器由于采用了过采样和噪声整形技术，能以较低成本达到较高的转换精度，在便携式电子产品中获得了广泛的应用。基于以上两点原因，论文主要针对Sigma-Delta模数转换器开展混合信号集成电路低压低功耗设计的研究。
鉴于模拟和数字集成电路设计方法的差异性，论文对模拟电路和数字电路低压低功耗设计的现有技术分别作了整理、归纳和总结。介绍了Sigma-Delta模数转换器的基本工作原理、采用的主要技术以及发展现状。在此基础上，对Sigma-Delta模数转换器中的模拟电路和数字电路分别进行了低压低功耗设计。
针对模拟电路部分，即Sigma-Delta调制器，本文在系统级分析了影响调制器功耗的各种本质的和非理想的因素，讨论了如何根据系统设计要求确定调制器的阶数以获取最低功耗；在结构级提出了一种能够实现小电容比值的开关电容积分器结构，从而解决零点优化中遇到的小系数实现问题，与传统积分器结构相比，大幅度地减小了电容面积，降低了功耗；在电路级对运放进行了功耗分析，对运放的典型结构进行了比较，并根据调制器的工作特点提出了两级AB／AB结构，和用交叉耦合对负载消除第一级共模反馈电路的方法，进一步降低调制器正常工作时的功耗。本文还分析了Sigma-Delta调制器中各种非理想因素，介绍了如何根据这些非理想因素计算得出满足系统要求的各模块的最低性能指标，亦即满足系统要求的最低实现功耗。研究结果经系统仿真验证了正确性。
针对数字电路部分，即抽样滤波器，本文分析了其在不同降采样率下的不同特点，分别针对低降采样率和高降采样率两种应用环境对抽样滤波器的结构进行了优化。在低过采样率应用环境中，分析与比较了梳状滤波器的三种不同实现结构，并提出了一种经过改进的多项式结构。仿真结果表明改进结构可比传统的CIC结构节省36％的面积和50％的功耗，比近期报道的多项式结构亦减少14％的面积和3％的功耗。在高过采样率工作环境下，论证了CIC结构的优越性，并根据抽样滤波器在该工作条件下的特点，提出了一种低采样率梳状滤波器带多级半带滤波器的优化结构。该部分所有工作都在TSMC 0.18μm工艺下设计完成。
As the feature size of modern integrated circuit (IC) keeps reducing, its operation frequency, density and complexity as well as its power dissipation is continuously increasing. Meanwhile, battery-charged portable electronic devices such as mobile phone, digital camera, PDA and so on are also developing very fast. The demand of long stand-by time of the consumer products keeps increasing. So, low voltage low power design of integrated circuits becomes one of the hot and difficult research areas in both academia and industry. On the other hand, more and more Sigma-Delta ADCs are applied to the portable electronic devices recently, which could offer quite a high resolution at a low cost due to utilizing the oversampling and noise shaping technology. For these reasons, as a good example, the thesis focused the research of low voltage low power mixed-signal IC on Sigma-Delta ADC.
Because of differences between design methods for analog and digital circuits, the recent approaches to low power design of digital and analog circuits were discussed, summarized and organized respectively. The fundamental principles, current technologies and developments on Sigma-Delta ADC were introduced. And the low voltage low power design for analog and digital circuits in it was conducted.
As to the analog part, Sigma-Delta modulator, all kinds of essential and non-ideal factors that are related to the power consumption of modulators were analyzed in the system level. Based on the analysis, it was discussed that how to fix the order for modulators to fulfill the system requirements as well as to achieve the minimum power. In the structure level, a new structure of switched-capacitor integrators was proposed to realize a small coefficient and solve the problem in zero optimization. Compared to the traditional one, this new structure largely reduced the area and power consumed by capacitors. In circuit level, the power consumption in operational amplifiers was analyzed. After analyzing and comparing several classical structures of operational amplifiers, a new structure of class AB/AB was proposed to reduce the power consumption in general operations. A kind of cross-couple load was used to eliminate the CMFB circuit in the first stage to further reduce the power. This thesis also analyzed all kinds of important non-idea factors in Sigma-Delta modulators, and introduced methods to calculate the minimum spec for all modules according to these factors, which means the required minimum power in order to fulfill the system requirements. The validity of research results was verified by system simulation.
As to the digital part, decimation filter, different characteristics under different down-sampling rates were analyzed. Two structure optimization schemes for decimation filters working in different down-sampling rates were presented respectively. As to the low down-sampling rate, three different structures to implement the sinc filter were analyzed and compared, a modified polyphase structure was proposed. Simulation results showed that in comparison with traditional CIC structure, the new structure could save about 36% area and 50% power. The results were also better than the latest reported polyphase structure: about 14% area and 3% power could be saved. As to the high down-sampling rate, the advantage of CIC structure was testified. And the optimization for the decimation structure was brought forward based on the distribution of power dissipation. All work in this part was completed in TSMC 0.18μm technology.
鉴于模拟和数字集成电路设计方法的差异性，论文对模拟电路和数字电路低压低功耗设计的现有技术分别作了整理、归纳和总结。介绍了Sigma-Delta模数转换器的基本工作原理、采用的主要技术以及发展现状。在此基础上，对Sigma-Delta模数转换器中的模拟电路和数字电路分别进行了低压低功耗设计。
针对模拟电路部分，即Sigma-Delta调制器，本文在系统级分析了影响调制器功耗的各种本质的和非理想的因素，讨论了如何根据系统设计要求确定调制器的阶数以获取最低功耗；在结构级提出了一种能够实现小电容比值的开关电容积分器结构，从而解决零点优化中遇到的小系数实现问题，与传统积分器结构相比，大幅度地减小了电容面积，降低了功耗；在电路级对运放进行了功耗分析，对运放的典型结构进行了比较，并根据调制器的工作特点提出了两级AB／AB结构，和用交叉耦合对负载消除第一级共模反馈电路的方法，进一步降低调制器正常工作时的功耗。本文还分析了Sigma-Delta调制器中各种非理想因素，介绍了如何根据这些非理想因素计算得出满足系统要求的各模块的最低性能指标，亦即满足系统要求的最低实现功耗。研究结果经系统仿真验证了正确性。
针对数字电路部分，即抽样滤波器，本文分析了其在不同降采样率下的不同特点，分别针对低降采样率和高降采样率两种应用环境对抽样滤波器的结构进行了优化。在低过采样率应用环境中，分析与比较了梳状滤波器的三种不同实现结构，并提出了一种经过改进的多项式结构。仿真结果表明改进结构可比传统的CIC结构节省36％的面积和50％的功耗，比近期报道的多项式结构亦减少14％的面积和3％的功耗。在高过采样率工作环境下，论证了CIC结构的优越性，并根据抽样滤波器在该工作条件下的特点，提出了一种低采样率梳状滤波器带多级半带滤波器的优化结构。该部分所有工作都在TSMC 0.18μm工艺下设计完成。
As the feature size of modern integrated circuit (IC) keeps reducing, its operation frequency, density and complexity as well as its power dissipation is continuously increasing. Meanwhile, battery-charged portable electronic devices such as mobile phone, digital camera, PDA and so on are also developing very fast. The demand of long stand-by time of the consumer products keeps increasing. So, low voltage low power design of integrated circuits becomes one of the hot and difficult research areas in both academia and industry. On the other hand, more and more Sigma-Delta ADCs are applied to the portable electronic devices recently, which could offer quite a high resolution at a low cost due to utilizing the oversampling and noise shaping technology. For these reasons, as a good example, the thesis focused the research of low voltage low power mixed-signal IC on Sigma-Delta ADC.
Because of differences between design methods for analog and digital circuits, the recent approaches to low power design of digital and analog circuits were discussed, summarized and organized respectively. The fundamental principles, current technologies and developments on Sigma-Delta ADC were introduced. And the low voltage low power design for analog and digital circuits in it was conducted.
As to the analog part, Sigma-Delta modulator, all kinds of essential and non-ideal factors that are related to the power consumption of modulators were analyzed in the system level. Based on the analysis, it was discussed that how to fix the order for modulators to fulfill the system requirements as well as to achieve the minimum power. In the structure level, a new structure of switched-capacitor integrators was proposed to realize a small coefficient and solve the problem in zero optimization. Compared to the traditional one, this new structure largely reduced the area and power consumed by capacitors. In circuit level, the power consumption in operational amplifiers was analyzed. After analyzing and comparing several classical structures of operational amplifiers, a new structure of class AB/AB was proposed to reduce the power consumption in general operations. A kind of cross-couple load was used to eliminate the CMFB circuit in the first stage to further reduce the power. This thesis also analyzed all kinds of important non-idea factors in Sigma-Delta modulators, and introduced methods to calculate the minimum spec for all modules according to these factors, which means the required minimum power in order to fulfill the system requirements. The validity of research results was verified by system simulation.
As to the digital part, decimation filter, different characteristics under different down-sampling rates were analyzed. Two structure optimization schemes for decimation filters working in different down-sampling rates were presented respectively. As to the low down-sampling rate, three different structures to implement the sinc filter were analyzed and compared, a modified polyphase structure was proposed. Simulation results showed that in comparison with traditional CIC structure, the new structure could save about 36% area and 50% power. The results were also better than the latest reported polyphase structure: about 14% area and 3% power could be saved. As to the high down-sampling rate, the advantage of CIC structure was testified. And the optimization for the decimation structure was brought forward based on the distribution of power dissipation. All work in this part was completed in TSMC 0.18μm technology.
引文
[1] HU, Y., LU, Z., SAWAN, M., "A Low-Voltage 38 mW Sigma-Delta Modulator Dedicated to Wireless Signal Recording Applications," IEEE, ISCAS, Thailand, May 2003.
[2] PELUSO, V., STEYAERT, M., SANSEN,W., "Design of Low-Voltage Low-Power CMOS Delta-Sigma A/D Converters," Kluwer Academic Publishers, Boston, 1999.
[3] RABII, S. and WOOLEY, B. A., "The Design of Low-Voltage, Low-Power Sigma-Delta Modulators," Kluwer Academic Publishers, 1999.
[4] 朱宁、周润德、羊性滋，“CMOS集成电路设计中的功耗优化技术”，清华大学学报自然科学版，1999年，第39卷第5期。
[5] 吴福炜、甘骏人，“系统级CMOS电路的低功耗设计”，微处理机，2002年，第4期。
[6] 张天骐、林孝康、余翔，“SOC系统的低功耗设计”，单片机与嵌入式系统应用，2004年6月。
[7] RAJPUT, S. S. and JAMUAR, S. S., "Low Voltage Analog Circuit Design Techniques," IEEE Press, 2002.
[8] 严晓浪、吴晓波，“低压低功耗模拟集成电路的发展”，微电子学，2004年8月，第34卷第4期。
[9] 邹志革、邹雪城、黄峰，“低压低功耗模拟集成电路设计技术及展望”，微电子学，2006年2月，第36卷第1期。
[10] PARK, S., "Principles of Sigma-Delta Modulation for Analog-to-Digital Converters," Application Report, DSP Operations, Motorola Inc., 1990
[11] 洪志良、曹先国、王晓悦，“18位过采样ZAA／D变换器设计”，半导体学报，1996年11月，第17卷第11期
[12] YEO, K., ROFAIL, S., GOH, W., "CMOS/BiCMOS ULSI: Low Voltage, Low Power," Publishing House of Electronics Industry, 2003.
[13] BOSER, B., and WOOLEY, B., "The Design of Sigma-Delta Modulation Analog-to-Digital Converters," IEEE Journal of Solid-State Circuits, Vol.23, No. 6, pp.1298-1308, December 1988.
[14] JOHNS, D., MARTIN, K., "Analog Integrated Circuit Design," J. Wiley & Sons, 1997.
[15] NORSWORTHY, S. R., SCHREIER, R. and TEMES, G. C., "Delta-Sigma Data Converters Theory, Design, and Simulation," IEEE Press, New York, 1997.
[16] SCHREIER, R. and TEMES, G. C., "Understanding Delta-Sigma Data Converters," IEEE Press, J. Wiley & Sons,
[17] CANDY, J. C., "Decimation for Sigma Delta Modulation," IEEE Transaction on Communication, COM-34(1): 72-76, 1986.
[18] STEYAERT, M., CROLS, J., and GOGAERT, S., "Switched-Opamp, a Technique for Realizing Full CMOS Switched-Capacitor Filters at Very Low Voltages," in Proc. 19th Eur. Solid-State Circuits Conf, pp. 178-181, Sept. 1993.
[19] PELUSO, V., VANCORENLAND, P., MARQUES, A. M., STEYAERT, M., SANSEN, W., "A 900-mV Low-Power ΣΔ A/D Converter with 77-dB Dynamic Range," IEEE Journal of Solid-State Circuits, Vol.33, No. 12, pp.1887-1897, 1998.
[20] AHN, G., CHANG, D., BROWN, M. E., OZAKI, N., YOURA, H., YAMAMURA, K., HAMASHITA, K., TAKASUKA, K., TEMES, G. C., MOON, U., IEEE Journal of Solid-State Circuits, Vol.40, No. 12, pp. 2398-2407, 2005.
[21] SANSEN, W. and PETEGHEM, P., "An Area-Efficient Approach to the Design of Very-Large Time Constants in SC Integrators," IEEE Journal of Solid-State Circuits, Vol. SC-19, No. 5, pp. 772-780, Oct. 1984.
[22] HUANG, Q., "A Novel Technique for the Reduction of Capacitance Spread in High-Q SC Circuits," IEEE Trans. Circuits and Systems, Vol. 36, No. 1, pp. 121-126, Jan. 1989.
[23] NAGARAJ, K., "A Parasitic-Insensitive Area-Efficient Approach to Realizing Very-Large Time Constants in SC Circuits," IEEE Trans. Circuits and Systems, Vol. 36, No. 9, pp. 1210-1216, Sep. 1989.
[24] CANDY, J. C., "Decimation for Sigma Delta Modulation," IEEE Transaction on Communication, Vol. COM-34, No. 1, pp. 72-76, 1986.
[25] ZHU, H., WU, X., and YAN, X., "Low-Power and Hardware Efficient Decimation Filters in Sigma-Delta A/D Converters," IEEE Conference on Electron Devices and Solid-State Circuits, pp. 665-668, December 2005.
[26] FARAG, E. N., YAN, R. and ELMASRY, M. I., "Programmable Power-Efficient Decimation Filter for Software Radios," International Symposium on Low Power Electronics and Design, pp. 68-71, 1997.
[27] ASCARI, L., PIERAZZI, A., MORANDI, C., "Low Power Implementation of a Sigma Delta Decimation Filter for Cardiac Application," IEEE Instrumentation and Measurement Technology Conference, pp. 750-755, May 2001.
[28] ALLEN, P., E., HOLBERG, D., R., "CMOS Analog Circuit Design," Oxford University Press, 2002.
[29] YAO, L., STEYAERT, M., SANSEN, W., "A 1-V 140-uW 88-dB Audio Sigma-Delta Modulator in 90-nm CMOS," IEEE Journal of Solid-State Circuits, Vol. 39, No. 11, pp. 1809-1818, Nov. 2004.
[30] RABII, S., and WOOLEY, B. A., "A 1.8-V Digital-Audio Sigma-Delta Modulator in 0.8-um CMOS," IEEE Journal of Solid-State Circuits, Vol. 32, No. 6, pp. 783-796, Jun. 1997.
[31] CHOKSI, O., and RICHARD, L., "Analysis of Switched-Capacitor Common-Mode Feedback Circuit," IEEE Trans. Circuits and Systems, Vol. 50, No. 12, pp. 906-917, Dec. 2003.
[2] PELUSO, V., STEYAERT, M., SANSEN,W., "Design of Low-Voltage Low-Power CMOS Delta-Sigma A/D Converters," Kluwer Academic Publishers, Boston, 1999.
[3] RABII, S. and WOOLEY, B. A., "The Design of Low-Voltage, Low-Power Sigma-Delta Modulators," Kluwer Academic Publishers, 1999.
[4] 朱宁、周润德、羊性滋，“CMOS集成电路设计中的功耗优化技术”，清华大学学报自然科学版，1999年，第39卷第5期。
[5] 吴福炜、甘骏人，“系统级CMOS电路的低功耗设计”，微处理机，2002年，第4期。
[6] 张天骐、林孝康、余翔，“SOC系统的低功耗设计”，单片机与嵌入式系统应用，2004年6月。
[7] RAJPUT, S. S. and JAMUAR, S. S., "Low Voltage Analog Circuit Design Techniques," IEEE Press, 2002.
[8] 严晓浪、吴晓波，“低压低功耗模拟集成电路的发展”，微电子学，2004年8月，第34卷第4期。
[9] 邹志革、邹雪城、黄峰，“低压低功耗模拟集成电路设计技术及展望”，微电子学，2006年2月，第36卷第1期。
[10] PARK, S., "Principles of Sigma-Delta Modulation for Analog-to-Digital Converters," Application Report, DSP Operations, Motorola Inc., 1990
[11] 洪志良、曹先国、王晓悦，“18位过采样ZAA／D变换器设计”，半导体学报，1996年11月，第17卷第11期
[12] YEO, K., ROFAIL, S., GOH, W., "CMOS/BiCMOS ULSI: Low Voltage, Low Power," Publishing House of Electronics Industry, 2003.
[13] BOSER, B., and WOOLEY, B., "The Design of Sigma-Delta Modulation Analog-to-Digital Converters," IEEE Journal of Solid-State Circuits, Vol.23, No. 6, pp.1298-1308, December 1988.
[14] JOHNS, D., MARTIN, K., "Analog Integrated Circuit Design," J. Wiley & Sons, 1997.
[15] NORSWORTHY, S. R., SCHREIER, R. and TEMES, G. C., "Delta-Sigma Data Converters Theory, Design, and Simulation," IEEE Press, New York, 1997.
[16] SCHREIER, R. and TEMES, G. C., "Understanding Delta-Sigma Data Converters," IEEE Press, J. Wiley & Sons,
[17] CANDY, J. C., "Decimation for Sigma Delta Modulation," IEEE Transaction on Communication, COM-34(1): 72-76, 1986.
[18] STEYAERT, M., CROLS, J., and GOGAERT, S., "Switched-Opamp, a Technique for Realizing Full CMOS Switched-Capacitor Filters at Very Low Voltages," in Proc. 19th Eur. Solid-State Circuits Conf, pp. 178-181, Sept. 1993.
[19] PELUSO, V., VANCORENLAND, P., MARQUES, A. M., STEYAERT, M., SANSEN, W., "A 900-mV Low-Power ΣΔ A/D Converter with 77-dB Dynamic Range," IEEE Journal of Solid-State Circuits, Vol.33, No. 12, pp.1887-1897, 1998.
[20] AHN, G., CHANG, D., BROWN, M. E., OZAKI, N., YOURA, H., YAMAMURA, K., HAMASHITA, K., TAKASUKA, K., TEMES, G. C., MOON, U., IEEE Journal of Solid-State Circuits, Vol.40, No. 12, pp. 2398-2407, 2005.
[21] SANSEN, W. and PETEGHEM, P., "An Area-Efficient Approach to the Design of Very-Large Time Constants in SC Integrators," IEEE Journal of Solid-State Circuits, Vol. SC-19, No. 5, pp. 772-780, Oct. 1984.
[22] HUANG, Q., "A Novel Technique for the Reduction of Capacitance Spread in High-Q SC Circuits," IEEE Trans. Circuits and Systems, Vol. 36, No. 1, pp. 121-126, Jan. 1989.
[23] NAGARAJ, K., "A Parasitic-Insensitive Area-Efficient Approach to Realizing Very-Large Time Constants in SC Circuits," IEEE Trans. Circuits and Systems, Vol. 36, No. 9, pp. 1210-1216, Sep. 1989.
[24] CANDY, J. C., "Decimation for Sigma Delta Modulation," IEEE Transaction on Communication, Vol. COM-34, No. 1, pp. 72-76, 1986.
[25] ZHU, H., WU, X., and YAN, X., "Low-Power and Hardware Efficient Decimation Filters in Sigma-Delta A/D Converters," IEEE Conference on Electron Devices and Solid-State Circuits, pp. 665-668, December 2005.
[26] FARAG, E. N., YAN, R. and ELMASRY, M. I., "Programmable Power-Efficient Decimation Filter for Software Radios," International Symposium on Low Power Electronics and Design, pp. 68-71, 1997.
[27] ASCARI, L., PIERAZZI, A., MORANDI, C., "Low Power Implementation of a Sigma Delta Decimation Filter for Cardiac Application," IEEE Instrumentation and Measurement Technology Conference, pp. 750-755, May 2001.
[28] ALLEN, P., E., HOLBERG, D., R., "CMOS Analog Circuit Design," Oxford University Press, 2002.
[29] YAO, L., STEYAERT, M., SANSEN, W., "A 1-V 140-uW 88-dB Audio Sigma-Delta Modulator in 90-nm CMOS," IEEE Journal of Solid-State Circuits, Vol. 39, No. 11, pp. 1809-1818, Nov. 2004.
[30] RABII, S., and WOOLEY, B. A., "A 1.8-V Digital-Audio Sigma-Delta Modulator in 0.8-um CMOS," IEEE Journal of Solid-State Circuits, Vol. 32, No. 6, pp. 783-796, Jun. 1997.
[31] CHOKSI, O., and RICHARD, L., "Analysis of Switched-Capacitor Common-Mode Feedback Circuit," IEEE Trans. Circuits and Systems, Vol. 50, No. 12, pp. 906-917, Dec. 2003.