无人机视频信号处理芯片的研究与设计
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摘要
随着无人机系统的不断发展,视频信号处理芯片作为无人机遥感系统中重要组成部分,受到国家越来越高的重视。本论文课题来源于中国电子科技集团58研究所承担的国家重点项目,无人机遥感系统中视频信号处理芯片的设计。
由于无人机常工作在恶劣环境下,遥感系统采集的信号很不稳定,故设计该芯片对遥感系统中采集的十路视频信号进行处理,自动检测并分离出其中信号强度最大一路,并将该信号转换为数字信号送入后端系统,提高了无人机在恶劣环境下的工作能力。视频信号处理芯片由模/数混合信号处理电路JS71186和特殊门限电平比较器JS988两部分组成。其中JS71186包括模拟部分JS71186A和数字部分JS71186D。JS71186A由选大网络、时钟脉冲产生电路和比较器三大部分组成。选大网络通过‘或运算’求出十路脉冲的合信号,该合信号每个周期均为十路采样信号中最大的一路,并将该合信号送入下级JS988处理。为了保证时钟的一致性,时钟脉冲产生电路产生两路时钟脉冲,可分别利用两路时钟脉冲在数字电路内部生成数字时钟信号。同时设计了齐纳二极管低温漂电压基准,提高了时钟脉冲产生电路输入端的温度系数匹配性,解决了时钟脉冲产生电路高温失效问题。在JS71186D中重点设计了高电源抑制比电压基准源,为了降低功耗和抑制噪声,采用了共源共栅电流镜和线性稳压负反馈结构,并在版图设计中采用温度系数微调设计方法,获得了高电源抑制比、低温度系数的电压基准。针对输入信号峰值随机变化的特点,在特殊门限电平比较器JS988的设计中,采用射极耦合电流开关控制采样电容使比较器上门限电平随输入信号峰值变化而变化,其变化范围可调。完成了芯片各部分的版图设计,最后进行了芯片的版图与电路图同一性验证。
芯片设计中,JS71186A和JS988采用双极型工艺制造,JS71186D采用CMOS工艺制造,最后三块芯片采用陶瓷封装技术混合封装成一块芯片。经流片测试,芯片可辨别脉冲脉宽为50ns以上、脉冲幅度为0V～4.5V的输入信号,对输入脉冲信号的最小脉冲幅度辨别率可达100mV,可在-55摄氏度到125摄氏度的温度范围工作。芯片功耗约为2.1W。
Along with unmanned aerial vehicles system unceasing develope, the video signal processing chip does for an important part of unmanned aerial vehicles, gets more and more attention from the national. The video signal processing is the most important part of the remote sensing system, The sensitivity and reliability of the video signal processing chip has decided the overall system performance.
The video signal processing chip is mainly composed by JS71186 and the special threshold level comparator JS988 two chips. JS71186 is composed by analog port JS71186A and digital port JS71187D. JS71186 include three port Choosing biggest network, the clock pulse produce, and comparaotor. Choosing biggest network can choose the biggest signal in ten video signals. We discuss and reasch the zener voltage in the clock pulse produce design. For twice tape out, JS71186A make a remodification to solver the problem that chip diswork at higt temperature, and promote the produce success rate. JS71186D include clock deal module, coding module, data temporary memory, high PSRR voltage reference. This reference is using cascode structure and linearity steady structure, and using small temperature to adjust in layout design. The reference has high PSRR and low temperature characteristic. Design the JS988 with E polar coupling to control the sample capacitance.The VH can change with the input signal. After the thesis made the chip layout and done lvs.
Because design has used the biopolar and the CMOS two kind of process, therefore each part used the mix seal technology to complete one chip. The chip design has be amended several times in order to solve the problem happened in test, The chips design used the biopolar and the CMOS process, the chip uses the ceramic seal technology. The characteristic of the chip processing signal: the least pulse width is 50ns, the biggest signal is 4.5V, the smallest pulse which can be recognized is smaller than 100mV,the operating temperature can rang from -55 celsius to 125 celsius. Chip power consumption is about 2.1W.
由于无人机常工作在恶劣环境下,遥感系统采集的信号很不稳定,故设计该芯片对遥感系统中采集的十路视频信号进行处理,自动检测并分离出其中信号强度最大一路,并将该信号转换为数字信号送入后端系统,提高了无人机在恶劣环境下的工作能力。视频信号处理芯片由模/数混合信号处理电路JS71186和特殊门限电平比较器JS988两部分组成。其中JS71186包括模拟部分JS71186A和数字部分JS71186D。JS71186A由选大网络、时钟脉冲产生电路和比较器三大部分组成。选大网络通过‘或运算’求出十路脉冲的合信号,该合信号每个周期均为十路采样信号中最大的一路,并将该合信号送入下级JS988处理。为了保证时钟的一致性,时钟脉冲产生电路产生两路时钟脉冲,可分别利用两路时钟脉冲在数字电路内部生成数字时钟信号。同时设计了齐纳二极管低温漂电压基准,提高了时钟脉冲产生电路输入端的温度系数匹配性,解决了时钟脉冲产生电路高温失效问题。在JS71186D中重点设计了高电源抑制比电压基准源,为了降低功耗和抑制噪声,采用了共源共栅电流镜和线性稳压负反馈结构,并在版图设计中采用温度系数微调设计方法,获得了高电源抑制比、低温度系数的电压基准。针对输入信号峰值随机变化的特点,在特殊门限电平比较器JS988的设计中,采用射极耦合电流开关控制采样电容使比较器上门限电平随输入信号峰值变化而变化,其变化范围可调。完成了芯片各部分的版图设计,最后进行了芯片的版图与电路图同一性验证。
芯片设计中,JS71186A和JS988采用双极型工艺制造,JS71186D采用CMOS工艺制造,最后三块芯片采用陶瓷封装技术混合封装成一块芯片。经流片测试,芯片可辨别脉冲脉宽为50ns以上、脉冲幅度为0V～4.5V的输入信号,对输入脉冲信号的最小脉冲幅度辨别率可达100mV,可在-55摄氏度到125摄氏度的温度范围工作。芯片功耗约为2.1W。
Along with unmanned aerial vehicles system unceasing develope, the video signal processing chip does for an important part of unmanned aerial vehicles, gets more and more attention from the national. The video signal processing is the most important part of the remote sensing system, The sensitivity and reliability of the video signal processing chip has decided the overall system performance.
The video signal processing chip is mainly composed by JS71186 and the special threshold level comparator JS988 two chips. JS71186 is composed by analog port JS71186A and digital port JS71187D. JS71186 include three port Choosing biggest network, the clock pulse produce, and comparaotor. Choosing biggest network can choose the biggest signal in ten video signals. We discuss and reasch the zener voltage in the clock pulse produce design. For twice tape out, JS71186A make a remodification to solver the problem that chip diswork at higt temperature, and promote the produce success rate. JS71186D include clock deal module, coding module, data temporary memory, high PSRR voltage reference. This reference is using cascode structure and linearity steady structure, and using small temperature to adjust in layout design. The reference has high PSRR and low temperature characteristic. Design the JS988 with E polar coupling to control the sample capacitance.The VH can change with the input signal. After the thesis made the chip layout and done lvs.
Because design has used the biopolar and the CMOS two kind of process, therefore each part used the mix seal technology to complete one chip. The chip design has be amended several times in order to solve the problem happened in test, The chips design used the biopolar and the CMOS process, the chip uses the ceramic seal technology. The characteristic of the chip processing signal: the least pulse width is 50ns, the biggest signal is 4.5V, the smallest pulse which can be recognized is smaller than 100mV,the operating temperature can rang from -55 celsius to 125 celsius. Chip power consumption is about 2.1W.
引文
[1] Shyy w, Berg M, Ljungqvist D. Flapping and flexible wings for biological and micro air vehicle. Progress in Aerospace Sciences, 1999,(35): 455-505
[2] Lennon Andy.R/C Model Aircraft Design Practical Techniques for Building better Models. London:Air Age Inc, 1996:130-132
[3] 龚喜盈, 周洲. 无人战斗机作战效能分析. 飞行力学, 2006, 24 (3): 30-32
[4] SUI Jie, LIN Zong-jian, CUI Hong-xia. Low Altitude Unmanned Aircraft Remote Sensing system. Remote Sensing Information, 2003, (1):25-27.
[5] 孙静. 微型无人机. 军民两用技术与产品, 2002, (12): 10
[6] 罗 卫 兵 , 王 永 生 . 无 人 机 平 台 的 超 视 距 多 链 路 中 继 . 遥 测 遥控,2003,24(2):672-675
[7] Thomas M. Thomas, Gerard C.MMeijer, GuiJie Wang. Temperature Sensors and Voltage References Implemented in CMOS Technology. IEEE Sensor Journal, 2001, 1(3):225-234
[8] Tomas. Joint Unmanned Systems Common Control. Porman Unmanned Systems Office NSWC Panama City, 2004, (2):75-79
[9] Slobodan Petkovic. Cloud SeedingTechnique Based on Unmanned Aerial Vehicle System. In: Eighth WMO Scientific Confer-ence on Weather Modification, 2003:467-470,549
[10] 杨邦朝,张经国.多芯片组件(MCM)技术及应用. 成都:电子科技大学出版社,2001:98-100
[11] 胡先进. 微电子封装与电子整机的微小型化进程. 电子与封装,2006,6(12):1-3
[12] Ma T P. Making silicon nitride film a viable gate die-lectric. IEEE Trans Elec Dev, 1998, 5(3): 680-690
[13] 严雪萍. MEMS 器件的封装材料与封装工艺. 半导体技术, 2006, 31(13): 900-903
[14] David J. Allstot. Precision Variable-Supply CMOS Comparator. IEEE Solid-state Circuits, 1982, 17(9): 87-88
[15] Behzad Razvi, Bruce A. Wooley. Design Techniques for High-Speed, High- Resolution Comparators, IEEE. Solid-State Circuits, 1992, 27(12): 314-315
[16] William C. Slemmer. High-Speed Low-Power Strobed Comparator. IEEE Solid-State Circuits, 1970, 5(10): 54-55
[17] 爱伦, 霍尔博格. CMOS 模拟集成电路设计. 北京:电子工业出版社, 2005:359-356
[18] Fernandes J R. Asymmetric latches and nonideal performance of parallel ADCs. In: Electrotechnical Conference, Proceedings of 7th Mediterranean, 1994:12-14
[19] James H Atherton, H Thomas Simmonds. An Offset Reduction Technique For Use with CMOS Integrated Comparators and Amplifiers. IEEE Journal of Solid-State Circuits, 1992, 27(8): 1168-1175
[20] Alan Hastings. The Art of Analog Layout. 北京 :清华大学出版社 , 2004: 334-335
[21] Gray P R, Meyer R G. Analysis and Design of Analog Integrated Circuits. New York:John Wiley & Sons, 2001:299-327
[22] 拉扎维. 模拟 CMOS 集成电路设计. 西安:交通大学出版社, 2003:309-312
[23] You F, Embabi S H K, Duque-Carrillo J F. An Improved TailCurrent Soure For Low Voltage Application. IEEE Solid-State Circuits, 1997,(32): 573-583
[24] Vincence V C, Galup-Montoro C and Schneider M C. A High Swing MOS Cascode Bias Circuit. IEEE Transactions on Circuits and Systems, 2000, 47(11): 318-31
[25] 金国峰. 电压基准源的合理选择. 电测与仪表, 2001, 38(424): 141-142
[26] 刘涛, 徐志伟, 程君侠. 一种高电源抑制比 CMOS 能隙基准电压源. 微电子学, 1999, (29): 128-131
[27] Tham K, Nagaraj K. A low supply voltage high PSRR voltage reference in CMOS process. IEEE Solid-State Circuitd, 1995, 30(5): 586-590
[28] 朱樟明, 杨银堂, 刘帘曦. 一种高性能 CMOS 带隙电压基准源设计. 半导体学报,2004,(5):47-49
[29] B. S. Song, P. R. Gray. A Precision Curvature-Compensated CMOS Bandgap Reference. IEEE Journal of Solid-State Circuits, 1983,18(11): 634-643
[30] Teresa Serrano Gotarredona, Bernabe Linares Barranco, Andreas G Andreou.Very wide range tunable CMOS/Bipolar current mirror with voltage calmped. IEEE Transactions Oncircuiuts and Systems, 1999, 46 (11): 1398-1402
[31] Daubert S J, Vallancourt D, Tsividis Y P. Current Copier Cells. Electronics Letters, 1988, 13(3): 24-25
[32] J Sarao, Z J Wang, Y L Wu, H L Kwok. An Improved Regulated Cascade Current Mirror. IEEE Solid-State Circuits, 2002, 37(4): 307-312
[33] M T Belaroussi, D Benamrouche, Y harabi. Evaluation and Comparison of BiCMOS and MOS Current Mirrors. Microelectonic Journal, 1998, 29: 895-900
[34] 曾健平, 邹韦华, 谢海情. 一种新型高输出阻抗, 高电流匹配精度电流镜的设计. 电子器件, 2007, 30(1): 126-128
[35] 吕江平. 集成电路中电阻的设计. 集成电路通讯, 2005, 23(3): 14-17
[36] Beeftink F, van Genderen A J, van der Meijs N P. Accurate and efficient layout-to-circuit extraction forhigh-speed MOS and bipolar/ Bi CMOS integrated circuits. IEEE Solid-State Circuits, 1995, 30(6): 360 -365
[37] Christopher Saint, Judy Saint. The design of ic layout. 北京:清华大学出版社,2006:110-112
[38] 秦世才, 贾香鸾. 现代模拟集成电子学. 天津:科学技术出版社, 2003:234-235
[39] 张颖, 潘亮. 芯片版图面积的设计优化. 中国集成电路, 2006, 15( 7): 57-60
[40] 薛耀国. 硅栅 CMOS 电路版图设计规则检查全面性探讨. 微电子学与计算机, 1999, (4): 4-7
[41] SHI Lin-chu. Module Recognition and its application to LVS of ASIC, In: the forth International Conference on ASIC. 2001, 13-15
[42] 冯玉波, 黄令仪, 张德骏. VLSI 全定制版图分级 LVS 验证的研究. 集成电路应用, 2004, (2): 44-47
[43] 石春琦, 吴金. LVS 版图验证方法的研究. 电子器件, 2002, 25(2):165-169
[2] Lennon Andy.R/C Model Aircraft Design Practical Techniques for Building better Models. London:Air Age Inc, 1996:130-132
[3] 龚喜盈, 周洲. 无人战斗机作战效能分析. 飞行力学, 2006, 24 (3): 30-32
[4] SUI Jie, LIN Zong-jian, CUI Hong-xia. Low Altitude Unmanned Aircraft Remote Sensing system. Remote Sensing Information, 2003, (1):25-27.
[5] 孙静. 微型无人机. 军民两用技术与产品, 2002, (12): 10
[6] 罗 卫 兵 , 王 永 生 . 无 人 机 平 台 的 超 视 距 多 链 路 中 继 . 遥 测 遥控,2003,24(2):672-675
[7] Thomas M. Thomas, Gerard C.MMeijer, GuiJie Wang. Temperature Sensors and Voltage References Implemented in CMOS Technology. IEEE Sensor Journal, 2001, 1(3):225-234
[8] Tomas. Joint Unmanned Systems Common Control. Porman Unmanned Systems Office NSWC Panama City, 2004, (2):75-79
[9] Slobodan Petkovic. Cloud SeedingTechnique Based on Unmanned Aerial Vehicle System. In: Eighth WMO Scientific Confer-ence on Weather Modification, 2003:467-470,549
[10] 杨邦朝,张经国.多芯片组件(MCM)技术及应用. 成都:电子科技大学出版社,2001:98-100
[11] 胡先进. 微电子封装与电子整机的微小型化进程. 电子与封装,2006,6(12):1-3
[12] Ma T P. Making silicon nitride film a viable gate die-lectric. IEEE Trans Elec Dev, 1998, 5(3): 680-690
[13] 严雪萍. MEMS 器件的封装材料与封装工艺. 半导体技术, 2006, 31(13): 900-903
[14] David J. Allstot. Precision Variable-Supply CMOS Comparator. IEEE Solid-state Circuits, 1982, 17(9): 87-88
[15] Behzad Razvi, Bruce A. Wooley. Design Techniques for High-Speed, High- Resolution Comparators, IEEE. Solid-State Circuits, 1992, 27(12): 314-315
[16] William C. Slemmer. High-Speed Low-Power Strobed Comparator. IEEE Solid-State Circuits, 1970, 5(10): 54-55
[17] 爱伦, 霍尔博格. CMOS 模拟集成电路设计. 北京:电子工业出版社, 2005:359-356
[18] Fernandes J R. Asymmetric latches and nonideal performance of parallel ADCs. In: Electrotechnical Conference, Proceedings of 7th Mediterranean, 1994:12-14
[19] James H Atherton, H Thomas Simmonds. An Offset Reduction Technique For Use with CMOS Integrated Comparators and Amplifiers. IEEE Journal of Solid-State Circuits, 1992, 27(8): 1168-1175
[20] Alan Hastings. The Art of Analog Layout. 北京 :清华大学出版社 , 2004: 334-335
[21] Gray P R, Meyer R G. Analysis and Design of Analog Integrated Circuits. New York:John Wiley & Sons, 2001:299-327
[22] 拉扎维. 模拟 CMOS 集成电路设计. 西安:交通大学出版社, 2003:309-312
[23] You F, Embabi S H K, Duque-Carrillo J F. An Improved TailCurrent Soure For Low Voltage Application. IEEE Solid-State Circuits, 1997,(32): 573-583
[24] Vincence V C, Galup-Montoro C and Schneider M C. A High Swing MOS Cascode Bias Circuit. IEEE Transactions on Circuits and Systems, 2000, 47(11): 318-31
[25] 金国峰. 电压基准源的合理选择. 电测与仪表, 2001, 38(424): 141-142
[26] 刘涛, 徐志伟, 程君侠. 一种高电源抑制比 CMOS 能隙基准电压源. 微电子学, 1999, (29): 128-131
[27] Tham K, Nagaraj K. A low supply voltage high PSRR voltage reference in CMOS process. IEEE Solid-State Circuitd, 1995, 30(5): 586-590
[28] 朱樟明, 杨银堂, 刘帘曦. 一种高性能 CMOS 带隙电压基准源设计. 半导体学报,2004,(5):47-49
[29] B. S. Song, P. R. Gray. A Precision Curvature-Compensated CMOS Bandgap Reference. IEEE Journal of Solid-State Circuits, 1983,18(11): 634-643
[30] Teresa Serrano Gotarredona, Bernabe Linares Barranco, Andreas G Andreou.Very wide range tunable CMOS/Bipolar current mirror with voltage calmped. IEEE Transactions Oncircuiuts and Systems, 1999, 46 (11): 1398-1402
[31] Daubert S J, Vallancourt D, Tsividis Y P. Current Copier Cells. Electronics Letters, 1988, 13(3): 24-25
[32] J Sarao, Z J Wang, Y L Wu, H L Kwok. An Improved Regulated Cascade Current Mirror. IEEE Solid-State Circuits, 2002, 37(4): 307-312
[33] M T Belaroussi, D Benamrouche, Y harabi. Evaluation and Comparison of BiCMOS and MOS Current Mirrors. Microelectonic Journal, 1998, 29: 895-900
[34] 曾健平, 邹韦华, 谢海情. 一种新型高输出阻抗, 高电流匹配精度电流镜的设计. 电子器件, 2007, 30(1): 126-128
[35] 吕江平. 集成电路中电阻的设计. 集成电路通讯, 2005, 23(3): 14-17
[36] Beeftink F, van Genderen A J, van der Meijs N P. Accurate and efficient layout-to-circuit extraction forhigh-speed MOS and bipolar/ Bi CMOS integrated circuits. IEEE Solid-State Circuits, 1995, 30(6): 360 -365
[37] Christopher Saint, Judy Saint. The design of ic layout. 北京:清华大学出版社,2006:110-112
[38] 秦世才, 贾香鸾. 现代模拟集成电子学. 天津:科学技术出版社, 2003:234-235
[39] 张颖, 潘亮. 芯片版图面积的设计优化. 中国集成电路, 2006, 15( 7): 57-60
[40] 薛耀国. 硅栅 CMOS 电路版图设计规则检查全面性探讨. 微电子学与计算机, 1999, (4): 4-7
[41] SHI Lin-chu. Module Recognition and its application to LVS of ASIC, In: the forth International Conference on ASIC. 2001, 13-15
[42] 冯玉波, 黄令仪, 张德骏. VLSI 全定制版图分级 LVS 验证的研究. 集成电路应用, 2004, (2): 44-47
[43] 石春琦, 吴金. LVS 版图验证方法的研究. 电子器件, 2002, 25(2):165-169