基于FPGA的SAR实时成像实现技术研究
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摘要
合成孔径雷达是一种高分辨力的成像雷达,具有全天时、全天候、远距离的工作能力。随着系统向大带宽、高分辨率、信号处理实时化的方向迈进,回波的数据率越来越高,因此对实时成像处理系统提出了更高的要求。SAR成像运算量主要集中在距离向和方位向脉压处理上,以前经常采用多片高速DSP并联的方式实现,目前已有大量的工程应用。但是近几年随着可编程器件的发展使得FPGA成为比DSP更优越的数字信号处理方式。较DSP而言,FPGA具有更多的硬件资源可以利用,处理速度更快,灵活性更好。
本文主要从实时成像处理技术的应用角度出发,对采用RD算法的实时成像处理系统的FPGA实现方法做了一定的研究,主要工作如下:
1.根据系统指标要求,确定设计方案,采用单片高密度FPGA芯片实现距离向和方位向两次脉压处理,实现转置存储控制,并实现各种接口协议;采用两片高速DSP芯片实现自聚焦算法。
2.根据系统方案,完成系统硬件电路的设计,主要包括各单元电路设计和芯片选型。
3.完成系统的FPGA程序开发与调试,主要包括FFT,IFFT,CMUL和转置存储控制等模块,在此基础上,重点介绍了一种基于DDR SDRAM的行写行读高效转置存储算法,在采用该算法进行转置存储操作时,读写两端的速度相匹配,满足流水线操作要求,提高了整个系统的实时性。最后介绍了采用CORDIC算法实现复图像求模运算的方法,分析了算法的硬件实现结构,并给出了基于FPGA的实现方法及仿真结果。
4.对系统部分功能进行测试,达到项目指标要求,并得到若干幅实时成像图。
Synthetic Aperture Radar (SAR) is a kind of high-resolution imaging Radar. Using SAR we can obtain high-resolution Radar images under all weather, day and night, and long distance conditions. With the system towards the large bandwidth, high-resolution, signal processing real-time direction, SAR raw signal has a high data rate, so a higher demand is raised to real-time imaging system. SAR imaging computing capacity mainly concentrated in the pulse compression in both range and azimuth directions. Often multi-chip high-speed DSPs are used to implement in parallel mode, and there are many engineering applications. But in recent years, with the development of programmable devices, the FPGAs become better than the DSPs in digital signal processing. Contrast to the DSPs , FPGAs has more hardware resources, and can be used to deal with faster and better flexibility.
This thesis studys on the implementation of real-time RD algorithm based on FPGA from the point of the application of real-time SAR imaging system.The main job is as follows:
1. According to the requirement of the system, the design is determined. A monolithic high-density FPGA is used to process the pulse compression of both the distance and azimuth directions, implement the control of corner turn memory(CTM), and a variety of interface protocol; Two high-speed DSPs are used to implement the Autofocus algorithm.
2. According to the system design, the hardware design is implemented, including the circuit design and chip selections.
3. The FPGA’s development and debugging are implemented, including FFT, IFFT, CMUL and control of CTM. Based on this, Implementation of a high efficient corner turn memory arithmetic with writing and reading by row based on DDR SDRAM is introduced. When using CTM with this algorithm , the speed of reading and writing matches and meets the requirement of pipelined operation. Finally a method of model implementation for complex image based on CORDIC algorithm is introduced. The algorithm's hardware implementation structure is analysed, and implementation methodology and simulation results are given.
4. System’s debugging is implemented, the function of the system is verified, system’s requirement is satisfied, and a number of pieces of real-time imaging is produced.
本文主要从实时成像处理技术的应用角度出发,对采用RD算法的实时成像处理系统的FPGA实现方法做了一定的研究,主要工作如下:
1.根据系统指标要求,确定设计方案,采用单片高密度FPGA芯片实现距离向和方位向两次脉压处理,实现转置存储控制,并实现各种接口协议;采用两片高速DSP芯片实现自聚焦算法。
2.根据系统方案,完成系统硬件电路的设计,主要包括各单元电路设计和芯片选型。
3.完成系统的FPGA程序开发与调试,主要包括FFT,IFFT,CMUL和转置存储控制等模块,在此基础上,重点介绍了一种基于DDR SDRAM的行写行读高效转置存储算法,在采用该算法进行转置存储操作时,读写两端的速度相匹配,满足流水线操作要求,提高了整个系统的实时性。最后介绍了采用CORDIC算法实现复图像求模运算的方法,分析了算法的硬件实现结构,并给出了基于FPGA的实现方法及仿真结果。
4.对系统部分功能进行测试,达到项目指标要求,并得到若干幅实时成像图。
Synthetic Aperture Radar (SAR) is a kind of high-resolution imaging Radar. Using SAR we can obtain high-resolution Radar images under all weather, day and night, and long distance conditions. With the system towards the large bandwidth, high-resolution, signal processing real-time direction, SAR raw signal has a high data rate, so a higher demand is raised to real-time imaging system. SAR imaging computing capacity mainly concentrated in the pulse compression in both range and azimuth directions. Often multi-chip high-speed DSPs are used to implement in parallel mode, and there are many engineering applications. But in recent years, with the development of programmable devices, the FPGAs become better than the DSPs in digital signal processing. Contrast to the DSPs , FPGAs has more hardware resources, and can be used to deal with faster and better flexibility.
This thesis studys on the implementation of real-time RD algorithm based on FPGA from the point of the application of real-time SAR imaging system.The main job is as follows:
1. According to the requirement of the system, the design is determined. A monolithic high-density FPGA is used to process the pulse compression of both the distance and azimuth directions, implement the control of corner turn memory(CTM), and a variety of interface protocol; Two high-speed DSPs are used to implement the Autofocus algorithm.
2. According to the system design, the hardware design is implemented, including the circuit design and chip selections.
3. The FPGA’s development and debugging are implemented, including FFT, IFFT, CMUL and control of CTM. Based on this, Implementation of a high efficient corner turn memory arithmetic with writing and reading by row based on DDR SDRAM is introduced. When using CTM with this algorithm , the speed of reading and writing matches and meets the requirement of pipelined operation. Finally a method of model implementation for complex image based on CORDIC algorithm is introduced. The algorithm's hardware implementation structure is analysed, and implementation methodology and simulation results are given.
4. System’s debugging is implemented, the function of the system is verified, system’s requirement is satisfied, and a number of pieces of real-time imaging is produced.
引文
[1]张澄波.综合孔径雷达原理-系统分析与应用.北京:科学出版社, 1989
[2]向敬成,张明友.雷达系统.成都:电子科技大学出版社, 1997
[3] Donald R. Wehner, High Resolution Radar. Artech House, 1987
[4]刘永坦.雷达成像技术.哈尔滨:哈尔滨工业大学出版社, 1999
[5]保铮,邢孟道,王彤.雷达成像技术.北京:电子工业出版社, 2005
[6]皮亦鸣,杨建宇,付毓生,杨晓波.合成孔径雷达成像原理.成都:电子科技大学出版社, 2007
[7]李海英,杨汝良.去斜率线性调频合成孔径雷达成像研究.现代雷达, 2003
[8]张德峰.高速DSP板的开发及其在合成孔径雷达实时信号处理中的应用研究.中科院电子所博士学位论文, 2001
[9]陆朋.合成孔径雷达实时成像技术研究.中科院电子所硕士学位论文, 2003
[10]肖欣. SAR实时处理机的FPGA实现.电子科技大学硕士学位论文, 2004
[11]李明.基于Virtex_Pro系列FPGA的SAR实时成像处理器中FFT的硬件实现.中科院电子所硕士学位论文, 2006
[12] Uwe Meyer_Bawese. Digital Signal Process with Field Programmable Gate Arrays.北京:清华大学出版社, 2003
[13] Analog Device Corporation. AD9230 Data Sheet. 2007
[14] Analog Device Corporation. AD8138 Data Sheet. 2006
[15] Altera Corporation. Stratix II Device Handbook. 2005
[16] Analog Device Corporation. ADSP-TS202 TigerSHARC Processor Hardware Reference. 2006
[17] Micron Corporation. MT48LC4M32B Data Sheet. 2001
[18] Cypress Corporation. CY2309 Data Sheet. 1999
[19] Altera Corporation. Megacore Core User Guide. 2008
[20] Michael D. Ciletti. Advanced Digital Design with the Verilog HDL. Publishing House of Electronics Industry. 2004
[21]卢世祥. SAR实时处理器预处理和转置存储技术的研究与实现.中国科学院电子学研究所硕士学位论文, 2004
[22]刘宇,杨汝良.合成孔径雷达实时转置存储的实现.电子与信息学报, 2003
[23]王量,皮亦明.基于FPGA的实时SAR成像系统转置存储的实现.中国通信学会第五届学术年会论文集, 2008
[24] S Panchanathan. Universal architecture for matrix transposition. IEE Proceedings-E, 1992
[25] Micron Corporation. MT46V32M16 Data Sheet. 2000
[26]陈昊,孙志刚,卢泽新. DDR SDRAM控制器的设计与实现.微计算机应用, 2007
[27]张磊,吴晖. WISHBONE总线协议下DDR存储控制器设计.微电子学与计算机, 2004
[28] Ray Andraka. A survey of CORDIC algorithms fo FPGA based computers. FPGA 98 Monterey, 1998
[29]雷元武,周杰.并行CORDIC算法的研究及FPGA实现.计算机工程与科学, 2008
[30]田耘,徐文波,张延伟.无线通信FPGA设计.北京:电子工业出版社, 2008
[2]向敬成,张明友.雷达系统.成都:电子科技大学出版社, 1997
[3] Donald R. Wehner, High Resolution Radar. Artech House, 1987
[4]刘永坦.雷达成像技术.哈尔滨:哈尔滨工业大学出版社, 1999
[5]保铮,邢孟道,王彤.雷达成像技术.北京:电子工业出版社, 2005
[6]皮亦鸣,杨建宇,付毓生,杨晓波.合成孔径雷达成像原理.成都:电子科技大学出版社, 2007
[7]李海英,杨汝良.去斜率线性调频合成孔径雷达成像研究.现代雷达, 2003
[8]张德峰.高速DSP板的开发及其在合成孔径雷达实时信号处理中的应用研究.中科院电子所博士学位论文, 2001
[9]陆朋.合成孔径雷达实时成像技术研究.中科院电子所硕士学位论文, 2003
[10]肖欣. SAR实时处理机的FPGA实现.电子科技大学硕士学位论文, 2004
[11]李明.基于Virtex_Pro系列FPGA的SAR实时成像处理器中FFT的硬件实现.中科院电子所硕士学位论文, 2006
[12] Uwe Meyer_Bawese. Digital Signal Process with Field Programmable Gate Arrays.北京:清华大学出版社, 2003
[13] Analog Device Corporation. AD9230 Data Sheet. 2007
[14] Analog Device Corporation. AD8138 Data Sheet. 2006
[15] Altera Corporation. Stratix II Device Handbook. 2005
[16] Analog Device Corporation. ADSP-TS202 TigerSHARC Processor Hardware Reference. 2006
[17] Micron Corporation. MT48LC4M32B Data Sheet. 2001
[18] Cypress Corporation. CY2309 Data Sheet. 1999
[19] Altera Corporation. Megacore Core User Guide. 2008
[20] Michael D. Ciletti. Advanced Digital Design with the Verilog HDL. Publishing House of Electronics Industry. 2004
[21]卢世祥. SAR实时处理器预处理和转置存储技术的研究与实现.中国科学院电子学研究所硕士学位论文, 2004
[22]刘宇,杨汝良.合成孔径雷达实时转置存储的实现.电子与信息学报, 2003
[23]王量,皮亦明.基于FPGA的实时SAR成像系统转置存储的实现.中国通信学会第五届学术年会论文集, 2008
[24] S Panchanathan. Universal architecture for matrix transposition. IEE Proceedings-E, 1992
[25] Micron Corporation. MT46V32M16 Data Sheet. 2000
[26]陈昊,孙志刚,卢泽新. DDR SDRAM控制器的设计与实现.微计算机应用, 2007
[27]张磊,吴晖. WISHBONE总线协议下DDR存储控制器设计.微电子学与计算机, 2004
[28] Ray Andraka. A survey of CORDIC algorithms fo FPGA based computers. FPGA 98 Monterey, 1998
[29]雷元武,周杰.并行CORDIC算法的研究及FPGA实现.计算机工程与科学, 2008
[30]田耘,徐文波,张延伟.无线通信FPGA设计.北京:电子工业出版社, 2008