基于65nm技术平台的低功耗嵌入式SRAM设计
摘要
随着集成电路技术的发展,数据吞吐量不断上升以及系统低功耗要求,现今的系统级芯片(System-On-Chip,SOC)对存储器的需求越来越大,嵌入式存储器在SOC的面积比重逐年增加,预计到2014年会达到大约90%。因此嵌入式SRAM的集成度,速度,功耗在整个系统级芯片中的重要性变得越来越突出。所以在设计系统级芯片时选择一个合适的嵌入式SRAM是非常关键的。
芯片的速度和集成度在不断提高,功耗密度也同时显著增大,为了减小芯片的功耗、延长手持设备中电池的使用时间、降低芯片的封装及散热成本,在芯片设计和实现时必须特别考虑功耗因素。
本文主要针对嵌入式64K Bit静态嵌入式存储器的设计进行了详细的阐述。芯片采用了先进的65 nm低功耗工艺平台。由于采用了存储阵列划分、分级位线、动态译码逻辑及CMOS正反馈差分放大器等先进技术,该存储器的读写速度可达到0.717 ns。由于采用multi-block结构及自时序复位逻辑电路功动态功耗明显降低。Power gating技术的应用也使芯片的静态功耗降低38%。失效列位移失效行屏蔽技术用于存储器的内建自修复,该方案接口简单、在保持低功耗的基础上具有较快的速度、集成密度较高。
As demands for increasing performance and features are being placed upon semiconductor designers, the amount of on-chip memory continues to grow. Base on the estimation, embedded memory will occupy 90% area of the whole chip by 2014. So the density, speed and power consumption of embedded SRAM become more and more important in system level IC design. Selecting the most optimal embedded memory for the application is becoming progressively more critical to avoid performance "bottlenecks", reduce system power consumption and cost.
With the increasment of integration and speed of IC, the power per area is becoming more and more serious. In order to optimize the power consumption, enlarge the working time of mobile device in battery mode and reduce the package cost. Designer must take special consideration in the power while designing a product.
In recent years, the SRAM development trends can be summarized as fast speed, large capacity and low power. In this paper a 64Kb embedded full-CMOS SRAM is described. The design is based on the 65nm low power process. In order to improve the speed of the eSRAM, array partition, divided bit line structure and the positive feedback sense amplifier and dynamic logic are adopted. The access time of SRAM in typical condition is about 0.717ns. How to reduce the power is the key target in design, so we use the multi-block architecture and self-time reset methodologies to optimize the dynamic power consumption. Apart from that, the power gating techniques are used to control the leakage power of the chip. The simulation result shown 38% reduction is obtained. This project also provides the redundancy solution to repair defective bitcells, which is very import to improve the chip yield.
芯片的速度和集成度在不断提高,功耗密度也同时显著增大,为了减小芯片的功耗、延长手持设备中电池的使用时间、降低芯片的封装及散热成本,在芯片设计和实现时必须特别考虑功耗因素。
本文主要针对嵌入式64K Bit静态嵌入式存储器的设计进行了详细的阐述。芯片采用了先进的65 nm低功耗工艺平台。由于采用了存储阵列划分、分级位线、动态译码逻辑及CMOS正反馈差分放大器等先进技术,该存储器的读写速度可达到0.717 ns。由于采用multi-block结构及自时序复位逻辑电路功动态功耗明显降低。Power gating技术的应用也使芯片的静态功耗降低38%。失效列位移失效行屏蔽技术用于存储器的内建自修复,该方案接口简单、在保持低功耗的基础上具有较快的速度、集成密度较高。
As demands for increasing performance and features are being placed upon semiconductor designers, the amount of on-chip memory continues to grow. Base on the estimation, embedded memory will occupy 90% area of the whole chip by 2014. So the density, speed and power consumption of embedded SRAM become more and more important in system level IC design. Selecting the most optimal embedded memory for the application is becoming progressively more critical to avoid performance "bottlenecks", reduce system power consumption and cost.
With the increasment of integration and speed of IC, the power per area is becoming more and more serious. In order to optimize the power consumption, enlarge the working time of mobile device in battery mode and reduce the package cost. Designer must take special consideration in the power while designing a product.
In recent years, the SRAM development trends can be summarized as fast speed, large capacity and low power. In this paper a 64Kb embedded full-CMOS SRAM is described. The design is based on the 65nm low power process. In order to improve the speed of the eSRAM, array partition, divided bit line structure and the positive feedback sense amplifier and dynamic logic are adopted. The access time of SRAM in typical condition is about 0.717ns. How to reduce the power is the key target in design, so we use the multi-block architecture and self-time reset methodologies to optimize the dynamic power consumption. Apart from that, the power gating techniques are used to control the leakage power of the chip. The simulation result shown 38% reduction is obtained. This project also provides the redundancy solution to repair defective bitcells, which is very import to improve the chip yield.
引文
[1]ITRS,International Technology Roadmap for Semiconductors,2005 Edition.2005.
[2]ITRS,International Technology Roadmap for Semiconductors,2007 Edition.2007.
[3]Kiyoo.VLSI Memory Chip Design[M].Springer-Verlag,2001:pp6-11
[4]John P.Hansen.The Advantages of Integrated RAM[R].Advanced Micro Devices,Inc.1996
[5]Furuyama T.Trends and challenges of large scale embedded memories[A].IEEE Proceedings of Custom Integrated Circuits Conference.2005:pp 449-456
[6]Zhongyuan Wu.Zhiqiang Gao,Xiangqing He.Development Of a DEEP Submicrometer Embedded SRAM Compiler[J].IEEE,2003
[7]Denny Steele.Achieving Low Power in 65-nm Cyclone Ⅲ FPGAs[R].White Paper of Altera Corporation 2007.4
[8]Etienne Sicard,Syed Mahfuzul Aziz.Introducing 65nm Technology In Microwind3[R]Microwind Software Application Note,2006
[9]Scott E.Thompson,Mark Armstrong,Chis Auth,ect.A Logic Nanotechnology Featuring Strained-Silicon[J].IEEE Electron Device Leters,VOL.25,NO.4,2004.4
[10]J.Heidenreich et al.Copper dual damascene wiring for sub-0.25mm CMOS technology[J].IEEE International Interconnect Technology Conference,pp.151-153,1998.
[11]F.&mud,B.DurieP,B.Tavel",ect.Low Cost 65nm CMOS Platform for Low Power & General Purpose Applications[C].2004 Symposium on VLS1Technology,pp10-11,
[12]胡伟武、李国杰.纳米级工艺对微处理器设计的挑战与机遇[C]《2006-2007年计算机科学学科发展报告》,2008
[13]Ban P.Wong;Anurag Mittal;Yu Cao;Greg Starr.Nano-CMOS Circuit And Physical Design[M]USA:A JOHN WILEY & SONS,1NC,pp1-12
[14]Marinissen E J,Prince B,et al.Challenges in embedded memory design and test[C].Design,Automation and Test in Europe.2005.pp722-727
[15]K.Zhang;et al.a 3-GHz 70Mb SRAM in 65nm CMOS technology with integrated column-based dynamic power supply[C].Proc.of IEEE International Solid-State Circuit Conference(ISSCC'05),2005,pp.474-475,
[16]Kiran Gonsalves,Laxminarayan Chavani,Prakash Bangalore Prabhakar.Design and Layout of a 128-bit Static Random Access Memory[J].ECE -546VLSI SYSTEM DESIGN,2007
[17]顾明,嵌入式SRAM性能模型与优化[D]:[博士学位论文]东南大学2006
[18].T.P.Haraszti.CMOS Memory Circuits[M].Kluwer academic publishers,2001
[19]Olivier THOMAS,Amara AMARAAn.4 Transistors Self-Refresh Ultra-Low-Voltage memory cell[J].IEEE,2003
[20]G.Razavipour;A.Afzali-Kusha;and M.Pedram.Design and Analysis of Two Low Power SRAM Cell Structures[J]IEEE Transactions on VLSI Systems,2008
[21]S.Yang et.al.Low-Leakage Robust SRAM Cell Design for Sub-100nm Technologies[C].Proceedings of Asia South Pacific Design Automation Conference 2005.pp.539-544.
[22]Clement Wann;Robert Wong;David Frankt;ect,SRAM Cell Design for Stability Methodology[J].IEEE,2005
[23]Terence B.Hook;Matt Breitwisch;Jeff Brown;ect.Noise Margin and Leakage in Ultra-Low Leakage SRAM Cell Design[J].IEEE Transactions On Electron Devices,VOL.49,NO.8,2002
[24].P.M.Carter;B.R.Wilkins.Influences on Soft Error Rates in Static RAM's[J].,IEEE J.Solid-State Circuits,Vol.SC-22(3),pp.430-436,June.1987
[25]贺朝会;李国政;罗晋生;刘恩科.CMOS SRAM单粒子翻转效应的解析分析[J].半导体学报,pp174-178,2000,21(2)
[26]Behnam Amelifard;Farzan Fallah;Member;Massoud Pedram.Leakage Minimization of SRAM Cells in a Dual-Vt and Dual-Tox Technology[J].Manuscript received January 15,2007;revised May 21,2007
[27]K.Itoh et al.A Deep Sub-V,Single Power-Supply SRAM Cell with Multi-Vt,Boosted Storage Node and Dynamic Load[J].Symp.VLSI Circuits,pp.132-133,June,1996
[28]Martin Margala.Low Power SRAM Circuit Design[J].IEEE Computer Society,1999
[29]K.Kanda;S.Hattori;T.Sakurai.90%write power-saving SRAM using sense amplifying memory cell[J]. IEEE J. Solid-State Circuits, vol. 93, pp. 929-933,2004
[30] Byung-Do Yang and Lee-Sup Kim. A Low-Power SRAM Using Hierarchical Bit Line and Local Sense Amplifiers[J]. IEEE, 2005
[31] Jeanne P. Bickford; Raymond Rosner; Erik Hedberg; Joseph W. Yoder; Thomas S. Barnett. SRAM Redundancy - Silicon Area versus Number of Repairs Trade-off[C] 2008 IEEE/SEMI Advanced Semiconductor Manufacturing Conference
[32] Tao Peng; Greg Landry. Design Base Yield And Redundancy Model For High Density Dual port SRAM On 90nm Technology[J]. IEEE, 2004
[2]ITRS,International Technology Roadmap for Semiconductors,2007 Edition.2007.
[3]Kiyoo.VLSI Memory Chip Design[M].Springer-Verlag,2001:pp6-11
[4]John P.Hansen.The Advantages of Integrated RAM[R].Advanced Micro Devices,Inc.1996
[5]Furuyama T.Trends and challenges of large scale embedded memories[A].IEEE Proceedings of Custom Integrated Circuits Conference.2005:pp 449-456
[6]Zhongyuan Wu.Zhiqiang Gao,Xiangqing He.Development Of a DEEP Submicrometer Embedded SRAM Compiler[J].IEEE,2003
[7]Denny Steele.Achieving Low Power in 65-nm Cyclone Ⅲ FPGAs[R].White Paper of Altera Corporation 2007.4
[8]Etienne Sicard,Syed Mahfuzul Aziz.Introducing 65nm Technology In Microwind3[R]Microwind Software Application Note,2006
[9]Scott E.Thompson,Mark Armstrong,Chis Auth,ect.A Logic Nanotechnology Featuring Strained-Silicon[J].IEEE Electron Device Leters,VOL.25,NO.4,2004.4
[10]J.Heidenreich et al.Copper dual damascene wiring for sub-0.25mm CMOS technology[J].IEEE International Interconnect Technology Conference,pp.151-153,1998.
[11]F.&mud,B.DurieP,B.Tavel",ect.Low Cost 65nm CMOS Platform for Low Power & General Purpose Applications[C].2004 Symposium on VLS1Technology,pp10-11,
[12]胡伟武、李国杰.纳米级工艺对微处理器设计的挑战与机遇[C]《2006-2007年计算机科学学科发展报告》,2008
[13]Ban P.Wong;Anurag Mittal;Yu Cao;Greg Starr.Nano-CMOS Circuit And Physical Design[M]USA:A JOHN WILEY & SONS,1NC,pp1-12
[14]Marinissen E J,Prince B,et al.Challenges in embedded memory design and test[C].Design,Automation and Test in Europe.2005.pp722-727
[15]K.Zhang;et al.a 3-GHz 70Mb SRAM in 65nm CMOS technology with integrated column-based dynamic power supply[C].Proc.of IEEE International Solid-State Circuit Conference(ISSCC'05),2005,pp.474-475,
[16]Kiran Gonsalves,Laxminarayan Chavani,Prakash Bangalore Prabhakar.Design and Layout of a 128-bit Static Random Access Memory[J].ECE -546VLSI SYSTEM DESIGN,2007
[17]顾明,嵌入式SRAM性能模型与优化[D]:[博士学位论文]东南大学2006
[18].T.P.Haraszti.CMOS Memory Circuits[M].Kluwer academic publishers,2001
[19]Olivier THOMAS,Amara AMARAAn.4 Transistors Self-Refresh Ultra-Low-Voltage memory cell[J].IEEE,2003
[20]G.Razavipour;A.Afzali-Kusha;and M.Pedram.Design and Analysis of Two Low Power SRAM Cell Structures[J]IEEE Transactions on VLSI Systems,2008
[21]S.Yang et.al.Low-Leakage Robust SRAM Cell Design for Sub-100nm Technologies[C].Proceedings of Asia South Pacific Design Automation Conference 2005.pp.539-544.
[22]Clement Wann;Robert Wong;David Frankt;ect,SRAM Cell Design for Stability Methodology[J].IEEE,2005
[23]Terence B.Hook;Matt Breitwisch;Jeff Brown;ect.Noise Margin and Leakage in Ultra-Low Leakage SRAM Cell Design[J].IEEE Transactions On Electron Devices,VOL.49,NO.8,2002
[24].P.M.Carter;B.R.Wilkins.Influences on Soft Error Rates in Static RAM's[J].,IEEE J.Solid-State Circuits,Vol.SC-22(3),pp.430-436,June.1987
[25]贺朝会;李国政;罗晋生;刘恩科.CMOS SRAM单粒子翻转效应的解析分析[J].半导体学报,pp174-178,2000,21(2)
[26]Behnam Amelifard;Farzan Fallah;Member;Massoud Pedram.Leakage Minimization of SRAM Cells in a Dual-Vt and Dual-Tox Technology[J].Manuscript received January 15,2007;revised May 21,2007
[27]K.Itoh et al.A Deep Sub-V,Single Power-Supply SRAM Cell with Multi-Vt,Boosted Storage Node and Dynamic Load[J].Symp.VLSI Circuits,pp.132-133,June,1996
[28]Martin Margala.Low Power SRAM Circuit Design[J].IEEE Computer Society,1999
[29]K.Kanda;S.Hattori;T.Sakurai.90%write power-saving SRAM using sense amplifying memory cell[J]. IEEE J. Solid-State Circuits, vol. 93, pp. 929-933,2004
[30] Byung-Do Yang and Lee-Sup Kim. A Low-Power SRAM Using Hierarchical Bit Line and Local Sense Amplifiers[J]. IEEE, 2005
[31] Jeanne P. Bickford; Raymond Rosner; Erik Hedberg; Joseph W. Yoder; Thomas S. Barnett. SRAM Redundancy - Silicon Area versus Number of Repairs Trade-off[C] 2008 IEEE/SEMI Advanced Semiconductor Manufacturing Conference
[32] Tao Peng; Greg Landry. Design Base Yield And Redundancy Model For High Density Dual port SRAM On 90nm Technology[J]. IEEE, 2004