高速低功耗嵌入式SRAM的设计研究
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摘要
随着半导体制造工艺和集成电路设计能力的不断提高,人们已经能够把包括处理器、存储器、模拟电路、接口逻辑甚至射频电路集成到一个芯片上,形成所谓的SoC(系统级芯片)。资料表明,作为SoC重要组成部分的嵌入式存储器,在SoC中所占的比重(面积)逐年增加,由1999年平均20%的芯片面积上升到2007年60-70%乃至2014年的90%的面积。由此可见,嵌入式存储器的优劣对整个芯片系统来说至关重要。嵌入式静态随机存储器(eSRAM)由于其功耗低、速度快、性能稳定等优点而成为嵌入式存储器中不可或缺的重要组成部分,它在改善系统性能、提高芯片可靠性、降低成本与功耗等方面都起到了积极的作用。
本文主要以一个128Kbit(4Kx32位)嵌入式静态存储器的设计为例,对低功耗嵌入式SRAM的设计进行了阐述。该存储器采用了先进的65nm制作工艺。设计中采用了SCL(source-coupled-logic)结构的动态CMOS译码电路、脉冲信号技术、锁存型电压灵敏放大器、Power Gating、存储阵列分割等先进技术。SCL动态CMOS译码电路不仅加快了译码速度,而且相对于传统的译码电路来说面积要小得多；脉冲信号技术可以减少字线、位线以及外围电路的使能时间,从而提高芯片性能,降低功耗；锁存型电压灵敏放大器的应用不仅提高了读取速度而且降低了功耗；Power gating技术使存储器的静态功耗降低了将近47%左右；存储阵列分割技术的主要目标是使信号局域化,以减少开关电容,从而降低延时及功耗。但存储阵列分割使整体芯片面积增大,同时带来了过多的互连线延时,过分的划分存储阵列可能使得eSRAM性能降低。因此在进行存储阵列分割时应当评估其划分后的性能,以求获得最佳的符合设计要求的层次化结构。
With the improvement of semiconductor manufacturing process and IC design capability, various types of circuits including processors memory、analog circuit、I/O logic and RF(radio-frequency) circuit have already been integrated into one chip, which is called SoC (system-on-chip). By statistics, as an important part, Embedded memory gets a growing area proportion in SoC, which increases from 20% in 1999 to 60%-70% in 2007, and will be 90% in 2014 by estimation. Hence we can see that embedded memory plays a critical role in the whole chip. Embedded static RAM is a well known embedded memory due to its low power consumption, fast speed and stability. It can help to improve system performance and reliability, and lower the cost and power consumption.
In this paper,128Kbit(4Kx32) embedded static RAM is used as an example to describe how to design a low power embedded static RAM. Advanced 65nm process is used in the fabrication of the memory. Advanced technologies, such as dynamic CMOS decoder which using SCL(source-coupled-logic) circuits, pulse signal technology, latch type voltage sense amplifier, power gating, memory array segmentation are used in the design. SCL dynamic CMOS interpretation circuit not only speeds up the interpretation, but also occupies much smaller area than traditionally used interpretation circuit. Pulse signal technology can reduce enabling time of word line, bit line and peripheral circuit, so that can improve system performance and lower power consumption. Latch type voltage sense amplifier can not only speed up read/write but also cut down the power consumption. Power gating reduces the static power consumption by 47%. Memory array segmentation localizes the signal, which reduces the switched capacitor. As a result, the delay and power consumption can be reduced. However, memory array segmentation will lead to the increase of the chip area, as well as delay due to too much connection. So using memory array segmentation too much will cause the decrease of memory performance. When memory array segmentation is used, performance should be taken into consideration so that an optimum hierarchical structure can be achieved.
本文主要以一个128Kbit(4Kx32位)嵌入式静态存储器的设计为例,对低功耗嵌入式SRAM的设计进行了阐述。该存储器采用了先进的65nm制作工艺。设计中采用了SCL(source-coupled-logic)结构的动态CMOS译码电路、脉冲信号技术、锁存型电压灵敏放大器、Power Gating、存储阵列分割等先进技术。SCL动态CMOS译码电路不仅加快了译码速度,而且相对于传统的译码电路来说面积要小得多；脉冲信号技术可以减少字线、位线以及外围电路的使能时间,从而提高芯片性能,降低功耗；锁存型电压灵敏放大器的应用不仅提高了读取速度而且降低了功耗；Power gating技术使存储器的静态功耗降低了将近47%左右；存储阵列分割技术的主要目标是使信号局域化,以减少开关电容,从而降低延时及功耗。但存储阵列分割使整体芯片面积增大,同时带来了过多的互连线延时,过分的划分存储阵列可能使得eSRAM性能降低。因此在进行存储阵列分割时应当评估其划分后的性能,以求获得最佳的符合设计要求的层次化结构。
With the improvement of semiconductor manufacturing process and IC design capability, various types of circuits including processors memory、analog circuit、I/O logic and RF(radio-frequency) circuit have already been integrated into one chip, which is called SoC (system-on-chip). By statistics, as an important part, Embedded memory gets a growing area proportion in SoC, which increases from 20% in 1999 to 60%-70% in 2007, and will be 90% in 2014 by estimation. Hence we can see that embedded memory plays a critical role in the whole chip. Embedded static RAM is a well known embedded memory due to its low power consumption, fast speed and stability. It can help to improve system performance and reliability, and lower the cost and power consumption.
In this paper,128Kbit(4Kx32) embedded static RAM is used as an example to describe how to design a low power embedded static RAM. Advanced 65nm process is used in the fabrication of the memory. Advanced technologies, such as dynamic CMOS decoder which using SCL(source-coupled-logic) circuits, pulse signal technology, latch type voltage sense amplifier, power gating, memory array segmentation are used in the design. SCL dynamic CMOS interpretation circuit not only speeds up the interpretation, but also occupies much smaller area than traditionally used interpretation circuit. Pulse signal technology can reduce enabling time of word line, bit line and peripheral circuit, so that can improve system performance and lower power consumption. Latch type voltage sense amplifier can not only speed up read/write but also cut down the power consumption. Power gating reduces the static power consumption by 47%. Memory array segmentation localizes the signal, which reduces the switched capacitor. As a result, the delay and power consumption can be reduced. However, memory array segmentation will lead to the increase of the chip area, as well as delay due to too much connection. So using memory array segmentation too much will cause the decrease of memory performance. When memory array segmentation is used, performance should be taken into consideration so that an optimum hierarchical structure can be achieved.
引文
[1]薛霆,李红.嵌入式存储器发展现状[J].中国集成电路,2007,16(10)：2.
[2]汪东.嵌入式存储器面面观[J].今日电子,2005,(12)：
[3]顾明.嵌入式SRAM性能模型与优化[D].南京：东南大学,2006：
[4]JanM. Rabaey, Ananthachandrakasan.数字集成电路—电路、系统与设计[M].北京：电子工业出版社,2004：
[5]Kaushik Roy, Sharat Prasad. Low-Power Cmos Vlsi Circuit Design [M]. New York:A Wiley Interscience Publication,2000:
[6]Ashok K. Sharma先进半导体存储器—结构、设计与应用[M].北京：电子工业出版社,2005：
[7]David A. Hodges, Horace G. Jackson, Resve A. Saleh数字集成电路分析与设计—深亚微米工艺(第三版)[M].北京：电子工业出版社,2005.9
[8]Kerry Bernstein, Keith M. Carrig. High Speed Cmos Design Styles[M].Boston:Kluwer Academic Publishers,1998:
[9]Hiroaki Nambu, Kazuo Kanetani. A 1.8ns Access,550-MHz,4.5-Mb CMOS SRAM[J]. IEEE Journal of Solid-State Circuits,1998,33(11):1650-1657
[10]Synopsys Low-Power Flow User Guide, Version B-2008.09, September 2008
[11]Lohstroh J, Seevinck E, De Groot J D. Worst-Case Static Noise Margin criteria for logic circuits and their mathematical equivalence[J].IEEE Journal of Solid-State Circuits,1983,18(6):803-806
[12]S Lakshminarayananl, J Joungl, G Narasimhanl. Standby Power Reduction and SRAM Cell Optimization for 65nm Technology [J]. IEEE Quality of Electronic Design,2009,4(3):471-475
[13]田虹.嵌入式128Kb SRAM的设计与研究[D].西安：西北大学,2003：
[14]吕韬.高速低功耗嵌入式SRAM的设计与优化[D].长沙：国防科学技术大学,2009：
[15]Behzad Razavi模拟CMOS集成电路设计[M].西安：西安交通大学出版社,2002.12
[16]S.Yang et.al. Low-Leakage Robust SRAM Cell Design for Sub-100nm Technologies[C]. Proceedings of Asia South Pacific Design Automation Conference 2005:539-544.
[17]Clement Wann, Robert Wong, David Frankt, etc. SRAM Cell Design for Stability Methodology[J]. IEEE,2005
[18]Seevinck E, List F J, Lohstroh H J, Static-Noise Margin Analysis of MOS SRAM Cells[J]. IEEE Journal of Solid State Circuits,1987,22(5): 748-754.
[19]Behnam Amelifard, Farzan Fallah, Member, Massoud Pedram, Leakage Minimization of SRAM Cells in a Dual-Vt and Dual-Tox Technology[J]. Manuscript received January 15,2007:revised May 21,2007
[20]K.Itoh et al. A Deep Sub-V, Single Power-Supply SRAM Cell with Multi-Vt, Boosted Storage Node and Dynamic Load[J], Symp. VLSI Circuits,1996:132-133
[21]Hiroshi Kawaguchi. Dynamic Leakage Cut-off Scheme for Low-Voltage SRAMs. Symposium on VLSI Circuit Digest of Technical Papers,1998
[2]汪东.嵌入式存储器面面观[J].今日电子,2005,(12)：
[3]顾明.嵌入式SRAM性能模型与优化[D].南京：东南大学,2006：
[4]JanM. Rabaey, Ananthachandrakasan.数字集成电路—电路、系统与设计[M].北京：电子工业出版社,2004：
[5]Kaushik Roy, Sharat Prasad. Low-Power Cmos Vlsi Circuit Design [M]. New York:A Wiley Interscience Publication,2000:
[6]Ashok K. Sharma先进半导体存储器—结构、设计与应用[M].北京：电子工业出版社,2005：
[7]David A. Hodges, Horace G. Jackson, Resve A. Saleh数字集成电路分析与设计—深亚微米工艺(第三版)[M].北京：电子工业出版社,2005.9
[8]Kerry Bernstein, Keith M. Carrig. High Speed Cmos Design Styles[M].Boston:Kluwer Academic Publishers,1998:
[9]Hiroaki Nambu, Kazuo Kanetani. A 1.8ns Access,550-MHz,4.5-Mb CMOS SRAM[J]. IEEE Journal of Solid-State Circuits,1998,33(11):1650-1657
[10]Synopsys Low-Power Flow User Guide, Version B-2008.09, September 2008
[11]Lohstroh J, Seevinck E, De Groot J D. Worst-Case Static Noise Margin criteria for logic circuits and their mathematical equivalence[J].IEEE Journal of Solid-State Circuits,1983,18(6):803-806
[12]S Lakshminarayananl, J Joungl, G Narasimhanl. Standby Power Reduction and SRAM Cell Optimization for 65nm Technology [J]. IEEE Quality of Electronic Design,2009,4(3):471-475
[13]田虹.嵌入式128Kb SRAM的设计与研究[D].西安：西北大学,2003：
[14]吕韬.高速低功耗嵌入式SRAM的设计与优化[D].长沙：国防科学技术大学,2009：
[15]Behzad Razavi模拟CMOS集成电路设计[M].西安：西安交通大学出版社,2002.12
[16]S.Yang et.al. Low-Leakage Robust SRAM Cell Design for Sub-100nm Technologies[C]. Proceedings of Asia South Pacific Design Automation Conference 2005:539-544.
[17]Clement Wann, Robert Wong, David Frankt, etc. SRAM Cell Design for Stability Methodology[J]. IEEE,2005
[18]Seevinck E, List F J, Lohstroh H J, Static-Noise Margin Analysis of MOS SRAM Cells[J]. IEEE Journal of Solid State Circuits,1987,22(5): 748-754.
[19]Behnam Amelifard, Farzan Fallah, Member, Massoud Pedram, Leakage Minimization of SRAM Cells in a Dual-Vt and Dual-Tox Technology[J]. Manuscript received January 15,2007:revised May 21,2007
[20]K.Itoh et al. A Deep Sub-V, Single Power-Supply SRAM Cell with Multi-Vt, Boosted Storage Node and Dynamic Load[J], Symp. VLSI Circuits,1996:132-133
[21]Hiroshi Kawaguchi. Dynamic Leakage Cut-off Scheme for Low-Voltage SRAMs. Symposium on VLSI Circuit Digest of Technical Papers,1998