MIMO-OFDM系统中的几个关键算法的VLSI结构设计
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摘要
当信号经过无线信道传输，发射机和接收机产生的噪声和障碍物引起多径传播会严重的降低接收信号的质量，伴随着接收机的高速移动，使得信息更加难以可靠的接收。因此许多先进的技术不得不应用于高速率、快速移动的无线通信系统，例如MIMO多天线、正交频分复用和迭代译码技术等。与此同时，这些算法也增加了接收机的计算复杂度。人们试图寻找优良的VLSI算法实现，期望同时满足性能要求、低成本和低功耗。
本文针对MIMO-OFDM无线通信系统中的几个关键算法的VLSI设计做了系统和深入的研究，取得了以下关键性成果：
1.针对3GPP LTE中正交频分复用调制时所需的快速傅里叶变换，提出了一种采用时分复用控制策略的单蝶形VLSI结构。核心电路由一个混合基蝶形计算单元和一个CORDIC坐标旋转数字计算器组成，避免了传统FFT计算中的乘法运算。通过仔细设计规则的流水线电路结构，使得核心计算电路中的所有寄存器之间的组合电路的关键路径趋于一致，利用动态电压和频率调整技术，可以优化功耗管理。
2.针对2×2天线配置的多输入多输出无线通信系统,提出了一种新颖的近最大似然MIMO检测算法，该算法只对搜索树的第二层节点耗尽搜索，第一层应用提出的区域判定法直接得到假设星座点和反假设点，不需要对每一层搜索树的部分欧几里德距离排序。依据此算法设计了低复杂度且规则的VLSI结构，可以配置并行检测核的数目取得灵活的吞吐率控制。
3.针对采用最大后验概率算法的Turbo译码器,提出了一种前向、后向度量计算和存储器管理的策略，通过在前向状态度量计算时对部分度量值等间隔抽取存储，然后在对数似然比计算时经过内插还原出未存储的状态度量值，减少了状态度量存储单元，从而降低VLSI实现面积和功耗。
4.针对3GPP LTE标准中的Turbo码，设计了一种基于最大后验概率算法的低功耗并行译码器。根据二次置换多项式交织器的数学特性，分解并行处理中每个译码器的交织地址为子码块地址和块内偏移地址，提出一种递归计算子码块交织地址的算法，使得并行度可以为任意值，而不仅仅限于2的幂次。并依此设计了低复杂度的实时递归计算交织器的互连结构，以避免传统实现方法中对交织地址的存储，简化了Turbo译码器本征信息处理的互连网络，减小了实现面积和功耗。
As a signal propagates through a wireless channel, it experiences random fuctuationsin time if the transmitter, receiver, or surrounding objects are moving with high speed.Thus, some advanced technologies, such as multi-antennas MIMO system, OFDM anditerative decoding algorithms, are adopted for the high speed wireless communicationsystems to gain the best performance. However, the penalty is the strong requirement oncomputation complexity in the receiver. In the last decade, people spent huge efort onthese algorithm’s VLSI implementation to meet the low cost, low power and maintainingthe acceptable performance.
This dissertation focus on the VLSI implementation of MIMO spatial multiplexer de-tection, Turbo decoding and FFT processor in the MIMO-OFDM wireless communicationsystems. Some promising results are presented as follows:
1. Targeted to the fast fourier transform for the orthogonal frequency-division multi-plexing technique in3GPP LET standard, this paper proposes a single butterfyVLSI architecture with the strategy to time division multiplexing the hardwarerotation digital calculation unit. Here the traditional multiply operation fortwiddle factor is avoided. With respect to the regular and pipeline circuit archi-tecture, the combination circuits path between registers are well balanced, whichleading to the dynamic voltage and frequency can be applied for the optimizedpower management.
2. A novel maximum likelihood-like detection algorithm for the2×2MIMO wirelesscommunication system is proposed for that only the second layer in the searchtree needs to be verifed exhaustively, and then applying the area determinationstrategy to the frst layer to fgure out the hypothesis node and counter-hypothesisnodes without sorting the partial Euclidean distance for each layer, which reducesthe complexity signifcantly. The regular VLSI architecture is designed accordingto the detection algorithm, and fexible parallelism can well control the throughputfor versatile applications.
3. A novel forward and backward state metric calculation and the memory managementstrategy is presented for the turbo decoder which adopted the Log-MAP(MaximumA-Posteriori) algorithm. By the way of decimating the forward state metric atfrst and then interpolating during the LLR(Log Likelihood Ratio) computationstage to reduce the state metric memory size, which acquired signifcant power and area beneft with ignorable computation penalty. And the soft in soft outscheduling and control mechanism are also addressed for the supporting of ourproposed optimization architecture.
4. A parallel-structured turbo decoder based on the maximum a-posteriori algorithm isdesigned for the3GPP LTE system. Taking advantage of the mathematic propertyof the quadratic permutation polynomial, the address of each interleaver, in theparallel processing structure, is separated into two parts, block address and ofsetaddress in that block. An recursive algorithm is developed to calculate these twoaddresses in a parallel decoder，which leads to the parallelism can be any value,breaking the limitation of the power of2. Based on the developed algorithm arecursive VLSI architecture is presented, which signifcantly simplifes the extrinsicinformation interconnecting networks and avoids the usage of interleaver storagememory in the conventional approach.
本文针对MIMO-OFDM无线通信系统中的几个关键算法的VLSI设计做了系统和深入的研究，取得了以下关键性成果：
1.针对3GPP LTE中正交频分复用调制时所需的快速傅里叶变换，提出了一种采用时分复用控制策略的单蝶形VLSI结构。核心电路由一个混合基蝶形计算单元和一个CORDIC坐标旋转数字计算器组成，避免了传统FFT计算中的乘法运算。通过仔细设计规则的流水线电路结构，使得核心计算电路中的所有寄存器之间的组合电路的关键路径趋于一致，利用动态电压和频率调整技术，可以优化功耗管理。
2.针对2×2天线配置的多输入多输出无线通信系统,提出了一种新颖的近最大似然MIMO检测算法，该算法只对搜索树的第二层节点耗尽搜索，第一层应用提出的区域判定法直接得到假设星座点和反假设点，不需要对每一层搜索树的部分欧几里德距离排序。依据此算法设计了低复杂度且规则的VLSI结构，可以配置并行检测核的数目取得灵活的吞吐率控制。
3.针对采用最大后验概率算法的Turbo译码器,提出了一种前向、后向度量计算和存储器管理的策略，通过在前向状态度量计算时对部分度量值等间隔抽取存储，然后在对数似然比计算时经过内插还原出未存储的状态度量值，减少了状态度量存储单元，从而降低VLSI实现面积和功耗。
4.针对3GPP LTE标准中的Turbo码，设计了一种基于最大后验概率算法的低功耗并行译码器。根据二次置换多项式交织器的数学特性，分解并行处理中每个译码器的交织地址为子码块地址和块内偏移地址，提出一种递归计算子码块交织地址的算法，使得并行度可以为任意值，而不仅仅限于2的幂次。并依此设计了低复杂度的实时递归计算交织器的互连结构，以避免传统实现方法中对交织地址的存储，简化了Turbo译码器本征信息处理的互连网络，减小了实现面积和功耗。
As a signal propagates through a wireless channel, it experiences random fuctuationsin time if the transmitter, receiver, or surrounding objects are moving with high speed.Thus, some advanced technologies, such as multi-antennas MIMO system, OFDM anditerative decoding algorithms, are adopted for the high speed wireless communicationsystems to gain the best performance. However, the penalty is the strong requirement oncomputation complexity in the receiver. In the last decade, people spent huge efort onthese algorithm’s VLSI implementation to meet the low cost, low power and maintainingthe acceptable performance.
This dissertation focus on the VLSI implementation of MIMO spatial multiplexer de-tection, Turbo decoding and FFT processor in the MIMO-OFDM wireless communicationsystems. Some promising results are presented as follows:
1. Targeted to the fast fourier transform for the orthogonal frequency-division multi-plexing technique in3GPP LET standard, this paper proposes a single butterfyVLSI architecture with the strategy to time division multiplexing the hardwarerotation digital calculation unit. Here the traditional multiply operation fortwiddle factor is avoided. With respect to the regular and pipeline circuit archi-tecture, the combination circuits path between registers are well balanced, whichleading to the dynamic voltage and frequency can be applied for the optimizedpower management.
2. A novel maximum likelihood-like detection algorithm for the2×2MIMO wirelesscommunication system is proposed for that only the second layer in the searchtree needs to be verifed exhaustively, and then applying the area determinationstrategy to the frst layer to fgure out the hypothesis node and counter-hypothesisnodes without sorting the partial Euclidean distance for each layer, which reducesthe complexity signifcantly. The regular VLSI architecture is designed accordingto the detection algorithm, and fexible parallelism can well control the throughputfor versatile applications.
3. A novel forward and backward state metric calculation and the memory managementstrategy is presented for the turbo decoder which adopted the Log-MAP(MaximumA-Posteriori) algorithm. By the way of decimating the forward state metric atfrst and then interpolating during the LLR(Log Likelihood Ratio) computationstage to reduce the state metric memory size, which acquired signifcant power and area beneft with ignorable computation penalty. And the soft in soft outscheduling and control mechanism are also addressed for the supporting of ourproposed optimization architecture.
4. A parallel-structured turbo decoder based on the maximum a-posteriori algorithm isdesigned for the3GPP LTE system. Taking advantage of the mathematic propertyof the quadratic permutation polynomial, the address of each interleaver, in theparallel processing structure, is separated into two parts, block address and ofsetaddress in that block. An recursive algorithm is developed to calculate these twoaddresses in a parallel decoder，which leads to the parallelism can be any value,breaking the limitation of the power of2. Based on the developed algorithm arecursive VLSI architecture is presented, which signifcantly simplifes the extrinsicinformation interconnecting networks and avoids the usage of interleaver storagememory in the conventional approach.
引文
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